EE105 Fall 2015 Microelectronic Devices and Circuits: MOSFET Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 7-1
Simplest Model of MOSFET (from EE16B) 7-2
CMOS Inverter 7-3
CMOS NAND Gate 7-4
More Circuit Symbol for NMOS 4 terminal including Body (Arrow pointing to channel indicating substrate is p-type) Modified circuit symbol with arrow on source (Arrow indicating direction of current flow) Simplified circuit symbol with body connected to source (or when the effect of the body on device operation is unimportant) Note in NMOS 1. Drain voltage is always more positive than Source voltage 2. Current always flows from Drain to Source 7-5
More Circuit Symbol of PMOS 4 terminal including Body (Arrow pointing away from channel indicating substrate is n-type) Modified circuit symbol with arrow on source (Arrow indicating direction of current flow) Simplified circuit symbol with body connected to source (or when the effect of the body on device operation is unimportant) Note in PMOS 1. Source voltage is always more positive than Drain voltage 2. Current always flows from Source to Drain 3. Source is usually drawn on top so current flows downward (convention) 7-6
Analog Voltage Amplifier DC bias at Quiescent (Q) point Small-signal input superimposed on a DC bias voltage Symbol used in this course: vv GGGG = VV GGGG + vv gggg Need to know the transistor s I-V characteristics to find the voltage gain (and other properties of the amplifier) 7-7
I-V Curves of NMOS (for fixed Gate Voltage) id Current flows when vv GGGG > VV tttt (threshold voltage) vv GGGG,44 vv GGGG,33 vv GGGG,22 vv GGGG,11 vv DDDD 7-8
Drain Current vs Gate Voltage id = 11 22 kk nn vv GGGG VV tttt 22 Square Law V tn v GS 7-9
MOSFET Device Structure MOSFET: metal-oxide-semiconductor field effect transistor Typically Channel length: L ~ < 10 nm to 0.35 μm, Channel width: W ~ 0.05 μm to 100 μm, Oxide thickness: t ox ~ 1 to 10 nm 7-10
NMOSFET (or simply NMOS) N-channel MOSFET Current conducted by electrons 3 terminal device Source (S): n+ (heavily n-type) Drain (D): n+ Gate (G): metal deposited on insulator above channel Substrate (called Body ) is a 4 th terminal Substrate is p-doped Electrons is induced in channel when a positive gate voltage is applied Electrons moves from Source to Drain Current flows from D to S 7-11
Creating a Channel for Current Flow MOS is a capacitor across an insulator (oxide) When a positive voltage is applied at Gate, electrons are induced under the gate. At "thresold", sufficient number of electrons form a "channel" between Source and Drain, forming a conductive channel. Total charge in the channel: Q = C ox WL v GS V t where C ox = ε ox t ox ( ) is oxide capacitance per unit area ε ox = 3.9ε 0 = 3.9 8.854 10 12 F/m W : gate width L : gate length V t : Threshold voltage v GS V t v OV is called "Overdrive Voltage" 7-12
Large-Signal Model (usually used to solve DC bias voltage and current) 7-13
Current at Small v DS When v OV = v GS V t > 0, a channel is formed between Source and Drain. Linear charge density in channel: Q L = C ox W v OV Electric field along the channel E = v DS L Drain current = charge density x velocity: = Q L v n = Q L µ n E = C ox W v OV µ n v DS L = µ n C ox W L v OVv DS At small v DS, the transistor is like a gate-controlled variable resistor 7-14
Current at Small v DS = µ n C ox W L v OVv DS k n ' = k n ' W L v OVv DS = k n v OV v DS where = µ n C ox : process transconducance paramter k n = µ n C ox W L : MOSFET transconductance parameter MOSFET behaves like a linear resistor r DS = v DS = 1 k n v OV Resistance value can be changed by gate voltage (overdrive voltage) 7-15
Triode Region (v DS < v OV ) As v DS increases, the potential in the channel is no longer a constant. Assume the channel is v(x) : = C ox W ( v GS v(x) V t )v n (x) v n (x) = µ n E(x) = µ n dv(x) dx Note: is still constant along the channel (think Kirchhoff's Current Law) Integrate along the channel x=l dx = x=0 x=l x=0 # dv(x) & % C ox W ( v GS v(x) V t )µ n ( dx $ dx ' Change of variable on right-hand side: x v L = v=v DS v=0 = µ n C ox W L ( C ox W ( v OV v)µ n ) dv # % $ v v 1 OV DS 2 v 2 DS & ( ' 7-16
Triode Region (v DS < v OV ) When 0 v DS v OV W # = µ n C ox L v v 1 OV DS 2 v 2 & % DS ( $ ' This is called the "Triode Region" 7-17
Pinch-Off The channel potential at the drain side is v DS. When v DS = v OV, the local charge density there Q ( v GS v DS V t ) = C ox ( v OV v DS ) = 0 area = C ox So the channel is "pinched off" near the Drain. Once the channel is pinched off, the drain current remains constant: = 1 2 µ W nc ox L v 2 OV This region, v DS > v OV, is called "Saturation" 7-18
Saturation Region (v DS > v OV ) When 0 v DS v OV W # = µ n C ox L v v 1 OV DS 2 v 2 & % DS ( $ ' This is called the "Triode Region" When v DS > v OV, = 1 2 µ W nc ox L v 2 OV This is called "Saturation Region" 7-19
Full I-V Curves of NMOSFET 7-20 V tn : threshold voltage of NMOS
Drain Current vs Gate Voltage In Saturation Region = 1 2 µ W nc ox L v 2 OV = 1 2 µ n C ox W ( L v V GS tn) 2 To experimentally determine V tn : Measure and plot versus v GS = 1 2 µ C W n ox ( L v V GS tn) V tn = intercept with horizontal axis V tn v GS 7-21
PMOSFET (or simply PMOS) P-channel MOSFET Current conducted by holes 3 terminal device Source (S): p+ (heavily p-type) Drain (D): p+ Gate (G): metal deposited on insulator above channel Substrate (called Body ) is a 4 th terminal Substrate is n-doped Holes is induced in channel when a negative gate voltage is applied Holes moves from Source to Drain Current flows from S to D 7-22
CMOS (Complementary MOS) CMOS is the prevalent IC technology today Since NMOS and PMOS are formed on oppositely doped substrates, one of the transistor needs to be placed in a well PMOS is placed in an n well here. Alternatively, NMOS can be placed in p well 7-23