Low Power SOC Sensor Interface Design for High Temperature Applications - Doctor of Philosophy Thesis Proposal

Low Power SOC Sensor Interface Design for High Temperature Applications - Doctor of Philosophy Thesis Proposal Nima Sadeghi nimas@ece.ubc.ca Department of Electrical and Computer Engineering University of British Columbia Co-supervisors: Dr. Shahriar Mirabbasi and Dr. Chad P.J. Bennington May 1, 2009 i

Contents 1 Introduction and Overview 1 1.1 Improvement in Pulp and Paper Digester Operation Efficiency........... 1 1.2 State-of-the-Art Background Survey on High Temperature Circuit Design..... 2 1.3 High Temperature Considerations.......................... 3 1.3.1 Mobility Variation over Temperature..................... 4 1.3.2 Threshold Voltage Variation over Temperature............... 5 1.3.3 Junction (Reverse-Biased Diode) Leakage Current............. 6 1.4 High Temperature Compensation Techniques.................... 8 2 Fabricated SmartChip Building Blocks using 0.13 µm Bulk CMOS Technology 9 2.1 Bias Circuit Implementation............................. 9 2.1.1 Supply-Independent Bootstrapped Design.................. 9 2.1.2 Supply-Independent Start-Up for Bootstrap................. 10 2.1.3 Bias Circuit Design.............................. 10 2.1.4 Bias Circuit Simulation Results....................... 12 2.2 Amplifier Implementation.............................. 15 2.2.1 Folded Cascode Amplifier Design...................... 15 2.2.2 Amplifier Simulation Results......................... 16 2.2.3 Amplifier Performance Comparison..................... 18 2.3 Voltage Reference Implementation.......................... 19 2.3.1 Negative Temperature Coefficient Voltage.................. 20 2.3.2 Positive Temperature Coefficient Voltage.................. 20 2.3.3 Bandgap Reference.............................. 20 2.3.4 Bandgap Voltage Reference Design..................... 21 2.3.5 Bandgap Voltage Reference Simulation Results............... 22 2.4 Oscillator Implementation.............................. 24 2.4.1 Oscillator Delay Cell Design......................... 26 2.4.2 Oscillator Simulation Results........................ 26 2.5 Additional Temperature Testing Blocks....................... 28 3 Conclusion and Future Work 28 3.1 Overview....................................... 28 3.2 Planned Work..................................... 29 ii

1 Introduction and Overview Reliable electronics operation at high temperature environments is required for several applications including automotive sensors and electronics, oil field devices, and multi-phase chemical reactors used in pulp and paper industry as shown in Fig 1. Our target application is the pulp and paper industry, in which they need to optimize the process at high temperature operation up to 180 C by obtaining the temperature and pressure inside their digester though the process. Therefore they require data acquisition on the operating conditions at high temperature which introduces new challenges. Implementing a chip to provide such data results an increase of the operational efficiency of pulp and paper digester up to 5%. It is worthwhile to notice that in Canada only a 1% improvement in digester operation efficiency is worth $80 million/year. High Temperature Pulp and Paper Industry Automotive sensors and electronics ctor of 2 Drop of threshold voltage from 25 C to 250 C Multi-phase Oil field devices chemical reactors Figure 1: Some application examples that require electronic circuitry operating at high temperature. 1.1 Improvement in Pulp and Paper Digester Operation Efficiency Our intention is to implement a smart sensor device for data acquisition within Kraft Pulp Digester, the results of which are expected to improve digester operational efficiency by up to 5%. We plan to build an entire System-On-Chip (SOC) data acquisition device, called SmartChip, able to withstand high temperature operation, up to 180 C for several hours. The implementation of such a smart sensor platform has not been addressed in the past, but we know how to do it and are trying to use the knowledge for high temperature design [1]-[8] to implement the smart chip. In contrast to other published work [1]-[8] our first intention is to minimize the power consumption of our design using more recent 0.13 µm CMOS technologies with 2.5 V supply voltage. The low power/voltage requirements are due to autonomous battery operation and small size imposed by the proposed application. The entire sensor chip size needs to be at most about a match box, 1

the same size of a wood chip used in digester. Although individual electronic components are available that could withstand the process conditions, they would need to be packaged together, and therefore they could not satisfy the sizing requirement. Furthermore almost all commercially available high-temperature circuitry use non-cmos or non-standard CMOS processes which are more expensive than the standard bulk CMOS technologies. For instance, Silicon-On-Insulator (SOI) chips which are designed for up to 200 C usually require 5 V or more, need high power using around 20 ma per component and can cost in excess of $200 per component. Also The low power/voltage requirements of our SmartChip are due to its required autonomous battery platform to operate during the entire process of digester, for about 20 hours, in a harsh environment. We have considered the recent published work in bulk CMOS high temperature electronics [1]-[8] and try to improve the trade off between power and performance. We use switch capacitor differential circuit architectures with Correlated Double Sampling (CDS) as the basic circuit blocks due to their correction capability of leakage currents and voltage offsets. We first simulate the circuit at 125 C, since the available spice model is not valid above 125 C, and calculate the circuit parameters such as noise, power and voltage headroom which could be affected by the high temperature effects. Then we will fabricate a test chip leaving enough margins for 180 C operation to measure the Smart chip Chip results SOC at that Sensors temperature of interest and check our design. The SOC sensor is divided into MEMS sensors and electronic sensor interface parts as shown in Fig 2. The MEMS sensors are studied and designed with another college of mine in our group, we only look at electronic sensor interface on this paper. Power Management Oscillator Control Logic MEMS Sensors Bias Circuitry Amplifier ADC Memory Electronics Sensor Interface Figure 2: Smart Chip main system blocks. 1.2 State-of-the-Art Background Survey on High Temperature Circuit Design Recent research show that high temperature sensor interface components implemented in standard CMOS processes can operate at high temperature more than 200 C [1]-[8], which is well above for what our application aimed, but we still have more constraints on power consumption and supply 2

voltage of our Smart Chip. These addressed works used 0.5 um bulk CMOS technology with 5 V supply voltage source, our intention, however, is to design a chip using more recent CMOS technologies, 0.13 µm CMOS technology with 2.5 V as a voltage source. Also, as shown in Fig 2, our Smart Chip sensor interface besides an amplifier, an Analog-to- Digital Converter (ADC), an oscillator and a control logic blocks, which are addressed in almost all previous works [4]-[8], consists of a voltage reference as well as a non-volatile memory blocks, which have not been addressed in the bulk CMOS for high temperature environment up to 180 C. Therefore our Smart Chip can be considered as an independent self-functional data acquisition system at high temperature without using any external memory and supply voltage. As a quick over view of the system blocks shown in Fig 2, almost all analog blocks consist an amplifier including the integrator and comparator used in the ADC, the oscillator, and the voltage reference. Based on their design requirements for different purposes, different structures will be used. Since we want large dc gain and ability to drive capacitive loads at Pre-Amplifier stage, we chose the fully differential folded-cascode amplifier with switched-capacitor structure [10]. Although the authors of [4]-[8] used this type of amplifier, for the output stage, however, a tow-stage amplifier might perform better in terms of large output swing due to our low voltage limitation. After amplification we want to sample sensors data for data acquisition. Sigma-delta modulator, Σ ADC, has been reported as a robust analog-to-digital converter [18] by means of the noise shaping technique. Hence the feasibility of ADC in high temperature application has been addressed [4] and [8], and we also chose this type of ADC to mitigate analog device impairments at high temperature. The oscillator is generating the clock for using in ADC and micro controller unit. To build an entire SOC smart chip without using off-chip components, such as crystal and capacitors, also to prevent dealing with inductors quality in standard CMOS, we can possibly choose a differential ring oscillator [10] which has been shown functional at high temperature [4]. The micro controller is a simple control logic unit to control ADC clock for different sampling rates and to manage recording data on memory. In this proposal we study the design and implementation of the SmartChip building blocks that we have fabricated so far such as different structures of bias circuit, amplifier, voltage reference, and oscillator. The remaining building blocks will be focused as our future work plan. In the following section, before looking at our fabricated blocks, we first look at high temperature impact on CMOS electronics in general and the technique we can use to develop our SmartChip. 1.3 High Temperature Considerations At high temperature, these main blocks shown in Fig 2 implemented in standard CMOS present many impairments, including reduced electron/holes mobility, threshold voltages drop, and increased junction leakage currents [11]-[15], which introduce new design challenges. Among these impairments, excess leakage current at high temperature causes the most serious problem such as shifting the operating points in our analog circuits, lowering output resistance of high-impedance nodes, being a source of latch up triggering current, or greatly increasing offset among matching devices. It can bring the loss of charge stored at dynamic node or severely reduce circuit performance due to loss of bias current. So, the leakage is among the most serious challenges in silicon high temperature electronics [12]. Before we discuss the impact of high temperature on the mobility, threshold voltage and leakage current in the following sections, it is worthwhile to notice that in general the single-ended 3

circuitry is very sensitive to common mode errors including the ones caused by high temperature such as leakage current. The key is to choose a robust circuit architecture to mitigate the common mode errors, i.e. fully-differential. We use fully differential switch capacitor architectures due to their reduction capability of leakage currents at high temperature [8]. 1.3.1 Mobility Variation over Temperature In silicon material at high temperature the carrier (electron/holes) mobility is mainly affected by a basic scattering mechanism, called lattice scattering. This means by the vibration of the lattice a traveling carrier through the silicon crystal is scattered. The carrier mobility from the lattice scattering decreases as temperature increases. The temperature dependence of such a decrement is about T 1.5 [4]. Figure 3: NMOS channel electron mobility measurement vs. temperature ([4]). In Fig 3 an example of an NMOS channel electron mobility measurement versus temperature is depicted. In the temperature range of our interest here, from room temperature, 27 C (300 K) up to 180 C (453 K), we notice that the mobility linearly decreases over temperature. This measured results are fitted to the following simplified model provided by [12]. ( ) 1.5 T µ(t ) = µ(t 0 ) (1) T 0 4

1.3.2 Threshold Voltage Variation over Temperature The physical expression for the threshold voltage of a long channel MOS transistor without substrate biasing is given in Equation (2) according to [13]. V th = φ ms Q SS C OX ± 2φ F ± γ n,p 2φF (2) where + sign represents NMOS and - sign represents PMOS. Here C OX is the gate capacitance per unit area, γ n,p is the body-effect constant, Q SS is the surface-state charge density, φ F is the Fermi potential of the bulk, and φ ms is the contact potential difference between the gate and the substrate. The physical expressions for φ F and φ ms are given by: φ F = kt ( ) q ln NB (3) φ ms(nmos) = kt ( ) q ln NB N g n 2 i n i φ ms(p MOS) = kt q ln ( Ng N B where N B and N g are the doping levels for the bulk and the gate, respectively. The temperature dependency of threshold voltage can be derived by taking the derivative of these quantities with respect to temperature as follow: δ(2φ F ) = 1 ( 2φ F E g δt T q 3kT ) (5) q δφ ms δt = 1 T ( φ ms + E g q + 3kT q δφ ms ) (4) ), (NMOS) (6) δt = φ ms, (P MOS) (7) T By substituting Equations(5) and (6) into the temperature derivative of Equation (2), one can obtain the NMOS threshold voltage temperature dependency given by the following equation [4]. δv th δt = φ ms T + 2φ F T + γ n δφ F, (NMOS) (8) 2φF δt For a typical CMOS process this dependency at room temperature, i.e., 300 K, results in a value of -3.10 mv/ C for the first term, 2.70 mv/ C for the second term, and -0.4 mv/ C for the last term [4], which show that the threshold voltage of an NMOS transistor decreases when the temperature increases. On the other hand, the threshold voltage temperature dependency for a PMOS device becomes δv th δt = φ ms T 2φ F T γ p 2φF δφ F δt + 1 T ( Eg q + 3kT q ), (P MOS) (9) where comparing to Equation (8), for a typical CMOS process this dependency at room temperature, i.e., 300 K, results in the decreased magnitude of first term which is about -0.5 mv/ C, the negative sign of second and third terms and an extra added term with a value of about 4.3 mv/ C at 300 K [19]. As a result, by increasing the temperature the NMOS threshold voltage 5

turns to be more negative and PMOS threshold voltage urns to be more positive, in other words, for both NMOS and PMOS the absolute value of threshold voltage decreases as temperature increases. Also we notice that the change of PMOS threshold voltage is a bit faster than that of NMOS. Such trend is also confirmed by experimental results showing that for a typical CMOS process for both NMOS and PMOS a 0.5 V change of the threshold voltage happens while temperature changes from 25 C to 250 C [15]. Fig. 4 shows the measurement results of an NMOS transistor operating over a such wide range of temperature variation (up to 250 C). Figure 4: NMOS threshold voltage measurement vs. temperature ([15]). For the next section we focus on the leakage current variation over temperature. A rule of thumb to keep in mind in general to prevent relatively large channel leakage for high temperature operation is to use long channel devices, however, obtaining constant W, increasing the channel L length forces to increase the width as well which leads to extra junction leakage. Hence there is a trade of between these two different source of leakage currents that we have to take into our consideration as follows. The high temperature variation causes two sources of leakage currents, one is sub-threshold channel leakage current and the other is junction-to-substrate leakage current. The sub-threshold channel leakage current exponentially increased due to decreased Threshold Voltage (A half-volt V t decreases from 25 to 250 C) and decreased Carrier Mobility ( At 250 C is less than 1 the 2 mobility at 25 C), however all the building blocks of our SmartChip shown in Fig 2 operate in Strong Inversion, so we only consider the junction-to-substrate leakage current in our study here. This leakage current increased (About 5 orders of magnitude from 25 to 250 C) due to increased Intrinsic Carrier Concentration n i (T ) that we discuss in the following section [4]. 1.3.3 Junction (Reverse-Biased Diode) Leakage Current This section refers to the work presented in [4] about high temperature impacts on leakage current. At room temperature, the leakage current is very small, usually on the order of pa. As temperature 6

rises, two different effects cause the increase of the junction leakage current, drift current and diffusion current as follow: I Leak = I L.Diffusion + I L.Drift = qan i 2 (T ) N D DP τ qan i(t )W 2τ V A (10) where n i (T ) is the intrinsic carrier concentration, A is the area of the p n junction, V A is the reverse bias voltage, which is negative, N D is the n type doping density, W is the width of the junction depletion region at applied V A, D P is the minority carrier diffusion constant, and τ is the minority carrier lifetime. The first term is diffusion current and the second term is drift current. Drift (generation-recombination) current is due to the thermally generated electron-hole pairs in the depletion region. This current is proportional to n i (T ), and dominates to temperatures up to 100 150 C. It doubles the leakage current for every increase of 10 C based on the formula provided here. Diffusion current is due to the thermally generated minority carriers away from the junction area. This current is proportional to n i 2 (T ) and dominates at higher temperature 150 300 C. It, however, quadruples the leakage current for every increase of 10 C. Figure 5: Comparison of the Drain Junction Measured Leakage Currents for NMOS vs PMOS over the High Temperature Variation [5]. Measured drain junction leakage currents for both NMOS and PMOS devices are presented in Fig 5. The leakage current increases about 5 orders of magnitude from 25 to 250 C. NMOS and PMOS have different doping concentrations. For NMOS the p-type epitaxial layer doping concentration is N A = 10 15 cm 3, while for PMOS the n-well doping concentration is N D = 4 10 16 cm 3. More importantly, The concentration of minority carriers is a strong function of the temperature but is inversely proportional to the doping concentration. Therefore, PMOS transistors have much less leakage current than NMOS in an n-well process and as depicted in this 7

plot the PMOS leakage current is about 3 orders of magnitude less than NMOS [4]. Therefore for temperature robustness it is better to use more PMOS based structures in our building blocks rather than NMOS counterparts if possible. 1.4 High Temperature Compensation Techniques There are some improving techniques to decrease the impact of high temperature leakage currents, which in general depend on the specific requirements and the structure of the particular circuit, for instance zero temperature coefficient gate biasing, substrate biasing feedback, leakage current feedback cancellation, and constant-gm biasing are addressed in [4]. Among these techniques, the constant-g m biasing is a classic and popular technique that is commonly used in regular circuits [10] as well as high-temperature circuits [3, 4]. We will use this structure with a modification to improve its performance in the presence of temperature variations. The design will be discussed in more details in the next section. Also threshold voltage drop and leakage current might cause the voltage offset problem. It has been shown that auto-zeroing, chopper stabilization and correlated double sampling could reduce the voltage offset [16] and [17]. As explained earlier, in the SmartChip system, we would like to have a relatively low supply voltage (less or equal to 3 V which is available from a coin-type battery). Furthermore, to improve the battery longevity, power consumption must be minimized. However, low DC bias current means increased sensitivity to currents variations due to the increased leakage at high temperatures. Therefore, during the design, special care has to be given to this trade-off. Since the spice model available from foundry is not valid at temperature beyond 125 C, we simulate the circuit at 125 C and calculate the circuit parameters such as noise, power and voltage headroom which could be affected by the high temperature effects. Knowing these impacts, we could find and leave enough margin for 180 C operation as we need. Then we will fabricate a test chip and afterward measure the circuit results at the temperature of interest up to 180 C to check the functionality of the design. We are now looking at each component of our Smart Chip to explore its functionality at high temperature and its possible circuit topologies. Figure 6: Layout of our fabricated SmartChip building blocks as a high-temperature test chip. 8

2 Fabricated SmartChip Building Blocks using 0.13 µm Bulk CMOS Technology For our first fabrication run, we taped out some of the SmartChip building blocks using CMC CAD tool in 0.13 µm Bulk CMOS Technology IBM design kit. Our chip consists the following blocks: a bias circuit, an OpAmp, a voltage reference, and an oscillator as the main SmartChip building blocks as well as different size switches, different size inverters and different type of resistors for studying their temperature behavior. The lay out of our taped out test chip is presented in Fig 6 and we explain each fabricated block in the following separate sections. 2.1 Bias Circuit Implementation Considering the simple current mirror circuit shown in Fig 7, we notice that since the reference current created from a simple resistor, if we assume we have a variation in our supply, we can derive the output variations in current and voltage as follow: Figure 7: Supply-Dependent Biasing. So the output voltage is quite sensitive to the supply variation is this biasing, we now look at another biasing to solve this problem. 2.1.1 Supply-Independent Bootstrapped Design If we have a feedback from our output to sense our reference input like the bootstrapped circuit shown in Fig 8, by writing a KVL over M3 and M4 in top current mirror and assuming both current are equal due to using long channel devices to eliminate channel length modulation we notice that there is no dependency on supply voltage at the output as derived equation in this figure shows, however it is still highly dependent on temperature due to µ p, C ox and R s that we discuss in details later on. 9

Figure 8: Supply-Independent Bootstrapped Biasing. 2.1.2 Supply-Independent Start-Up for Bootstrap It is worthy to mention that for switching supply voltage (On/Off) scenario, if the initial value of our current reference in Fig 8 happens to be equal zero, it will remain zero for ever, so we need a start-up circuitry to ensure our previous assumption which is the reference current has the initial non-zero value. The start-up circuitry could be a diode-connected transistor which is added into circuit Fig 8 to provide a current path from VDD through M3 and M1 and forces M2 and M4 to start conducting current.... 2.1.3 Bias Circuit Design A generic constant-g m biasing circuit is shown in Fig. 9.(a). The transconductance (g m ) of devices is a critical parameter affecting gain, bandwidth, and stability of an amplifier. Therefore, it is important to minimize g m variations over the desired temperature range of operation. A classic bias circuit for having constant-g m biasing [10] is shown in Fig. 9.(a). It is well-known that the g m of a MOS transistor in saturation region, assuming long-channel devices and neglecting channel length modulation and the body effect, is given by [10] g m = 2µ n C ox ( W L ) I D. (11) Since g m is proportional to mobility, if one can generate a bias current that is inversely proportional to the mobility, then the g m of any transistor whose bias current is derived from such current is ideally independent of the mobility. This is the task of the classic constant-g m bias circuit of Fig. 9.(a), and it can be shown that I B in this circuit (again, assuming long-channel devices and neglecting channel length modulation and the body effect) is given by [10]: I B = ( ) 2 2 L1 L2 2. (12) µ n C ox R B W 1 W 2 10

Constant Gm Biasing V DD M 7 M 8 M 9 M 11 M 13 V Pbias Startup Circuit M 5 M 6 V Pcas V CM M 3 M 4 V Ncas V Nbias R B2 Positive TC R B R B1 Negative TC M 1 R B M 2 I B M 10 M 12 M 14 ( b) ( a) Figure 9: (a) Bias circuit using constant-g m biasing. (b) our modification; using two resistors in series with negative and positive TC. From Eqs. 12 and 11, the g m of M 2 is given by g m2 = 2 R B ( 1 1 ) K where K is the relative sizing factor of M 2 and M 1 ; W 2/L 2 W 1 /L 1. Thus g m2 to the first order of approximation is independent of the bias current, and is inversely proportional to R B. Hence, although the bias current would increase due to change in the temperature, g m would ideally be stable over temperature if the bias resistor, R B, has a zero temperature coefficient (TC). In [3], the main core of the circuit of Fig. 9 have been used and with acceptable performance has been reported when R B is implemented using a conventional poly resistor with TC of about 1000ppm/ C. In this work, we further improve the performance by using an alternative implementation for this resistor. First, in the 0.13µm CMOS technology that we are using, a resistor with TC on the order of 100ppm/ C is available. Using this resistor which is less sensitive to temperature further improves the temperature stability of the circuit. Second and the more important modification is the realization of R B using a series combination of two different type of resistors, one with a positive TC and another with a negative TC (the magnitude of their temperature coefficients differ by a factor of two ), thus using a proper ratio of resistors we minimize the effective TC of the series combination, as shown in Fig. 9.(b). Implementing these two modifications, the temperature stability of the circuit has been improved. We present our constant-g m performance over temperature in simulation results section. We can think of an alternative approach in which we still use constant-g m biasing circuit shown (13) 11

in Fig. 9, but we try to make the bias current constant rather than g m. The constant bias current ensure to obtain constant voltage bias points to compensate temperature variations. If we again consider Eq. 12, we notice that I B has two temperature dependent parameters; µ n and R B 2. We know that µ n linearly decreases over temperature as we discussed in previous section on Eq.??, hence to make I B constant we can use a biasing resistor, R B, which has a positive temperature coefficient. Using this alternative constant-i B, we can further improve the temperature performance of the biasing circuit. We implemented and fabricated the circuit of both constant-g m and constant-i B approaches as we discuss in more details in following section. 2.1.4 Bias Circuit Simulation Results Since the foundry models for the 0.13 µm CMOS technology used here are only validated up to 125 C, all simulation results presented in this work are for temperatures up to 125 C. The simulation results of the bias circuit here and the amplifier in the next section are compared with the corresponding simulation results presented in [4] as well as measured results reported in [3]. Ibias 13.5 DC Response: Constant gm Biasing 13 12.5 I (µa) 12 11.5 11 10.5 10 25 50 75 100 125 Temperature ( C ) Figure 10: I bias versus Temperature variations of series combination of two different type of resistors for Constant g m Biasing circuitry. First we look at our constant-g m approach using a series combination of two different type of resistors with positive and negative TC. We simulated the circuit shown in Fig. 9.(a) to obtain I B vs temperature. The bias current I B changes from 10.3 µa at room temperature (25 C) and almost linearly increases to 13.05 µa at 125 C as shown in Fig. 10. The reason for such linear increase in I B for constant-g m approach, while we almost keep R B value constant using a series combination 12

of positive and negative TC Resistors, is the µ n temperature behavior which is linearly decreasing based on Eq. 12. In comparison, the same bias current in [4] varies from 9 µa to 14µA for the same temperature range. Both results are based on simulations. In [3] the measured bias current varies from 15 µa to 20 µa for the same temperature variation. In the next simulation we compare the two constant-g m and constant-i B approaches. In this simulation we decrease the amount of bias current to achieve a lower power consumption. The straight line in Fig. 11 represents the constant-g m approach in which the bias current I B shows the same characteristic as previous simulation. I B changes from 6.4 µa at room temperature (25 C) and almost linearly increases to 8.2 µa at 125 C. The I B variation over this temperature range in the constant-g m approach is about 1.8 µa. The g m variation over this temperature range is about 5 µω 1 from 82.51 to 77.55 µω 1. The reason for this minor variation of g m is due to overall temperature coefficient of R 1 and R 2 in series which is not absolutely zero. In order to obtain a better constant-g m characteristic we can properly adjust the ratio of R 1 and R 2 regarding to their temperature coefficient value. The second plot in Fig. 11, however, illustrates the characteristic of the constant-i B approach. As we mentioned we use a positive temperature coefficient biasing resistor for R B to compensate the negative temperature coefficient behavior of µ n in Eq. 12. I B obtain its minimum value of 6.26 µa at room temperature (25 C) and its maximum value of 6.68 µa at around 85 90 C. I B behaves almost as a flat curve in this temperature range. This I B variation over the temperature range of 25 125 C in the constant-i B approach is about 0.42 µa which is less than 1/4 of that of constant-g m approach, 1.8 µa. Figure 11: Comparison of I bias versus Temperature Variations between constant-g m approach and constant- I B approach for Constant g m Biasing Circuitry. 13

Figure 12: I bias versus Temperature Variations of Different TC Resistors for Constant g m Biasing Circuitry. In Fig. 12 we simulate different type of resistors having different temperature coefficient available in IBM 0.13µ CMOS technology. As I B behavior moves from linear to almost flat curve, the TC of corresponding resistors changes from highest negative values to highest positive values as we expected to compensate the negative temperature behavior of µ in Eq. 12. Hence we choose one of the resistors with highest positive TC in this simulation for our constant-i B approach. The summarized comparison between our bias circuit designs and [4] at simulation level as well as [3] at implementation level is presented in Table 1. Our design used 0.13 um CMOS technology while the other two used older 1.5 um CMOS technology. Both of our constant-g m and constant-i B approaches show a lower power consumption as well as a lower temperature variation compared to [4] and [3]. Design Cons-g m Cons-I B [4] (Sim.) [3] (Mes.) Technology (µm) 0.13 0.13 1.5 1.5 V dd (V ) 2.5 2.5 5 5 I B (µa) from 25 to 125 C 6.4 to 8.2 6.26 to 6.68 9 to 14 15 to 20 Table 1: Bias Circuit Performance Comparison. 14

V DD V DD V DD Bias Circuitry V i+ V i + OpAmp V o+ V + o SC CMFB V bias 2.2 Amplifier Implementation 2.2.1 Folded Cascode Amplifier Design Figure 13: Open-Loop OpAmp Block Diagram. Our amplifier open-loop block diagram shown in Fig 13, consists of a core amplifier, a bias circuit and a switch-capacitor common-mode feedback. We used the constant g m bias topology which we presented above as the bias circuit here, now we explain the implementation of other two blocks in Folded Cascode OpAmp2 more details. V DD I REF 3 M 9 M10 V cmfbpbias I REF1 V Pcas M 3 M 4 V in+ M1 M 2 V Ncas V o V o+ V in VNbias M 5 M 6 I REF 2 VNbias M 11 M 7 M 8 Figure 14: Folded-cascode amplifier. Since a large-gain amplifier is desired (so that when the gain drops due to temperature increase [8, 9] it still has sufficient gain) and also it should be capable of driving capacitive loads 15

(e.g., input capacitance of the ADC), a fully differential folded-cascode topology [10], shown in Fig. 14, with a classic switched-capacitor common-mode feedback (CMFB) circuit is chosen since it has been proved operational at high temperatures [8]. It also provides good stability performance and has lower voltage headroom requirement as compare to the telescopic structure [10]. An amplifier with NMOS input pair is chosen to to achieve larger g m with reasonable device sizes. All amplifier bias voltages are generated using the bias circuit shown in Fig. 9.(a). The CMFB is to maintain the common-mode output voltage around V dd. Such a CMFB is shown in Fig. 15.(a) and its functionality at high temperature is confirmed in [8]. Here, V pbias, provided from the bias circuit is used in CMFB circuit to adjust V cmfbp bias for controlling the bias voltage of the M 9 10 of the amplifier. All the switches in this figure are CMOS transmission gates, shown in Fig. 15.(b). The constant g m biasing circuit is also used to generate V CM = V dd 2 = 1.25 V. As shown in the simulation section the output common-mode voltage will settle to the desired voltage of 1.25 V after about 8 clock cycles. 2 SC CMFB V cmfbpbias Clk 1 Clk 2 Clk 2 Clk 1 V Pbias V Pbias ( a) V CM C SW C CM C CM C SW V CM Clk 1 Clk 2 VO+ V O Clk 2 Clk 1 Clk 1 ( b) Clk 1 Transmission Gate PMOS NMOS Clk 1 Figure 15: Switched-capacitor CMFB. 2.2.2 Amplifier Simulation Results The amplifier is simulated over the temperature range from 25 C to 125 C. At 125 C the bias currents, I REF 1, I REF 2 and I REF 3, shown in Fig. 14 are 60, 64, and 124 µa, respectively. Note that the larger the bias currents, the less sensitive the performance of the circuit to the increase of leakage at high temperature. Hence, there is a trade off between power performance and temperature stability. The magnitude frequency response of the amplifier at 25 C (and 125 C) are shown in Fig. 16. The open-loop DC gain is 72 db (69 db) and the unity gain bandwidth of the amplifier is 4.25 MHz (4.13 MHz). The phase margin is relatively insensitive to temperature and is greater than 86 over the temperature range as shown in Fig. 17. In [4], I REF 1, I REF 2 and I REF 3 are chosen as 180, 270, and 450 µa at 125 C and the simulated open-loop gain of the amplifier is 57 db. 16

at 25 ºC at 125 ºC UGBW ~ 4.13-4.25 (MHz) Tem. from 125 to 25 ºC Phase Figure 16: Amplifier frequency response; open-loop gain over the temperature range from 25 C to 125 C. at 125 (deg C) at 25 (deg C) Phase Margin 88 (deg) UGBW 4 (MHz) Figure 17: Amplifier frequency response; phase over the temperature range from 25 C to 125 C. The amplifier transient response at 125 C is shown in Fig. 18. In this figure, 100 Hz input signal is used. The common-mode of the output voltage, at the beginning is close to the ground due to the higher leakage current of NMOS as compared to that of PMOS transistors at 125 C. However, the CMFB circuit gradually sets the common-mode of the output to the desired value of V dd = 1.25 V. Table 2 summarizes the performance of the presented amplifier and compares 2 it with that of [3] and [4]. Here, the variations of I B correspond to the temperature range from 25 C to 125 C, however, based on the measurement results presented in [3] this current contin- 17

V dd 2 Figure 18: Amplifier transient response at 125 C. The CMFB gradually sets the common-mode of the output to the desired value of V dd 2 = 1.25 V. ues to increase (approximately) linearly as temperature goes beyond 125 C (up to approximately 200 C). Given the similarity between the structure of the amplifier presented here and that of [3], it is expected that I B increases to 14.6 µa, DC gain remains above 67 db, and the amplifier remains functional as temperature increases to 180 C. 2.2.3 Amplifier Performance Comparison The summarized comparison between our design and [4] at simulation level as well as [3] at implementation level is presented in Table 2. Our design used 0.13 um CMOS technology while the other two used older 1.5 um CMOS technology. Design This Work [4] (Sim.) [3] (Mes.) Technology (µm) 0.13 1.5 1.5 V dd (V ) 2.5 5 5 I REF 3 (µa) at 125 C 124 450 N.A. Amp. Power (mw) at 125 C 0.62 4.5 N.A. I B (µa) from 25 to 125 C 10.3 to 13.05 9 to 14 15 to 20 DC gain (db) at 125 C 69 57 56 Table 2: Amplifier Performance Comparison. Our design outdo in both power performance and temperature stability in comparison of our design and [4] at simulation level. In the first part of Table 2 we look at power performance comparison. Our power supply is half of the other two design and give us a better power performance in general. More specifically the power improving factor can be seen as 18 5(V ) 450(uA) 2.5(V ) 124(uA), which is

more than 6 times. In the second part of the table we look at temperature stability comparison. We obtained about half a bias current variation over the temperature range of 25-125 C due to our design modification of constant g m biasing circuitry compared with [4] simulation result. Also the results from [3] shows the same bias current variation as [4] with shifted to the 15-20 ua for the same temperature variation, however, this results are at implementation level. In overall for the amplifier performance we achieved more than 10 db open loop DC gain at high temperature, 125 C. Since our SPIC simulations show a better performance compared with [4] up to 125 C, we can expect its performance improvement for the test chip when we test the fabricated chip up to our target temperature, 180 C. 2.3 Voltage Reference Implementation Fig 19 presents our voltage reference block diagram. It consists of a core voltage reference circuitry, a single-ended amplifier including its bias circuit. We get into the implementation details Voltage Reference Block Diagram of voltage reference core in this section. The single-ended amplifier has the same topology as our fully differential amplifier and the only difference is to change the biasing of one output to make it single-ended. For the amplifier bias circuit, we used the same constant g m bias topology as before. V DD V DD V DD Bias Circuitry V i V i+ + OpAmp + V o Voltage Reference V REF V bias Figure 19: Voltage Reference Block Diagram. The voltage reference is a dc voltage independent of three main parameters; temperature, supply voltage, and process variations. The temperature has the most impact and it has the most concern of our study here. The supply voltage has the moderate level of importance and we used a bootstrapped, supply-independent biasing, design as we discussed priorly to compensate supply variation of the voltage reference. The process variation has less effect since most process parameters vary with temperature, so if our design is temperature independent, then it is process independent as well [10]. Therefore we explain how to design a temperature-independent voltage reference and discuss more details of the design and simulation results. The solution to have almost constant voltage reference over the temperature is based on having two different electrical characteristics; negative temperature coefficient (N-TC) voltage and positive temperature coefficient (P-TC) voltage. Then by adding these two together with some proper scaling we can obtain the constant voltage reference. The bipolar transistors have well-defined quantities for N-TC and P-TC. The bandgap reference is a common circuit to obtain proper temperature compensation solution using BJT transistors with N-TC and P-TC. 19

2.3.1 Negative Temperature Coefficient Voltage The bipolar pn-junction temperature characteristic expresses as follows: V BE = V T ln(i C /I S ) (14) where I S µ k T n i 2. If we assume that the collector current is constant, we have the derivative of base-emitter voltage as follows [10]: δv BE δt = V BE (4 + m)v T E g /q (15) T where m is a constant about -1.5 and E g is bandgap energy of silicon which is about 1.12 ev and has temperature dependency. For typical base-emitter voltage (750 mv ) at room temperature (300 K) we get the value of -1.5 mv/ K for this derivative. Therefore the bipolar base-emitter voltage has negative TC characteristic. 2.3.2 Positive Temperature Coefficient Voltage Two bipolar transistors with unequal bias current have V BE proportional to absolute temperature (PTAT) characteristic. Considering Eq 14 for I s1 = I s2 and small base current assumption, so we derive the following equation: V BE = V T ln ni 0 I S 1 V T ln I 0 I S 2 = V T ln n (16) where n is the ratio of currents. If we take the derivative of the above equation we will find: δ V BE = k ln n (17) δt q which is a constant. Therefore the bipolar base-emitter voltage has positive TC characteristic. In the following section we explain how to create a constant voltage reference using N-TC and P-TC voltages. 2.3.3 Bandgap Reference The idea is to properly add N-TC and P-TC voltages to cancel out the impact of temperature on reference voltage. The circuit which does this for us called bandgap. One bandgap example is shown in Fig 20. The opamp ensures that the voltage at X is equal to the voltage at Y. So by applying the KVL over the loop of Q1, R1 and Q2 we can find that the voltage of R1 is equal to V BE, so in this branch we add a N-TC voltage, base-emitter voltage of Q2, with a P-TC voltage, R1 voltage. The example design values for R0, R1 and n in the Fig 20 is given as follow. For room temperature and V BE =750 mv we obtain δv BE /δt -1.5 mv/ K and δv T /δt +0.087 mv/ K [10], hence for nominally zero TC we set: ( ln n 1 + R ) 0 (0.087mV/ K) = 1.5mV/ K (18) R 1 we may choose n = 31 and R 0 R 1 = 4. 20

Figure 20: Bandgap Voltage Reference Example Circuit. 2.3.4 Bandgap Voltage Reference Design The bandgap topology shown in Fig 21 is based on PTAT current which flow through a resistor to create a Positive Temperature Coefficient (P-TC) voltage to add up with a Negative Temperature Coefficient (N-TC) voltage which is a base-emitter voltage of a BJT. In order to obtain a PTAT current we used our amplifier which has been designed and studied early on. therefore we can assume to have a high open-loop gain opamp based on our simulation results. Figure 21: Implemented Bandgap Voltage Reference. We use PMOS transistors for PTAT current mirror in our design to take advantage of obtaining about 3 orders of magnitude less leakage current in our wide range of temperature variation as studied early on. To minimize the effect of channel length modulation in our PMOS mirror devices we use about a two times the minimum length transistor sizes, which decreases the mismatch 21

characteristic of copying the PTAT current. The output voltage reference,similar to our previous discussion, could be derived as follows [10]: V REF = V BE6 + R 2 R 1 V T ln n (19) Although the output voltage reference is depend on the resistor components which are temperature dependent, they essentially do not change the temperature characteristic of our P-TC and N-TC topology since the ratio of these resistors shows up in this equation and this ratio will cancel out this dependency. Before discussing the simulation results, it is worthwhile to mention how we can physically implement PNP BJTs in standard CMOS technology. A PNP transistor interestingly has a nice compatibility in an n-well CMOS process. As presented in Fig 22, the emitter could be the p+ inside the n-well region, the n-well itself considered as the base and the p-substrate is the collector. One issue is that the collector is inevitably connected to ground, so we can not easily use the cascade topology. Figure 22: Implementation of PNP BJT in CMOS Technology. 2.3.5 Bandgap Voltage Reference Simulation Results Our bandgap reference voltage circuit shown in Fig 21 is simulated to obtain the following results. First we plot the negative TC voltage and PTAT current variations versus temperature shown in Fig 23. The Base-Emitter voltage of Q 6 shows a N TC characteristic and current flowing through R 2 has PTAT behavior as discussed above. Adding the NTC V BE and PTAT I R2 times R 2, R 2 =5.8 KΩ, almost compensates temperature variation and leads to a fairly stable voltage reference at the output. Fig 24 zoom into the out put reference voltage variation over temperature for more variation details. V ref changes from 1.2544 V at 0 C and linearly increases to 1.2620 V at 125 C which gives about 7.6 mv variation. It gives a voltage reference of 1.258.2 V with a variation of ±3.8 mv in the range of 0 125 C. This result turns out to obtain a temperature coefficient (TC) of 48.3 ppm/ C based on the following calculation. 22

Figure 23: Voltage Reference Output vs Temperature. NTC V BE added to PTAT Output Current times R 2 Leads to Almost a Constant V ref over Temperature. Figure 24: Voltage Reference Output vs Temperature. 23

V ref T C = 7.6 (mv ) 1.2582 (V ) 1 (125 0)( C) = 48.3 (ppm/ C) (20) It is worthwhile to notice that as shown in Fig 23 the NTC V BE changes from 832 mv at 0 C) and linearly decreases to 648 mv at 125 C which gives about 184 mv variation. The PTAT I R2 changes from 75 µa at 0 C) and linearly increases to 110 µa at 125 C which gives about 35 µa variation. The R 2 value used in this simulation is about 5.8 KΩ. Hence the PTAT voltage variation, I R2 R 2, turns to be 35 5.8 = 203 mv. Therefore we can further improve the temperature stability of the output voltage by tuning the R 2 values to achieve such a PTAT voltage variation less than 203 mv in order to compensate this 7.6 mv of the output reference voltage. This Work [20] Technology (µm) 0.13 0.6 V dd (V ) 2.5 4 V ref (V ) 1.2582 ±3.8 mv 1.1421 ±2.85 mv T-Range 0 125 C 0 100 C T-Coefficient 48.3 ppm/ C 50 ppm/ C Table 3: Voltage Reference Performance Comparison. We compare our voltage reference performance with one of the state-of-the art recent work presented in [20] in Table 3. Although we achieved less than ±1 mv extra variation for output voltage reference, our temperature range is 25% wider than that of [20] and therefore our temperature coefficient is less than the reported result in [20]. Our reference voltage gives a 1.25 V, however for our SmartChip we want a reference voltage of 2.5 V that we need to implement in the next fabrication. The idea is the same as what we explained and Oscillator presentedblock in Fig. Diagram 21. The modification to achieve double output voltage is to stack up two diode connected BJT to add their corresponding V B E as presented in [10]. 2.4 Oscillator Implementation V DD V DD Bias Circuitry Ring Oscillator V o+ V o V bias Figure 25: scillator Block Diagram. 24

Our oscillator design consists of a core oscillator circuitry, and a bias circuit as shown in Fig 25. The bias circuit is our constant g m bias topology the same as the one we used for voltage reference and amplifier before. In this section we discuss the implementation details of the oscillator core. The oscillator is another main building block of our SmartChip. Since off-chip components, such as crystal and capacitors used in oscillator are hard to obtain for high temperature environments, also we plan to design a system on chip for our high temperature application, we do not use any off-chip component for the oscillator. To implement an all-silicon oscillator we use a fullydifferential three-stage ring oscillator since high quality inductors are hard to obtain for traditional 3-Stage Differential Ring Oscillator LC oscillator topology in CMOS process. V DD V DD V DD V Pbias V Pbias V Pbias + + + V O+ + + + V O V Nbias V Nbias V Nbias Figure 26: Block Diagram of Three-Stage Fully-Differential Ring Oscillator. Fig 26 shows the block diagram of our three-stage differential ring oscillator which consists of three identical inverters as delay cells [10]. Using a 1st-order linear model, the transfer function of each delay cell can be approximated as follows: V o V i = A 0 1 + ω/ω 0 (21) where A 0 is the small-signal low frequency gain and ω 0 is the dominant pole, the 3-dB bandwidth. To satisfy the oscillation criterion, Av must be at least 2. It oscillates at a frequency of: 3ω0 f osc = (22) 2π which means the ring oscillator frequency is the frequency with 60 phase shift per delay cell stage [10]. 25

Oscillator Delay Cell; Inverter V DD M 3 M5 M 6 M 4 V Pbias V o V o + CL CL Vi+ M1 M 2 V i V Nbias M 7 Figure 27: 1-Stage Delay Cell of the Ring Oscillator. 2.4.1 Oscillator Delay Cell Design For our delay cell inverter, we used a typical fully-differential 1-stage OpAmp with additional diode-connected PMOS load at the output [21] as illustrated in Fig 27. This topology called symmetric load design which obtain better noise performance than with single PMOS load, and it is easier to achieve the necessary voltage gain presented in [22]. The oscillation frequency is proportional to 1, and the gain of each delay cell, inverter gain, is determined as follows: R oc o = g m3,4 C L /2 2.4.2 Oscillator Simulation Results A inv = g m1,2 R o = g m1,2 g m3,4 (23) In Fig 28 we demonstrate the output voltage of each delay cell in our three-stage ring oscillator. You can see that each delay cell introduces an extera phase shift to the signal which is related to the value of C L. With C L in order of 10 pf the transient simulation shows that the ring oscillator has an oscillation frequency about 500 KHz. Using our already introduced constant-g m -biasing circuitry shown in Fig. 9 to bias V N bias and V P bias of our oscillator delay cells shown in Fig 27, we got a frequency variation of about ±20% from room temperature up to 125 C. In this biasing circuitry, similar to what [4] did, we biased the NMOS tail current source, V N bias in Fig 27, using NMOS diode-connected biasing transistor M 1 in Fig. 9 and similarly we biased the PMOS loads, V P bias in Fig 27, using PMOS diodeconnected biasing transistor M 8 in Fig. 9. We noticed that, however, if we bias both NMOS tail current source and PMOS load of each delay cell with a same type of biasing transistor, let say M 6 and M 8 PMOS transistors for example, we get a better temperature stability over the temperature 26