TUTORIAL I ECE 555 CADENCE SCHEMATIC SIMULATION USING SPECTRE

TUTORIAL I ECE 555 CADENCE SCHEMATIC SIMULATION USING SPECTRE Cadence Virtus Schematic editing prvides a design envirnment cmprising tls t create schematics, symbls and run simulatins. This tutrial will take yu thrugh the varius steps invlved in the creatin f a schematic using Virtus schematic editr. The steps are explained in cntext f a simple inverter and then later with tw inverters t shw hierarchy. T have all yur cadence related wrk in a flder, create a new flder cadence using the cmmand mkdir. Change yur wrking directry t the flder created using the cd cmmand. T set-up the cadence wrking envirnment, run the cmmand fixcadence If yu already have a cadence envirnment set, skip this step. All yur cadence envirnment settings will have t be reactivated after executing this cmmand. Setting f cadence wrking envirnment includes adding additinal library paths. Yu dn t need t add any additinal library paths fr this curse. NCSU libraries are already set fr yu t use in this curse T invke a cadence, type icfb & at the cmmand prmpt. This pens a cmmand interface windw (CIW) as shwn in Fig. 1. Fig. I. Cmmand Interface Windw We will use the NCSU CDK which autmatically starts the library manager and yu shuld see the NCSU libraries as shwn in Fig. 2. Updated By : Vind Reddy fr 0.18u n 09/11/08

Fig 2. Library Manager. Creating a new library: Select File --> New --> Library in Library manager. Enter a library name in the new library creatin windw as shwn in Fig. 3. Press OK. Fig. 3. New Library Creatin Windw. Then a new windw pens t cnfigure the new library with a technlgy file. The windw is shwn in Fig. 4. Select Attach t an existing techfile and press OK.

Fig. 4. Windw fr cnfiguring the technlgy file. A new windw pens t attach the library file. Under Technlgy Library select NCSU_TechLib_tsmc02d and press OK. Creating a new schematic: Select File --> New --> Cell view in library manager and chse library under which yu wuld like t create the new cell view. Enter a cell view name and chse Cmpser-Schematic as the tl. View name shuld be schematic exactly accrding t Fig. 6. Fig. 6. Creating a new cell Updated By : Vind Reddy fr 0.18u n 09/11/08

Click OK. A blank cmpser-schematic windw shuld pen. Placing instances n schematic: T draw the inverter, yu have t add a PMOS transistr, a NMOS transistr, GND, pwer supply, pins fr input and utput, and wire them tgether. T add cmpnents t yur schematic: Frm Cmpser-Schematic menu, select Add --> Instance. This brings ut Add instance frm with Cmpnent brwser. Select library as NCSU Analg Parts. The cmpnent brwser is shwn in Fig. 7. Fig. 7. Cmpnent Brwser. Select P_Transistrs and then select pms4 t instantiate a pms transistr. After selecting pms4, place the pms transistr by using a single left muse click in the cmpser schematic windw. If yu need t get ut f add instance mde, just press the Esc key. Fllw similar steps as abve t place a nms transistr in the cmpser schematic windw. Yu need t select nms4 under N_Transistrs t instantiate a nms transistr. T add the VDD and GND t the schematic, select Supply Nets frm the NCSU Analg Parts in the cmpnent brwser. Select the cmpnent vdd fr supply vltage. Place it in the schematic. Select the cmpnent gnd fr grund vltage. Place it in the schematic. If yu make a mistake and need t get ut f add instance mde, just press the Esc key. S far, yu shuld have schematic as shwn in Fig. 8.

Fig. 8. Cmpser Schematic Windw after the cmpnents is placed. Defining the devices: After the instances are placed, we have t define the device widths and lengths. This can be dne by Selecting the device. A device can be selected by a single left muse click n the device that has t be defined. A slid white bx appears n the selected device. Press the letter Q in the keybard. An Edit Object Prperties windw pens up as shwn in Fig. 9.

Fig. 9. Edit bject prperties windw. Fr a PMOS, select mdel name as tsmc18dp and define its length and width. Press OK. Fr a NMOS, select mdel name as tsmc18dn and define its length and width. Press OK. The minimum length fr the devices in this technlgy is 18 0nm. The minimum width fr the devices in this technlgy is 27 0nm. After defining the devices, yu shuld have schematic as Fig. 10.

Fig 10. Cmpser Schematic Windw after the cmpnents are defined Cnnecting wires with pins: After the instances are defined and placed, yu can cnnect them by wires t frm the inverter. T add wires, Frm Cmpser-Schematic menu, select Add --> Wire (narrw). Click left muse buttn n the starting pint, and click left muse buttn n as many transitin pints as yu want. Then if yu want t end wire, just duble click. After wiring, yu need t create pins fr input and utput ndes. In rder t d this, Frm Cmpser-Schematic menu, select Add --> Pin. An Add Pin frm appears. The windw is shwn in Fig. 11. Fig. 11. Windw t add a pin. Updated By : Vind Reddy fr 0.18u n 09/11/08

Type in "IN as the pin name, and make sure the Directin is "input" as shwn Fig. 11. Mve cursr t schematic windw. Then, click left muse buttn t place pin. Mve cursr back t Add Pin frm, change "Directin" t "utput". Type in "OUT" as the pin name. Then, repeat abve step. The pins fr glbal signals are autmatically given. Final schematic view f inverter will be similar as Fig. 12. Dn't frget t save by selecting Design --> Check and Save in Cmpser-Schematic menu. Fig. 12. Cmpleted schematic. Creating a Symbl: Select Design --> Create Cellview --> Frm Cell view in the Virtus Schematic Editing Windw. A new symbl creatin windw will pen as shwn in Fig. 13. Press OK t create a symbl fr the schematic yu created. A new Virtus Symbl editing windw then appears as shwn in Fig. 14. If yu want t name the part, then select @partname with a single left muse click. A white bx appears ver the @partname indicating that it is selected. Press Q in the keybard. An Edit Object Prperties windw pens as shwn in Fig. 15. Change the partname t the name f yur interest. Dn't frget t save by selecting Design --> Check and Save in Symbl Editing menu. Updated By : Vind Reddy fr 0.18u n 09/11/08

Fig. 13. Creating a Symbl Fig. 14. Virtus Symbl Editing Windw. Fig. 15. Edit Object Prperties Windw

Creating a Schematic using an existing instance: Select File --> New --> Cell view in library manager and chse library under which yu wuld like t create the new cell view. Enter a cell view name and chse Cmpser-Schematic as the tl. View name shuld be schematic exactly accrding t Fig. 16. Fig. 16. Creating a new cell T instantiate an already existing symbl, Frm Cmpser-Schematic menu, select Add --> Instance. This brings ut Add instance frm with Cmpnent brwser. Select library as ece555. The cmpnent brwser is shwn in Fig. 17. Fig. 17. Cmpnent Brwser Place tw instances f the inverter in parallel. Draw wires and cnnect them as shwn in Fig. 18. A thick blue line indicates a wide wire (used fr multiple bits). A thin blue line indicates a narrw wire.

Fig. 18. Schematic with existing instances T add wire labels n the bus. Frm Cmpser-Schematic menu, select Add --> Wire Name. The wire name windw in shwn in Fig. 19. Type a name as shwn in the figure and select Bus Expansin ON. Place labels n each wire in the input side. D a similar naming fr the utput wires. The named wires are shwn in Fig. 20. Fig. 19. Wire Name Windw

Fig. 20. Schematic after named wires. After wiring, yu need t create pins fr input and utput ndes. In rder t d this, Frm Cmpser-Schematic menu, select Add --> Pin. An Add Pin frm appears. Type in "A<1:0> as the pin name, and make sure the Directin is "input". Mve cursr t schematic windw. Then, click left muse buttn t place pin. Mve cursr back t Add Pin frm, change "Directin" t "utput". Type in "B<1:0> as the pin name. Then, repeat abve step. Final schematic view f inverter will be similar as Fig. 21. Since the glbal surces namely, V DD and GND are nt in the schematic, we can add them t the schematic. The initializatin f the glbal surces in the schematic wuld enable us t cntrl the vltage surces when simulating the circuit. The new schematic is shwn in Fig. 22. Dn't frget t save by selecting Design --> Check and Save in Cmpser- Schematic menu.

Fig. 21. Cmplete Schematic fr tw inverters. Fig. 22. Cmplete Schematic fr tw inverters with glbal surces.

CIRCUIT SIMULATION We will be using SPECTRE circuit simulatr t simulate the designed circuit. This part f the tutrial will illustrate the steps t be fllwed befre simulating a single inverter. Simulating a bigger circuit with mre devices is similar t the prcess described belw. Clse all the windws and pen the schematic f a single inverter. Frm Cmpser-Schematic menu, select Tls --> Analg Envirnment. This brings ut Virtus Envirnment windw as Fig. 23. Fig. 23. Virtus Analg Envirnment. Select Setup --> Simulatr/Directry/Hst. A Chsing Simulatr/Directry/Hst windw appears like Fig. 24. Make sure the simulatr is set t spectre. If yu need t change yur simulatin directry (place where all the simulatin files are created and stred), yu can change the prject directry. Click n OK when yu are dne. Fig. 24. Setting up the simulatr.

Select Setup --> Mdel Path. A Setting Mdel Path windw appears like in Fig. 25. Brwse t the path where the mdel card is present and Click ADD and yu will have a windw similar t the ne shwn in Fig. 25. A cpy f the mdel card fr TSMC 0.18um CMOS Technlgy is available at /png/usr2/v/vindren/mdels /spectre/mdelfile18 Fig. 25. Setting up the mdel path. Then, in Virtus Envirnment windw, select Analyses --> Chse and fill it as shwn in Fig. 26. This is the setting t run a transient analysis fr 20ns. Fig. 26. Setting up transient analysis

In Virtus Envirnment windw, select Outputs --> T Be Pltted --> Select On Schematic. Then, g back t schematic and click n the wires attached input and utput f inverter. The wires shuld change clrs. Press Esc key t exit f selectin mde. The signals shuld be added in the utputs windw, as shwn in Fig. 27. Fig. 27. Setting up the utput plts. Select Setup --> Stimuli. A Setting Analg Stimuli windw appears like in Fig. 28. T set-up a input pulse at the pin IN Select Stimulus Type Inputs Check Enable Set functin t pulse Set Vltage 1 t 0.0 Set Vltage 2 t 1.8 Set Delay time t 0 Set Rise Time t 0.05n Set Fall Time t 0.05n Set Pulse Width t 2n Set Perid t 4n Press Change T set-up a glbal inputs Select Stimulus Type Glbal Surces Check Enable Set functin t dc Set DC Vltage t 1.8V Press Change Press OK In Virtus Envirnment windw, select Simulatin --> Run. The plt f the simulatin shuld appear in the Wavefrm Windw, similar t Fig. 28.

Fig. 28. Final Output Plts. T calculate the prpagatin delay using the calculatr tl prvided in Cadence In the wavefrm windw, select Tls -> Calculatr. Duble-click n delay t find the prpagatin delay between tw signals. The calculatr windw lks as shwn in Fig. 29. Fig. 29. Calculatr Tls set t calculate the prpagatin delay between tw signals Select wave in Selectin Chices. Place the cursr in Signal 1 and select the IN signal in the plt. Place the cursr in Signal 2 and select the OUT signal in the plt.

Set Threshld Value 1 t 0.9 [ V DD/2 (i.e.) 1.8/2] Set Edge Number 1 t 2 Set Edge Type 1 t rising Press >>> t setup the calculatr with mre ptins Set Peridicity 1 t 1 Set Threshld Value 2 t 0.9 [ V DD/2 (i.e.) 1.8/2] Set Edge Number 2 t 2 Set Edge Type 2 t falling Set Peridicity 2 t 1 Press OK Press Eval The prpagatin delay between the tw signals will be displayed as shwn in Fig. 30. The abve set-up calculates the High-t-Lw prpagatin delay between the signals. A similar set-up with a change in the Edge Types can be used t calculate the Lw-t- High prpagatin delay. Fig. 30. Indicating the High-t-Lw Prpagatin delay f the designed inverter The circuit simulatin set-up illustrates a step-by step prcedure fr ding a transient analysis. A similar prcedure with a change in the analysis type can be used t perfrm a dc analysis. Updated By : Vind Reddy fr 0.18u n 09/11/08

SIMULATION OF LARGE CIRCUITS We can fllw the abve prcedure t simulating large circuits. Hwever, as the number f stimuli increases, the time t set the stimuli values als increases. In this sectin f the tutrial, yu will be intrduced t sme techniques t save time while simulating large circuits with many stimuli values. Technique I: The easiest ptin is t save the stimuli values that were entered nce and reuse the state values when needed cnsequently. After all the stimuli values are entered fr the first time in the Virtus Envirnment windw, select Sessin -> Save State. A save state windw appears as shwn in Fig. 31. Fig. 31. Save State Windw The stimuli values alng with the analysis type, wavefrms t plt, technlgy file path and ther settings gets saved under the specified name. When needed later, the state can be retrieved by selecting Sessin -> Lad State in the Virtus Envirnment windw after selecting the crrespnding simulatr.

Technique II: The ther ptin is t write the stimuli in a file and add it t the simulatin whenever needed. A sample stimulus file fr the abve inverter is given belw A cpy f the stimulus file is available at /png/usr2/v/vindren/ece555/sample_stimuli V1 vdd! 0 DC 1.8 V2 gnd! 0 0 VIN in 0 pulse (0 1.8 0 0.05n 0.05n 2n 4n) The abve cmmands can be stred in a file and can be added used during simulatin. In the Virtus Envirnment windw, select Setup -> Simulatin Files. A simulatin file setup windw appears as shwn in Fig. 32. Fig. 32. Simulatin File set-up. In the Stimulus File enter the exact lcatin f the file with all the stimulus values and press OK. Run the simulatin as befre. Nte: Yu still have t setup the analysis, technlgy file selectin, and the utput waves t be pltted.

Syntax f sme imprtant statements Pulse Signal: The definitin f a pulse is as fllws: pulse ( vltage_1 vltage_2 ffset_time rise_time fall_time duty_cycle perid) Ex: pulse( 0 1.8 0 0.05n 0.05n 2n 4n) Prduces a pulse frm 0V t 1.8V with 0 ffset and 0.05n rise and fall time with a duty cycle f 2n and a perid f 4n Piece-Wise Linear: The definitin is as fllws pwl ( time1 vltage1 time2 vltage2 time3 vltage3 time4 vltage4..) Ex: pwl ( 0 0 2n 0 2.1n 1.8 4n 1.8 4.1n 0) Prduces a signal that stays at 0v frm time 0s t 2ns and then rises t 1.8vlts in the time interval 2ns t 2.1ns and stays at 1.8v frm 2.1n t 4ns and ges frm 1.8v t 0v in the time interval 4ns t 4.1ns and remains statinary afterwards. Updated By : Vind Reddy fr 0.18u n 09/11/08