Track Triggers for ATLAS

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Track Triggers for ATLAS André Schöning University Heidelberg 10. Terascale Detector Workshop DESY 10.-13. April 2017 from https://www.enterprisedb.com/blog/3-ways-reduce-it-complexitydigital-transformation 1

ATLAS Detector and HW-Triggers Calorimeter triggers: Muon triggers: No track triggers: energy distribution and rough particle ID muon identification and momentum no momentum, origin and separation of charged particles 2

Motivation for Track Triggers @ Hadron Colliders (with high pileup) event pileup: z 3

Motivation for Track Triggers @ Hadron Colliders (with high pileup) Isolated high-momentum track trigger: highest momentum track z 4

Motivation for Track Triggers @ Hadron Colliders (with high pileup) Isolated high-momentum track trigger: highest momentum track z typical signature for e, μ, τ 5

Motivation for Track Triggers @ Hadron Colliders (with high pileup) track triggers can provide useful information about: particle momentum particle direction origin (primary vertex, secondary vertex) particle counting particle isolation ( lepton identification) particle identification (in combination with other triggers) complementary to calo / muon triggers improve selectivity of trigger in general 6

Overview ATLAS Track Triggers Phase I upgrade (2018) Fast TracKer Processor (FTK) 100kHz (being installed) Phase II upgrade (2025): Regional track trigger (baseline) 1 MHz (not decided) Triplet Track Trigger (option) 40 MHz (idea) 7

FTK FTK Project Track Processor Inner Detector Level 1 ~100kHz ~100kHz FTK <100 µs Higher Level Trigger (HLT) & Event Filter Aim & Concept full track reconstruction p >1 GeV using 8 silicon layers (pixel+strips) T fast pattern lookup using associative memory linearised track fit for precise track parameters 8

Associative Memory fast matches (100 MHz) highly parallel AM Board AMchip06: 100k patterns ~10000 AMchips (pattern banks) in FTK tricks like Don t Care bits for variable resolution 9

FTK Expected Performance track reconstruction efficiency b-tagging (FTK technical design report) track finding efficiency depends on size of pattern bank pattern generation algorithm 10

FTK Limitations I number of (pre-calculated) patterns is limited ( AMchip06: ~100k) patterns covering small phase space are neglected inefficiency superstrips (-pixels) needed in order to reduce number of patterns backdraws of superpixels: loss of resolution ambiguities (e.g. A B) cannot be resolved with coarse patterns coarse patterns need to be validated! 11

FTK Limitations II to regain precision: refine hit positions and fit track candidates (DSPs) resolve ambiguities ( hit warrior ) time consuming data flow limitations needs to be upgrade for HL-LHC upgrade 12

HL-LHC Phase II Upgrade all silicon current silicon detector 13

HL-LHC Phase II Upgrade current silicon detector 14

Pileup at HL-LHC 5 times more luminosity significantly higher data rate up to 200 pileup events tracking becomes even more important HL-LHC: extremely challenging environment for track trigger! 15

Track Trigger Challenges for Phase II 14-19 tracking layers pattern lookup? Hit uncertainty region (pt > 10 GeV/c): Multiple Scattering region (pt < 10 GeV/c): N patterns N 2layer N patterns X 2 N layer use reduced number of layers 16

ATLAS Baseline Phase-II Readout + Trigger Architecture TRACKS not final! 17

ATLAS Baseline Phase-II Readout + Trigger Architecture not final! Upgrade: Level 1 (100 khz) Level 0 (1 MHz) 18

ATLAS Baseline Phase-II Readout + Trigger Architecture not final! No Track-Trigger @ Level 0 Upgrade: Level 1 (100 khz) Level 0 (1 MHz) 19

ATLAS Baseline Phase-II Readout + Trigger Architecture not final! No Track-Trigger @ Level 0 Upgrade: Level 1 (100 khz) Level 0 (1 MHz) Track-Trigger @ Event Filter 20

Common Track Trigger HW based on FTK Concept with AMs? being investigated by ATLAS: Two systems but same HW: FTK++: Full tracking at 100 khz EFTrack: Tracking with 1 MHz in Regions of Interest (10% of ITK) (L1Track): Tracking with 4 MHz in Regions of Interest (10% of ITK) Remark: L1Track requires dedicated L0/L1 readout architecture very preliminary! FTK++ EFTrack (L1Track) Input Rate 100 khz 1 MHz (ROI) 4 MHz (ROI) ptmin (GeV/c) >1.0 >2.0 >4.0 #patterns (billion) 5 2.5 2.5 2nd fitting stage yes no no development of improved AMchip2020 ~ 400k patterns per chip (250 MHz) 21

ATLAS Track Trigger Emulation 22

Simulation Results of AM-based Track Trigger Muon (MIP) track finding and fitting efficiency ~99% Rejection and Efficiency of Muons and Electrons triggered by Level 0: Muons Electrons numbers refer to pt threshold numbers refer to pt threshold factor 5-10 rejection of minimum bias background 23

Why not reconstruct all tracks at 40 MHz? 24

The Bandwidth Problem ATLAS detector for HL-LHC Readout of all hits for every bunch crossing only feasible for large radii ~R-2 100 Mbit/s 25

Minimum Number of Tracking Layers? transverse view: longitudinal view: pt with beamline constraint y beamline pt(triplet) z0 r dca beamline x z with beamline constraint 2 layers w/o beamline constraint 3 layers (some redundancy included!) 26

Optimal Distance Between Tracking Layers? Large gap between layers: reduction of extrapolation uncertainties increase of ambiguities (fake tracks) Small gap between tracking layers increase of extrapolation uncertainties reduction of ambiguities (fake tracks) no ambiguities ambiguities optimal tracking layer distance ~2-4 cm hits line up on almost straight lines easy reco 27

WARNING THE FOLLOWING SLIDES CONTAIN CONTENT THAT SOME MAY FIND DISTURBING AND THAT ARE NOT SUITABLE FOR SOME AUDIENCE ACCORDINGLY, VIEWER DISCRETION IS ADVISED 28

Alternative 40 MHz Track Trigger (L0TT) Strips D-MAPS Hybrid Pixel D-MAPS = Depleted Monolithic Active Pixel Sensors 29

Hybrid Pixel versus Monolithic Pixel Chip 50 µm MCC sensor FE-Chip FE-Chip 30

High Voltage Monolithic Pixel Chips Ivan Perić, NIMA 582 (2007) 876 50 µm no composite - no interconnects simplified design (ASIC) sparsified readout (zero suppressed) fast signals low noise thin sensor! fast serial output continuous readout trigger radiation hard! 31 Mupix7 (AMS 180 HV-CMOS) neutron irradiated

Possible Design of HV-MAPS stave distribution of optical links over stave optical links optical fiber Double Group lpgbtx link 2x power groups 2x 15 reticles 2x data concentrator data rate: 6Gbps (cluster) 1x optical link (1 spare?) cooling pipes data concentrator (15 inputs) 1400mm 100mm 32

Alternative 40 MHz Track Trigger (L0TT) y triplet trigger x pixel size: 50 x 50 µm2 gap 20mm Strips D-MAPS Hybrid Pixel D-MAPS = Depleted Monolithic Active Pixel Sensors 33

Track Finding Efficiency Single track efficiency for mips different pt thresholds >2 >5 >10 >15 migration losses >20 pt(gen) (GeV/c) Track reconstruction efficiency ~ 100% * Track purity is close to 100% (not shown) 34 * assuming 100% single hit efficiency

Simulated Z0 Resolution event vertex can be reconstruction with a resolution of a few mm in z-direction (depends on tracker material) σ(z0) ~ 2.5 mm z endcap endcap barrel good separation of pileup events possible! relevant for multi-jet triggers 35 coverage up to eta =2.2

Example: Simple Two Track Trigger 36

Summary FTK Phase I upgrade full track reconstruction at 100 khz being installed and fully operational in 2018 ATLAS Phase II: discussed track trigger upgrades FTK++: continuation of FTK concept with associative memories (baseline) EFTrack: similar to FTK but reconstruction at higher rate (1 MHz) in regions of interest (ROI) only ATLAS Phase II: L0TT triplet track trigger not so crazy idea of instrumenting large areas with monolithic active pixel sensors for track trigger can reconstruct ALL tracks (pt>1 GeV) at 40 MHz 37

Backup 38

Track Parameters from Space Points basic assumption: solenoidal magnetic field z s 3D tracking: simple robust from three planes 9 parameters helix and crossings described by 8 parameters over-constrained fit 39

Variable Pattern Matches with Don t Care 40