A new Vertical JFET Technology for Harsh Radiation Applications

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 1 A new Vertical JFET Technology for Harsh Radiation Applications A Rad-Hard switch for the ATLAS Inner Tracker P. Fernández-Martínez, D. Flores, S. Hidalgo, D. Quirion, M. Ullán IMB-CNM (CSIC), Spain

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 2 Outline 1. Introduction: V-JFET 2. Motivation and basic Structure 3. Device Layout and Process Technology 4. Electrical Performance 5. First Radiation Hardness Results 6. Conclusions

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 3 Motivation: Powering Scheme in the ITk ATLAS experiment @ CERN Upgrade for High Luminosity Higher performance, Higher compactness, Higher radiation hardness Switch Goal: To switch-off a malfunctioning sensor when it demands too much current to the power supply Powering scheme for the strips detectors of the Inner Tracker (the HV-MUX system) requires radiation-hard switches. 500 700 V detector bias Forward current: > 5 ma Reverse current: < 1 ma (after irradiation) Maximum radiation levels: Fluence: 2 10 15 1-MeV equivalent neutrons/cm 2 Total Ionizing Dose: 50 Mrad(Si) Targeted production of 20k devices Gate Large Current Increase Switchoff Source Drain

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 4 Controlled Switch Candidates Silicon Insulated Gate Transistors (MOSFET, IGBT): Gate oxide degradation by ionization damage prevents their use. Thyristors: Difficult turn-off and complex control circuitry. Not feasible for the application. JFET: Optimal candidate, but: N-type substrates too sensitive to radiation displacement damage (undergo type inversion under high fluences). P-type JFET: lack of commercially available devices. SiC Commercial JFETs have been tested: Most of them fail. The only surviving device is no longer sold. GaN Commercial HEMTs have been tested: Good performance of one candidate, but: Normally-Off device: need for continuous control voltage. Technology not mature; long term radiation damage in GaN still to be fully understood.

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 5 Silicon Custom V-JFET Main Features Bulk device: Very hard against radiation ionizing damage Reduced power density (long-term reliability) High resistivity p-type substrate: Hard against radiation displacement damage (p-type) High blocking voltage; low switch-off voltage (High resistivity) Poor on-state conduction (p-type and High resistivity) To reach the target current: parallel cell design Deep Trench technology: Deep trench (80 µm range) needed to achieve the target V OFF (1-3 V) Increased current density Final device area meet the reserved space in the HV-MUX board Layout made with independent cylindrical cells: Deep trench filling prevents the use of honeycomb designs Guard ring edge termination

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 6 V-JFET: Features Custom Silicon Vertical JFET based on the 3D-trench technology set-up at CNM- Barcelona for 3D detectors. Cellular design Each cell includes a conduction channel, surrounded by a deep trench (circular layout), which constitutes de gate electrode. The channel current is modulated by the depletion region extended from the gate-substrate reversebiased junction Features: - Depletion mode device (Normally-On) - 3D Device with Vertical Conduction High voltage capabilities Rad-hard against ionization Low switching-off voltage - P-type Rad-hard against displacement (at least, damage mechanisms are known) - Cellular design Adaptable Current capability - Custom made Optimization for the requirements Figures of merit in terms of several geometric parameters evaluated for an optimum design (2D TCAD simulation)

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 7 V-JFET cell: How it works? Source Oxide ON-State (V GS = 0) OFF-State (V GS > V OFF ) 80 µm Polysilicon Gate Channel Region (Inside) Output Transfer Drift Region Drain

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 8 First V-JFET Prototypes Optimization: substrate doping? Trench depth = 80 µm Substrate Thickness = 300 µm 2r=35 µm Substrate Resistivity: 150 500 Ω cm (Boron doping: 3e13 8e13 cm -3 ) Values on Target 2r=23 µm Nominal substrate doping spans in a wide range!

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 9 Cell Core Inter-level Oxide (TEOS) Device Structure Metal Electrode (Source) _ Non-doped polysilicon P+ Electrode (Source) N-Type Diff. Doped polysilicon (N-type) Diffusion (N-type) from the Doped polysilicon Cell Core Region 2r S/2 Inter-cell Region

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 10 Device Layout 7 photolithographic levels Gate Electrode Guard Rings Ch. Stopper Source Electrodes Gate Runners

Technology Design A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 11 Design of Experiments Device Design (parameter values) 7 Designs with different 2r and/or S (6x6 mm 2 ) (green) S\2r 23 29 35 10 X X XX 7 X X 2 Additional designs with 8.9x6 mm 2 (blue) P-Spray Strategy Dose [cm -2 ] w/o P-Spray - S With P-Spray With P-Pray 1e12 5e12 2r Substrate Doping High-Resistivity (500-1000 Ω cm) Lower V OFF Low-Resistivity (150-500 Ω cm) Lower V Drop

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 12 Process Technology D = 80 µm 2r = 35 µm S = 10 µm

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 13 Process Technology Trenches are sealed Inter-level Oxide P-type Diffusion (Source) N-type diffusion from Poly 1 Poly 1 Poly 2

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 14 Process Technology Inter-level Oxide N-type Diff. Doped (N + ) Polysilicon Non-Doped Polysilicon P-type Source 80 µm 300 µm

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 15 Electrical Performance Output Characteristic 2r = 23 µm; S = 10 µm Transfer Characteristic Narrow channel devices: High enough current Low enough V OFF Close to target device Good agreement with simulations Confirms simulation results Good starting point for fine optimization I DSS (I DS @V DS =-50V) V drop (V DS @I DS =5mA) V OFF (V GS @ I DS =10 µa) I OFF (I DS @V GS =10V) Measured 12 18 ma 0.46 0.64 V 1.90 2.55 V 0.4 1.7 µa Sim (6e13) 11 ma 0.68 V 1.85 V 0.5 µa Sim (7e13) 17 ma 0.50 V 2.25 V 0.5 µa

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 16 Electrical Performance Gate current Voltage capability Most devices show Gate current < 1 µa Some devices show high Gate current Other devices show I G increase when biased in the off-state Interlevel oxide pin-holes may totally or partially short Source and Gate Metals Breakdown voltage < 300 V Edge termination (4 floating guard rings) is not optimized for the used substrate doping Edge termination is tricky: Gate voltage at the device periphery and maximum electric field 80 µm deep into the substrate

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 17 Performance at low Temperature Output Transfer Operating temperature (External cooling): -30 ºC Blocking

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 18 Radiation Hardness Ionizing damage has been tested Gamma irradiations up to 50 Mrad(Si) I ON is reduced as a consequence of Ionizing damage (Dependence with Dose) Devices are still fully operative (meeting the specifications) under 50 Mrad(Si)

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 19 Conclusions ATLAS upgrade ITk requires rad-hard switches for the new powering scheme CNM proposes a custom silicon Vertical JFET Based on the 3D-trenched technology First V-JFET devices already fabricated Technology developed in one year! First measurements are already within specs (pre-irradiation) Results in very good agreement with simulations Blocking performance is an issue Full characterization program started Full on-wafer characterization Additional measurements (IR Thermography, etc ) Present and Future work Technological characterization (test structures) Radiation hardness study (Neutron irradiations, etc.) Fine optimization (new batches, design revisiting ) Other CERN experiments have shown interest on the V-JFET switch

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 20 Thank you!

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 21 Back up To be used just in case of tenacious questioners

9.0mm A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 22 ABC130 Power Board with HV Switch Provides low voltage for both hybrids and optional HV for sensor Designed to locate on sensor surface within a tightly constrained geometry Geometry set by available real-estate between hybrids and tooling requirements for stave module mounting Device packaging is biggest driver of board size (plus maintaining 500V clearances...) Board made up of two blocks, controlled by addressable 1-wire dual switch DCDC power board, based on CERN radiation tolerant Buck regulator FEAST2 HV switch, designed around two stacked EPC2025 GaN FETs (rated to 300V V DS ) 600V total Board separation provides independent development paths of circuits before their integration into a single unit HV Switch FEAST2 5x5mm EPC2025 FET 2x2mm HV Switch locates here DCDC V out adjust for TM Hybrids 68.0m m 2

9.0mm A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 23 ABC130 Power Board Integration on electrical module Single integrated board shown below with circuit function blocks highlighted Sensor Filter HV Switch 1-wire Control DCDC Power Block 13.5m m 20.0m m 6.5mm 28.0m m ABC130 Module with Power Board 3

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 24

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 25

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 26 HV Si, SiC and GaN based devices are being investigated FAILED FAILED FAILED FAILED FAILED PASS N.A. FAILED FAILED FAILED FAILED FAILED T.B.T. PASS need conf. 6

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 27 Requirements 2D Section for JFET (without P-column) Shallower trenches V BR > 500 V (target ~1000 V) I ON ~ 5-10 ma R ON << 1-10 kω (target ~ 100 Ω) I leak < 200 µa (target ~ 10 µa) R OFF ~ 100 MΩ V P ~ 5 V (target) V drop ~ few Volts (target ~ 3V) Area ~ 25 mm 2 (target) Rad-hard (Φ ~ 1-2 10 15 n eq /cm 2 ; Dose ~ 50 Mrad) Temp. Oper. = -30 ºC Possible self-heating Oper. In Magnetic Fields

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 28 Figures of Merit and Variables Figures of Merit: - Pinch-off voltage, V p The lowest possible - On-Resistance, R ON The lowest possible - Active area, A (dep. with R ON ) The lowest possible - Breakdown voltage, V BR (G-D) The highest possible - Gate-Source Breakdown Voltage is not a limiting figure of merit in normal operation, provided it is always higher than the Gate voltage (The highest possible) Design Optimization Variables: 3 basic variables: - Inter-trench Distance: 2r - Trench Depth: D - Substrate Doping Concentration: N A Trench Width (W) is not considered a basic parameter for the simulations, since it has a secondary influence on the electric performance (Though, it is an important technological parameter) Wafer thickness (t) is initially fixed (300 µm), although it can be modulated for the final device. N + P - P + P +

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 29 Technological Process 1. Starting material: 300 µm-thick wafer of high resistivity p-type silicon. Silicon dioxide is thermally grown to passivate the silicon surface. 2. Oxide is patterned, implanted with N- type dopants and then annealed to form the device termination (N-diff). A protective silicon dioxide layer is grown on top of the doped regions. 3. Trenches are etched by deep reactive ion etching (DRIE), down to the optimal depth for device operation (i.e. 80 µm) Typical width of the trenches is 5 µm.

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 30 Technological Process 4. Polysilicon is deposited and doped with phosphorous to form the gate. N-type dopants result diffused into the silicon, to form an n-type layer around the gate. 5. Non-doped polysilicon is deposited to seal the trenches. The non-doped polysilicon layer on the surface is then removed 6. Doped polysilicon is patterned and removed from the center of the channel region.

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 31 Technological Process 7. Cylindrical window is opened on the oxide at the channel center. Boron is then implanted on both sides of the wafer to form the source and drain 8. Inter-level dielectric is deposited on the surface. Vias to both p+ source and n+ gate are then opened. 9. Aluminum is deposited, patterned and etched to from connection lines and bonding pads. Similar Aluminum layer is deposited on the back side of the wafer (drain)

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 32 Technological Process 10. Passivation layer (Silicon oxide + Silicon nitride bilayer) is deposited, patterned and etched to open metal pads for bonding. Substrate (P-type) N-type Diffusion (Gate) Thermal Oxide N-type Polysilicon (Gate) Inter-level Oxide P-type Diffusion (Source & Drain) Metal Passivation Non-Doped Polysilicon

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 33 Trench photolithography: Metal mask Fabrication: Trench Etching Exposed Protected Trench Etching: SEM images Trench width = 4.7 µm

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 34 Fabrication: Trench Filling (Polysilicon 1) Trench filling with Polysilicon 1: SEM images Hole width = 3 µm

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 Fabrication: Trench Filling (Polysilicon 2) Trenches are filled with Poly 2, which is then removed from the surface Hole width after Poly 1 deposition (< 3 µm) Doped Poly 1 Non-Doped Poly 2 (inside the trench) Hole width after Poly 2 deposition (350-480 nm) ~1.1 µm 35

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 36 Fabrication: Trench Re-Filling (Polysilicon 2) An additional layer of non-doped polysilicon (300 nm) is deposited. SEM images before the polysilicon etching Trench closed

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 37 650 Ω cm 330 Ω cm 220 Ω cm 160 Ω cm 130 Ω cm

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 38

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 39 Ionization (TID) Effects Two physical mechanisms: Study of Radiation Effects - Accumulation of positive fixed charge within the oxide volume (N OT ) - Formation of charge traps at the Si/SiO 2 interface (N IT ) Expected electrical effects: - Minor effect on V OFF, V drop and I OFF - Degradation of the voltage capability of the Gate-Source junction (V br G-S ) - Impact on edge termination efficiency Increase of I G and/or reduction of V br G-D Displacement Damage (DD) Effects Different effects depending on the operation mode: - OFF-State: Charge generation, reduction of minority carrier lifetime, and trap assisted tunneling are major issues - ON-State: Majority carrier removal and mobility degradation are important Expected effects: - In OFF-State: Increase of V OFF, I OFF and I G - In ON-State: Decrease of I ON, with an increase of V drop

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 40 Study of Radiation Effects Simulation of Ionization (TID) Effects Both mechanisms can be studied with TCAD simulations - N OT and N IT are related with the Dose value by analytical expressions - N OT is introduced as a charge concentration at the Si/SiO2 interface (cm -2 ) or within the oxide volume (cm -3 ) - N IT is introduced as a concentration (cm -2 ) of traps at the Si/SiO2 interface Each trap is modeled with a donor level at Ev+0.8 ev and an acceptor level at Ev+0.3 ev First results show minor effects both for N OT and N IT, only the Edge termination is degraded

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 41 Study of Radiation Effects: Ionizing (TID) Effects Edge Termination quality P-Spray can avoid the degradation of the edge termination efficiency This points are not a real breakdown of the Gate-Drain junction, but an increase of the I G current (injected from the device edge)

A New Vertical JFET Technology for Harsh Radiation Applications ISPS 2016 42 Study of Radiation Effects Displacement Damage (DD) Effects OFF-State issues can be studied with TCAD Simulations - Operating in OFF-state, the V-JFET is like a depleted 3D (trenched) detector - Perugia model of silicon traps (developed for detectors) is applicable here Three levels which concentration is related with the fluence First results show a leakage current increment at same order as that of the detectors ON-State is better studied by irradiation of samples - Operating in ON-State, the V-JFET is like a (lowly doped) silicon resistor - Mobility degradation can be studied by irradiating diode and resistor samples