E Series Power MOSFET SiHD2N5E PRODUCT SUMMARY (V) at T J max. 55 R DS(on) max. at 25 C (Ω) V GS = V.38 Q g max. (nc) 5 Q gs (nc) 6 Q gd (nc) Configuration Single FEATURES Low figureofmerit (FOM) R on x Q g Low input capacitance (C iss ) Reduced switching and conduction losses Low gate charge (Q g ) Avalanche energy rated (UIS) Material categorization: for definitions of compliance please see www.vishay.com/doc?9992 DPAK (TO252) D G S G D S NChannel MOSFET APPLICATIONS Computing PC silver box / ATX power supplies Lighting Two stage LED lighting Consumer electronics Applications using hard switched topologies Power factor correction (PFC) Two switch forward converter Flyback converter Switch mode power supplies (SMPS) ORDERING INFORMATION Package Lead (Pb)free and Halogenfree DPAK (TO252) SiHD2N5EGE3 ABSOLUTE MAXIMUM RATINGS (T C = 25 C, unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage 5 GateSource Voltage V GS ± 3 V Continuous Drain Current (T J = 5 C) V GS at V T C = 25 C.5 I D T C = C 6.6 A Pulsed Drain Current a I DM 2 Linear Derating Factor.9 W/ C Single Pulse Avalanche Energy b E AS 3 mj Maximum Power Dissipation P D 4 W Operating Junction and Storage Temperature Range T J, T stg 55 to 5 C DrainSource Voltage Slope = V to 8 % 7 dv/dt Reverse Diode dv/dt d 27 V/ns Soldering Recommendations (Peak Temperature) c for s 3 C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. V DD = 5 V, starting T J = 25 C, L = 28.2 mh, R g = 25 Ω, I AS = 2.7 A. c..6 mm from case. d. I SD I D, di/dt = A/μs, starting T J = 25 C. THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient R thja 62 C/W Maximum JunctiontoCase (Drain) R thjc. S5278Rev. B, 23Feb5 Document Number: 9636 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
SiHD2N5E SPECIFICATIONS (T J = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage V GS = V, I D = 25 μa 5 V Temperature Coefficient Δ /T J Reference to 25 C, I D = ma.6 V/ C GateSource Threshold Voltage (N) V GS(th) = V GS, I D = 25 μa 2. 4. V GateSource Leakage I GSS V GS = ± 2 V ± na V GS = ± 3 V ± μa = 5 V, V GS = V Zero Gate Voltage Drain Current I DSS = 4 V, V GS = V, T J = 25 C μa DrainSource OnState Resistance R DS(on) V GS = V I D = 6 A.33.38 Ω Forward Transconductance g fs = 3 V, I D = 6 A 3. S Dynamic Input Capacitance C iss VGS = V, 886 Output Capacitance C oss = V, 52 Reverse Transfer Capacitance C rss f = MHz 6 Effective Output Capacitance, Energy pf Related a C o(er) 45 = V to 4 V, V GS = V Effective Output Capacitance, Time Related b C o(tr) 3 Total Gate Charge Q g 25 5 GateSource Charge Q gs V GS = V I D = 6 A, = 4 V 6 nc GateDrain Charge Q gd TurnOn Delay Time t d(on) 3 26 Rise Time t r V DD = 4 V, I D = 6 A, 6 32 TurnOff Delay Time t d(off) V GS = V, R g = 9. Ω 29 58 ns Fall Time t f 2 24 Gate Input Resistance R g f = MHz, open drain.92 Ω DrainSource Body Diode Characteristics MOSFET symbol D Continuous SourceDrain Diode Current I S.5 showing the integral reverse G Pulsed Diode Forward Current I SM p n junction diode 2 S A Diode Forward Voltage V SD T J = 25 C, I S = 7.5 A, V GS = V.2 V Reverse Recovery Time t rr 244 ns Reverse Recovery Charge Q rr T J = 25 C, I F = I S = 6 A, di/dt = A/μs, V R = 25 V 2.5 μc Reverse Recovery Current I RRM 9 A Notes a. C oss(er) is a fixed capacitance that gives the same energy as C oss while is rising from % to 8 % S. b. C oss(tr) is a fixed capacitance that gives the same charging time as C oss while is rising from % to 8 % S. S5278Rev. B, 23Feb5 2 Document Number: 9636 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
SiHD2N5E TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) I D, DraintoSource Current (A) 3 24 8 2 6 TOP 5 V 4 V 3 V 2 V V V 9 V 8 V 7 V 6 V BOTTOM 5 V T J = 25 C R DS(on), DraintoSource OnResistance (Normalized) 3. 2.5 2..5..5 I D = 6 A V GS = V 5 5 2 25 3, DraintoSource Voltage (V) Fig. Typical Output Characteristics 6 4 2 2 4 6 8 2 4 6 T J, Junction Temperature ( C) Fig. 4 Normalized OnResistance vs. Temperature I D, DraintoSource Current (A) 2 6 2 8 4 TOP 5 V 4 V 3 V 2 V V V 9 V 8 V 7 V 6 V BOTTOM 5 V T J = 5 C C, Capacitance (pf) C iss C oss V GS = V, f = MHz C iss = C gs C gd, C ds shorted C rss = C gd C oss = C ds C gd C rss 5 5 2 25 3, DraintoSource Voltage (V) Fig. 2 Typical Output Characteristics 2 3 4 5, DraintoSource Voltage (V) Fig. 5 Typical Capacitance vs. DraintoSource Voltage 3 6 I D, DraintoSource Current (A) 25 2 5 5 T J = 25 C T J = 5 C = 3.4 V C oss (pf) 5 5 C oss E oss 5 4 3 2 E oss (μj) 5 5 2 25 V GS, GatetoSource Voltage (V) Fig. 3 Typical Transfer Characteristics 5 2 3 4 5 Fig. 6 C oss and E oss vs. S5278Rev. B, 23Feb5 3 Document Number: 9636 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
SiHD2N5E V GS, GatetoSource Voltage (V) 24 2 6 2 8 4 = 4 V = 25 V = V I D, Drain Current (A) 2 9 6 3 2 3 4 5 Q g, Total Gate Charge (nc) 25 5 75 25 5 T C, Case Temperature ( C) Fig. 7 Typical Gate Charge vs. GatetoSource Voltage Fig. Maximum Drain Current vs. Case Temperature 65 I SD, Reverse Drain Current (A) T J = 5 C T J = 25 C V GS = V..2.4.6.8..2.4 V SD, SourceDrain Voltage (V), DraintoSource Breakdown Voltage (V) 625 6 575 55 525 5 I D = 25 μa 475 6 4 2 2 4 6 8 2 4 6 T J, Junction Temperature ( C) Fig. 8 Typical SourceDrain Diode Forward Voltage Fig. Temperature vs. DraintoSource Voltage Operation in this Area Limited by R DS(on) I DM Limited I D, Drain Current (A) Limited by R DS(on) * μs ms.. T C = 25 C T J = 5 C Single Pulse BVDSS Limited ms, DraintoSource Voltage (V) * V GS > minimum V GS at which R DS(on) is specified Fig. 9 Maximum Safe Operating Area S5278Rev. B, 23Feb5 4 Document Number: 9636 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
SiHD2N5E Duty Cycle =.5 Normalized Effective Transient Thermal Impedance..2..2 Single Pulse.5..... Pulse Time (s) Fig. 2 Normalized Thermal Transient Impedance, JunctiontoCase R D t p V GS D.U.T. V DD R G V DD V Pulse width µs Duty factor. % I AS Fig. 3 Switching Time Test Circuit Fig. 6 Unclamped Inductive Waveforms 9 % V Q G Q GS Q GD % V GS t d(on) t r t d(off) t f V G Fig. 4 Switching Time Waveforms Charge Fig. 7 Basic Gate Charge Waveform Vary t p to obtain required I AS R G V t p L D.U.T I AS. Ω V DD Current regulator Same type as D.U.T. 5 kω 2 V.2 µf.3 µf V GS D.U.T. V DS Fig. 5 Unclamped Inductive Test Circuit 3 ma Fig. 8 Gate Charge Test Circuit S5278Rev. B, 23Feb5 5 Document Number: 9636 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9 I G I D Current sampling resistors
SiHD2N5E Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period V GS = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. 9 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?9636. S5278Rev. B, 23Feb5 6 Document Number: 9636 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?9
Package Information TO252AA (HIGH VOLTAGE) E E b3 L3 D D H L4 A c2 b e b2 A c L L θ L2 MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. E 6.4 6.73.252.265 L.4.77.55.7 L 2.743 REF.8 REF L2.58 BSC.2 BSC L3.89.27.35.5 L4.64..25.4 D 6. 6.22.236.245 H 9.4.4.37.49 b.64.88.25.35 b2.77.4.3.45 b3 5.2 5.46.25.25 e 2.286 BSC.9 BSC A 2.2 2.38.87.94 A..3..5 c.45.6.8.24 c2.45.58.8.23 D 5.3.29 E 4.4.73 θ ' ' ' ' ECN: S8965Rev. A, 5Sep8 DWG: 5973 Notes. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed. mm per side. 2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. The package top may be smaller than the package bottom. 4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be. mm total in excess of "b" dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. Document Number: 9344 www.vishay.com Revision: 5Sep8
Application Note 826 RECOMMENDED MINIMUM PADS FOR DPAK (TO252).224 (5.69).9 (2.286).87 (2.22).42 (.668).243 (6.8).8 (4.572).55 (.397) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72594 www.vishay.com Revision: 2Jan8 3
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