MICROPROCESSORS LEAKAGE POWER REDUCTION USING DUAL SUPPLY VOLTAGE SCALING

5 th International Advanced Technologies Symposium (IATS 09), May 13-15, 2009, Karabuk, Turkey MICROPROCESSORS LEAKAGE POWER REDUCTION USING DUAL SUPPLY VOLTAGE SCALING Diary R. Sulaiman Electrical Engineering Department, Engineering College, Salahaddin University, Erbil, IRAQ E-mail: diariy@gmail.com Abstract Power efficient design is one of the most important goals for microprocessors, especially in the design of portable, notebook, and handheld computers. In the new high performance designs the static or leakage power is expected to increase because of the exponential increase in leakage currents with technology scaling. The International Technology Roadmap for Semiconductors (ITRS) predicts that leakage power would contribute to 50% of the total power in the next generation processors. Therefore, it is important for system designers to get an early estimate of leakage power to meet the challenging and methodologies for power dissipation reduction. This paper presents a hardware design and implementation for microprocessors leakage power reduction using dual supply voltage scaling, and it can be considered as an effective mechanism for reducing processors power and energy while preserving performance by scaling the supply voltage at runtime depending on the workload variation. SPICE simulation program is used to verify the theoretical idea and confirm the hardware operations. Keywords: Dual supply voltage scaling. 1. Introduction Power dissipation reduction, as mentioned is an important consideration in the design of microprocessors, especially battery-powered portable devices, and emerges as a key technology in the VLSI system design. The high power dissipation results in increased packaging and cooling costs as well as potential reliability problems. Then, the low power design is required for a battery-powered device to extending the battery service life, while meeting performance requirements [1]. Today most digital circuits are constructed using CMOS circuits, especially processors, therefore the analysis of leakage power dissipation in CMOS circuits is essential to find out the sources of power dissipation, and the elements of each source with its influences. There are three sources of power dissipation in CMOS circuits. The total power dissipation of a CMOS circuit can be expressed as [2], P + total = Ps + Pd Psc (1) Where, P s is the static power dissipation, P d is the dynamic power dissipation, P sc is the short circuit power dissipation. P d is the dominant component of the P total in the current manufacturing technologies which include P sc also. For 0.18µm technology at 100 C, leakage energy dissipation is estimated to be 7% of the total energy dissipation, meaning that the rest 93% is dynamic energy dissipation. As the technology scales down, for the same die in a smaller technology, at the same temperature level static energy dissipation percentage is expected to go up as much as 50% in the future technology generation [3]. Figure 1 shows the power dissipation components of a typical CMOS inverter, Figure 1: Power dissipation components of a typical CMOS inverter - P s can be expressed by the equation, n P = Leakage Current SupplyVoltage (2) s * 1 When the transistors of the CMOC inverter above are all off, there is still some energy dissipation occurs in the circuit because of the leakage current passing through the transistors, this leakage current can be expressed by [4], qv / KT I = i e( 1) (3) leakage s Where, i s = reverse saturation current, V = diode voltage, q = electronic charge, k = Boltzmann s constant (1.38x10 23 J/K), T = temperature [5]. Static energy dissipation is the product of the leakage current and the supply voltage from which the leakage current is drawn. - P d can be expressed by the equation, P 2 d = CL Vdd f clk (4) Where, C L is the collective load capacitance, V dd is the supply voltage, and f clk is the clock frequency. When any transistor in the CMOS circuit makes a transition, the capacitances on its nodes are either charged or discharged causes dynamic energy dissipation. This dynamic energy dissipation directly depends on the sizes of capacitances on the terminals of the transistors [2,5]. IATS 09, Karabük University, Karabük, Turkey

- P sc can be expressed by the equation, t P ) rf scα ( Vdd 2V t (5) t p transistor channel because of the V dd potential on the V DS. Figure 3 shows the variation of the drain current of an NMOS transistor as a function of the gate voltage in 0.18µm technology [8]. Where, V t is the threshold voltage, t rf is the rise time or fall time, t p is the period of the input waveform. P sc is occurs when both the pull-up and pull-down transistors of a CMOS gate are simultaneously on. There are three main techniques to reduce static or leakage power dissipation in microprocessors CMOS building blocks, design and implementation of low leakage transistors, dynamic threshold modulation, and finally using dual supply voltage scaling [4,5]. During the five years ago, there are many subjects related to the topic, H. Qin in [6] investigate the voltage limit of SRAM standby operation for Low Leakage Standby Operation, M. A. Sheets in [7] presents a structured methodology and architecture for the implementation and control of power domains to form a power managed system. This paper presents additional hardware design for microprocessors system to reduce leakage power using dual supply voltage scaling at runtime depending on the workload variation; SPICE simulation program shows satisfactory results. 2. Leakage Power Analysis In high performance portable, handheld, and notebook computer architectures, the leakage component of total consumed power was increased with technology scaling, which exceeds 50% of the total consumed power as ITRS indicated [3]. There are four leakage mechanisms contribute to the total leakage in a CMOS inverter as shown in figure 2, Figure 2: The four main leakage components in an NMOS transistor These four leakage current components are: - Subthreshold leakage current (I SUB) - Gate direct tunneling leakage current (I GATE) - Reverse biased leakage current (I REV) - Gate induced drain leakage current (I GIDL) The subthreshold leakage current (I SUB) is the main part in the four components above due to the diffusion current of the minority carriers in the channel for a MOS device. For a low input voltage in a CMOS inverter shown in figure 1, the output will be high, in this case V GS is 0, but there is still a subthreshold leakage current passing in the NMOS Figure 3: The drain current of a n-type MOSFET as a function of the V GS The magnitude of the subthreshold current is a function of both process, device sizing (W/L), and supply voltage V dd [9]. The process parameter that predominantly affects the current value is V t. Reducing V t exponentially increases the subthreshold current, which is proportional to V DS, or equivalently, V dd. Gate direct tunneling leakage current (I GATE) results from the Fowler-Nordheim tunneling of electrons into the conduction band of the oxide layer under a high applied electric field across the oxide layer. I GATE depending on the tunneling probability function and the number of tunneling carriers. The magnitudes of the gate direct tunneling current increases exponentially with the gate oxide thickness T ox and supply voltage V dd. As transistor length and gate oxide thickness are scaled down supply voltage must also be reduced to maintain effective gate control over the channel region. Reverse biased leakage current (I REV) occurs from the source or drain to the substrate through the reverse-biased diodes when a transistor is OFF. For an inverter with low input voltage the NMOS is OFF, the PMOS is ON, and the output voltage is high. Then, the drain-to-substrate voltage of the OFF NMOS transistor is equal to the supply voltage. This cause a leakage current from the drain to the substrate through the reverse-biased diode. The magnitude of this leakage current depends on the area of the drain diffusion and the leakage current density, which is in turn determined by the doping concentration [10]. Gate induced drain leakage current (I GIDL) is caused by high field effect in the drain junction of MOS transistors. For an NMOS transistor with grounded gate and drain potential at V dd. The I GIDL is made worse by high drain to body voltage and high drain to gate voltage. I GIDL Magnitude increases as thinner oxide and supply voltage increase. Figure 4 shows the amount leakage power prediction of the total power for the next generation CMOS technology.

Where, k is function of the technology, V T is the thermal voltage, V t is the threshold voltage, V GS is the gate to source voltage, V DS is the drain to source voltage, and η is the subthreshold swing coefficient [8]. Figure 4: Leakage & total power Vs. CMOS technology scaling Then, the reduction of leakage power can significantly reduce the total power dissipated in CMOS VLSI circuits. Also, many times a large number of CMOS circuits spend a long time in a standby mode where the leakage power is the only source of power consumption. 3. Subthreshold leakage current (ISUB) Leakage power consumption has become an important factor in the design of high performance portable, handheld, and notebook processors. Process scaling has resulted in a continual reduction in the supply voltage to reduce the total power consumption and maintain circuit performance. The subthreshold leakage power trends is shown in figure 5 [11]. It is clear from the equation 6, that the reduction of threshold voltage by 100 mv increases the subthreshold leakage current by a factor of 10. Decreasing the length of transistors increases the subthreshold leakage current as well. Therefore, in a chip, transistors that have smaller threshold voltage and/or length due to process variation contribute more to the overall leakage. Although the leakage current was important in systems with both active and inactive periods [13]. So, the subthreshold leakage current reduction is a critical design concern in any system in today s designs because it increases UPS or battery lifetime, reducing temperature, decreasing the production cost, and extended the IC lifetime. Dual supply voltage scaling is an effective technique to reduce subthreshold current, leakage power, dynamic power (equation 4), and then the total power consumption in CMOS integrated circuits, especially processors at standby and varied workload condition using high threshold transistors called sleep transistors. As the supply adjusted between the two values V ddh and V ddl based on the workload prediction to complete the specific task with a targeted latency. Adjusting the supply voltage restricts the operating frequency accordingly because, f ( V V ) 2 dd t clk = (7) Vdd Meaning that changes in frequency are accompanied by appropriate adjustment in voltage. Figure 6, shows the reduction of the leakage power, dynamic power, and total power dissipation depending on the supply voltage adjustments [14], Figure 5: Subthreshold Leakage power trends The subthreshold leakage current is the current that is conducted through a transistor from its source to drain when the device is intended to be off. Because of the dramatic increase in subthreshold current as shown in figure 5, static power consumption is now one of the primary issues in deep submicron design and can account for as much as 50% of the total power dissipation for today s processors. Then the subthreshold leakage power has become the dominant factor in the total power dissipation and battery life time due to the growing difficulty in controlling the device dimensions and characteristics [12]. In the current CMOS technologies subthreshold leakage current is much larger than the other three leakage current components because of the lower threshold voltage and increasing short channel and drain induced barrier lowering effects, and is can be expressed by the equation, I sub = k V VGS Vt VDS 2 η VT V T e (1 e T ) (6) Figure 6: Leakage power, dynamic power, and total power dissipation with supply voltage (V dd) adjustment for a fixed clock frequency (f clk) 4. Dual Supply Voltage Scaling Microprocessors with dual supply voltages scaling technique have the dramatic effect on power consumption reduction when a specific computer system is in consideration; this technique can significantly reduce dissipated power without degrading speed by selectively

lower supply voltage along non-critical delay paths or light workloads and higher supply voltage among heavy workloads. This work focuses on dual supply voltage usage. However, the same technique can be used in more than two supply voltage designs as well. The main problem of designing dual supply voltage scaling in CMOS circuits is the increased leakage current in the high voltage gates when a low voltage gate is driving a high voltage gate. Figure 7 shows the case when a low voltage inverter is driving a high voltage inverter. [15]. Figure 8: Block diagram of battery powered system To avoid problems of level converter, domino logic, and CVS circuits, the complete circuit of DC-DC converter using buck-converter topology shown in figure 9 is designed, Figure 7: A low voltage inverter driving a high voltage inverter. To solve the problem of increased leakage current additional circuit of level converter is required, but it introduced area, and energy overhead. To reduce level converter problems some researchers proposed clustered voltage scaling (CVS), in such techniques no low voltage gate will drive a high voltage gate [16]. Both of these techniques introduce additional constraints to the dual supply voltage scaling process, and reducing the obtainable energy savings. Domino logic, however, does not require level shifting due to the lack of the PMOS tree in the domino gates, while the necessity to generate and route the additional supply voltages remains [17]. Other researchers introduced gate-level dual supply voltage assignment that requires the use of level shifters when a high voltage gate is driven by a low voltage gate. The level shifting circuitry in the optimized circuits constitutes 8% of the total energy consumption [18]. Battery-powered digital systems which are typically present in portable electronic devices such as cellular phones, notebook, and handheld computers, consist of the microprocessor, the DC/DC converter, voltage controlled oscillator (VCO), supply voltage control unit, and workload predictor as shown in the block diagram shown in figure 8. The control unit of the high frequency DC-DC converter applicable to dual supply voltage CMOS circuits is presented in order to provide two voltage levels with low energy consumption. The workload predictor unit predicts the cycles required for the next program execution tasks by calculating both the idle and event times, and then estimate the workload is it light or heavy to generate a control signal to the Vdd control unit in order to select the high or low supply voltage. The VCO (ring oscillator) converts the output of the DC-DC converter to a clock frequency. The DC-DC converter output with the generated clock frequency is fed to the processor. Figure 9: The complete design of DC-DC converter using buck converter topology The two outputs are connected electronically in the control unit to produce a single output voltage, which is controlled by a wakeup command from the workload predictor to select VO1 or VO2, where the processor workload is divided into light and heavy workloads based on program cycles calculation. The VCO (ring oscillator), which is designed depending on the range of the clock frequency and time delay of one CMOS stage, converts the output of the DC-DC converter to a clock frequency which is fed to the processor [19]. 5. Simulation Results The complete hardware of dual supply voltage scaling of figure 9 has been designed, and then simulated Using SPICE simulator program depending on the A. Thomas measurement platform circuitry shown in figure 10 [20].A sense resistors with a value of 0.01 Ohms is used. The voltage drop measured across the sense resistor is amplified by the LT178 current sense amplifier and sent to the pin labeled output. This voltage can be measured by placing probes at both the output node and the ground node. Figure 10: A. Thomas circuit overview

Using A. Thomas measurement platform circuit above the simulation results of table 1&2 are obtained using different Benchmark programs, Table 1: Simulation results of leakage & total power consumption using different benchmark programs. Benchmarks Cycles (10 6 ) Selected Power Supply Leakage Power (W) Total Power (W) ARMARM9E 425.68 V ddl 10.73 26.57 TIOMAP1610 310.24 V ddl 10.07 25.16 APPLU 1624.80 V ddh 14.63 36.58 TURB3D 4567.17 V ddh 15.75 39.49 TOMCATV 1420.47 V ddl 13.27 32.37 HYDRO2D 2756.15 V ddh 15.15 37.88 SWIM 444.12 V ddl 11.43 27.23 HTELPXA255 210.34 V ddl 09.24 24.56 Table2: Simulation results of energy saving using different Benchmark programs Benchmarks Energy Saving (%) ARMARM9E 11.67 TIOMAP1610 13.24 APPLU 13.25 TURB3D 08.13 TOMCATV 09.13 HYDRO2D 12.34 SWIM 12.16 HTELPXA255 13.25 The simulation results of table 1&2 using eight benchmark programs (ARMARM9E, TIOMAP1610, APPLU, TURB3D, HYDRO2D, SWIM,, and HTELPX255) which are used in our tests for measuring leakage power, total power, and energy saving, can be sketched as in the figures 11&12. Figure 11: Simulation results in graphical form of leakage power & total power consumption using different benchmark programs Figure 12: Simulation results in graphical form of energy saving using different benchmark programs. The simulation results shows that, the leakage power consumption is about 41.11% of the total power consumption, and the saved energy is 11.64% for the used benchmark programs. 6. Conclusion This paper introduced a hardware design for microprocessors energy reduction using dual supply voltage scaling technique, which can be considered as an effective mechanism and critical constraint for the current and future microprocessors energy consumption reduction, and can improve the energy efficiency of battery-powered processor systems, especially for portable, handheld, and notebook devices. The fully design of DC-DC converter using buck converter topology restrict the usage and problems of level converter, domino logic, and CVS circuits The SPICE simulation results yields that the leakage power is about 41.11% of the total power consumption, and 11.64% of energy saving is achieved for the used benchmark programs. This technique provides significant reduction in measured system energy consumption, thus significantly extending battery life. Therefore, Dual supply voltage scaling technique is becoming commonplace in high performance microprocessor systems to save power and increase processing speeds. 7. References [1] M. Horowitz, T. Indermaur, and R. Gonzalez, Low- Power Digital Design, IEEE Symposium on Low Power Electronics, pp.8-11, 1994. [2] B. H. Calhoun, and A. P. Chandrakasan, Standby Power Reduction Using Dynamic Voltage Scaling and Canary Flip-Flop Structures, IEEE Journal of Solid- State Circuits, Vol. 39, No. 9, September 2004. [3] Bose P., Brooks D., Irwin M., Kandemir M., Martonosi M., Vijaykrishnan N., Power-Efficient Design: Modeling and Optimizations, tutorial notes, the International Symposium on Computer Architecture (ISCA-28), Goteborg, Sweden, July 2001. [4] Miyatake H., Tanaka M., Mori Y., A design for highspeed low power CMOS fully parallel contentaddressable memory macros, IEEE Journal of Solid- State Circuits, Volume: 36 Issue: 6 V pp. 956-968, Jun 2001.

[5] N.E. Weste, K. Eshraghian, Principles of CMOS VLSI Design, 2nd Edition, Addison Wesley Publishers, 1993. [6] H. Qin, Deep Sub-Micron SRAM Design for Ultra-Low Leakage Standby Operation, PhD thesis, University of California, Berkeley, spring 2007. [7] M. A. Sheets, Standby Power Management Architecture for Deep-Submicron Systems, PhD thesis, University of California, Berkeley, spring 2006. [8] V. Kursum, Supply and Threshold Voltage Scaling Techniques in CMOS Circuits, PhD Thesis, University of Rochester, New York, 2004. [9] S. Sze, Physics of Semiconductor Devices, Wiley, New York, 1981. [10] Y.Lu and V.D.Agrawal, Statistical Leakage and Timing Optimization for Submicron Process Variation, In Proceedings of 20th International Conference on VLSI Design, 2007. [11] B.S. Deepaksubramanyan and A. Nu nez, Analysis of Subthreshold Leakage Reduction in CMOS Digital Circuits, In Proceedings of the 13th NASA VLSI Symposium, Post Falls, Idaho, USA, June, 2007. [12] R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, Statistical Analysis of Subthreshold Leakage Current for VLSI Circuits, IEEE Transactions on Very Large Scale Integration Systems (T-VLSI), Vol. 12, No. 2, pp 131-139, February 2004. [13] A. Abdollahi, F. Fallah, and M. Pedram, Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits, In Proceedings of Symposium on Low Power Electronics and Design, pp. 213-218, Aug. 2002. [14] P.J.M. Havinga, G.J.M. Smit, Design Ttechniques for Low Power Systems, Journal of Systems Architecture, Vol. 46, Issue 1, 2000. [15] Y. Cao, T. Sato, M. Orshansky, D. Sylvester, and C. Hu, New paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Simulation, IEEE Custom Integrated Circuits Conference Proceedings (CICC 2000), pp. 201-204. 2000. [16] J. M. Chang, and M. Pedram, Energy Minimization Using Multiple Supply Voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, pp. 436-443, 1997. [17] A. Srivastava, and D. Sylvester, Minimizing Total Power by Simultaneous V dd-v th Assignment, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, pp. 665-77, 2004. [18] K. Usami, K. Nogami, M. Igarashi, F. Minami, Y. Kawasaki, T. Ishikawa, M. Kanazawa, T. Aoki, M. Takano, C. Mizuno, M. Ichida, S. Sonoda, M. Takahashi, and N. Hatanaka, Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor, In Proceedings of theieee Custom Integrated Circuits Conference, Santa Clara, CA, USA,. pp. 131-134., May, 1997. [19] R. K. Krishnamurthy, L. R. Carley, Exploring the Design Space of Mixed Swing Quad Rail for Low Power Digital Circuits, IEEE Trans. VLSI Systems, vol. 5, pp383-400, December 1997. [20] A. Thomas, A Measurement Platform for DVS Algorithm Development and Analysis, B. Sc. Thesis, University nof Virginia, April, 2003.