Research Joural of Applied Scieces, Egieerig ad Techology 9(3): 45-57, 205 DOI:0.9026/rjaset.9.389 ISSN: 2040-7459; e-issn: 2040-7467 205 Maxwell Scietific Publicatio Corp. Submitted: September 25, 204 Accepted: September 25, 204 Published: Jauary 25, 205 Research Article Modelig ad Aalysis of Cascade Multilevel DC-DC Boost Coverter Topologies Based o H-bridge Switched Iductor R. Aad ad 2 I. Gaambal Departmet of Electrical ad Electroics Egieerig, Mahedra College of Egieerig, 2 Departmet of Electrical ad Electroics Egieerig, Govermet College of Egieerig, Salem, Idia Abstract: I this study ivestigatio is doe o a H-bridge switched iductor base cascade multilevel DC-DC boost coverter. The proposed multilevel DC-DC boost coverter topology improves the coversio efficiecy of traditioal topology. The proposed boost coverter topology is differig from the traditioal topology by the additio of switched iductor circuit. The switched iductor improved the coversio ratio gai of the boost coverter circuit. The switched iductor provides a very large output voltage with differet output DC levels which makes it suitable for multilevel applicatio. The, the mode I ad mode II of operatio of switched iductor are aalyzed. The use of proposed switched iductor base multilevel DC-DC boost coverter improved the power quality ad reduced the switchig frequecy. The proposed DC-DC boost coverter topology simulated i MATAB/Simulik workig platform ad the coversio performace is evaluated. The, the coversio performace of proposed H-bridge switched iductor based topology is compared with sigle level ad multilevel cascade boost coverter topologies. Keywords: Cascade multilevel, DC-DC boost coverter, operatio mode, switched iductor INTRODUCTION Now-a-days, for power coversio multilevel coverters have attracted iterest i power idustry (Rosas-Caro et al., 2008; ai ad Peg, 996), sice; the multilevel coverters already are a very importat alterative i high power applicatios (Rodriguez et al., 2002). I almost all power coversio processes such as ac-dc, dc-ac, dc-dc ad ac-dc-ac, it has bee show that multilevel coverters are advatageous (Peg, 200). ow harmoic distortio, low voltage stress, low EMI oise, low switchig frequecy, high efficiecy, ability to operate without magetic compoets are some of the advatages of multilevel coverters cotrary to traditioal topologies (Rosas-Caro et al., 200a; Ortuzar et al., 2006). All these advatages make multilevel coverters oe of the best importat topics i power electroics ad idustrial applicatio research ad i some applicatios they ca get modular topologies (Nilkar et al., 20). There are several advatages for multilevel DC-DC boost coverter (Samosir et al., 20; Hwu ad Yau, 200) such as fewer compoets, self-voltage balacig ad high voltage gai without usig a extreme duty ratio ad without employig a trasformer (Mayo-Maldoado et al., 20a, b; Kouro ad Wu, 2009). Furthermore, without modifyig the mai circuit more levels ca be added (Mayo-Maldoado et al., 200a). The multilevel coverter derived from the basic types of dc-dc coverters which are buck, boost (Park ad Choi 200), buck-boost, cuk, sepic ad Zeta (Axelrod et al., 2008; Hwu ad Yau, 2009). I the high power applicatio, the trasformer based coverter is ecessary, as i a power coverter the voltage coversio ratio is a purpose of the modulatig cotrol sigal of the active switch (eyva-ramos et al., 20a). For implemetig a trasformer less dc-dc coverter with high efficiecy ad high boost ratios, a umber of topologies are preseted (Mayo-Maldoado et al., 200b). A multilevel coverter cosists of pricipally a array of power semicoductors ad coverters that produce a output voltage of stepped shape by likig its output termials to more tha oe differet voltage sources (Cecati et al., 200). Neutral poit clamped, flyig capacitor ad cascaded H-bridges multi-level structures are also icluded i the class of DC-DC coverters (Karugaba et al., 2008). The switched iductor multilevel boost coverter is a high gai DC-DC coverter to feed ay applicatios that require high DC voltage or to feed multilevel iverter that is used i AC applicatios that requires low total harmoic distortios. Similarly, it ca achieve high gai without icreasig the duty cycle ad it is the mai advatage of the multilevel boost coverter (Mousa et al., 200). I the covetioal coverter, a very good ad probably expesive driver circuit is Correspodig Author: R. Aad, Departmet of Electrical ad Electroics Egieerig, Mahedra College of Egieerig, Salem, Idia This work is licesed uder a Creative Commos Attributio 4.0 Iteratioal icese (UR: http://creativecommos.org/liceses/by/4.0/). 45
eeded; whe extreme duty cycle is applied (Jiao ad uo, 20). Oly oe switch is used for reducig the cost effect i multilevel DC to DC boost coverter (Mousa et al., 200). But, that icreased the switchig frequecy of the MOSET hece, the coversio voltage is deviated from the expected level ad the output voltage is affected high oscillatio (opez et al., 2008). To achieve better dyamic performace, multi switch iterleaved coverters are used with small iductors ad high switchig frequecy (Wag et al., 20). I literature several related works are already available which is based o multilevel DC-DC boost coverters. Some of them are reviewed here. She et al. (2008) have proposed a multilevel dc-dc power coversio system with multiple dc sources. Very high temperature operatio was possible with this magetless system. Power loss ad efficiecy aalysis was provided. Rosas-Caro et al. (200b) have proposed a DC-DC coverter topology. The DC-DC multilevel boost coverter (MBC) was a pulse-width modulatio (PWM)-based DC-DC coverter. To provide differet output voltages ad a self-balaced voltage usig oly oe drive switch, oe iductor, diodes ad capacitors for a Nx MBC, which combies the boost coverter ad the switched capacitor fuctio. Mayo-Maldoado et al. (20c) have proposed several dyamic models. The model is maily developed for a DC-DC multilevel boost coverter. Zhao et al. (20) have proposed multilevel circuit topologies. Based o switched-capacitor ad diodeclamped coverters (MCT-BSD), they are called multilevel circuit topologies. Rosas-Caro et al. (20) have preseted a topological derivatio of PWM DC- DC coverters. The structure of the coverters is very simple ad provides high-voltage gai. Boost, buckboost, Cuk ad SEPIC are the traditioal topologies that are discussed. Nami et al. (20) has proposed H-bridge multilevel pulse width modulatio coverter topology. This topology is developed based o a series coectio of a high-voltage diode-clamped iverter ad a lowvoltage covetioal iverter. iu et al. (202) have proposed a cascade active-frot-ed coverter. It was developed based o dual-boost/buck coverters, sice it allows regulatig the power factor to cotrol both the active ad reactive powers betwee medium ad low voltage levels. It has much ehaced system reliability compared to the traditioal cascade H-bridge coverter. eyva-ramos et al. (20b) have proposed a average curret-mode cotroller desig methodology for a N-stage cascade boost coverter. This class of coverters has -C filters; thus, it would exhibit 2order characteristic dyamics. The proposed scheme employs the iductor curret of the iput stage ad the capacitor voltage of the output stage; thus, there were (-) capacitor voltages ad (-) iductor currets that were ot used for feedback purposes. The sesed curret could also be used for oe-cycle overload protectio; therefore the full beefits of curret-mode cotrol were maitaied. The reaso is used for oly a reduced set of scheme as feedback variables the system. Also, the C filters are used to reduce the oscillatio of output coversio. The review shows that, the multilevel DC-DC coverter devices have bee used i switch power semicoductors at icreasigly high frequecies i order to miimize harmoics ad reduce passive compoet sizes. However, the icrease i switchig frequecy icreases the switchig losses which become especially sigificat at high power levels. For icreasig the coversio efficiecy of DC-DC coverter several topologies are used. The three mai topologies used are the diode-clamped multilevel, capacitor-clamped multilevel ad cascaded multilevel. The diode-clamped multilevel coverter is relatively simple, but eeds a large umber of diodes to clamp the switch voltage stress. The capacitor-clamped multilevel coverter is more flexible tha the diode-clamped multilevel coverter, but it eed large umber of capacitors to clamp the voltage. Both the diode-clamped ad capacitor-clamped multilevel coverter have a key drawback that there are o voltage boostig feature, amely the output peak-to-peak ac voltage, which must be the same as the iput dc voltage. The cascade coverter is required i may isolated dc-dc coverters. I this study, the multilevel cascade DC to DC boost coverter with H-bridge switched iductor based topology is proposed. I this study, a switched iductor based multilevel cascade bridge DC to DC boost coverter is proposed to overcome this problem. Each bridge has oe switch ad the switch is coected with switched iductor, i the proposed coverter. For reducig the switchig frequecy ad improvig the coversio voltage, the switch iductor is used. PROPOSED MUTIEVE CASCADE DC TO DC BOOST CONVERTER The multilevel cascade dc to dc boost coverter is the extesio topology of sigle level boost coverter. The use of multilevel coverter is to improve the coversio ratio ad efficiecy of the coverter. The mai advatage of the multilevel topology is that the voltage coversio ratio is directly ehaced by the additio of levels. The multilevel cascade dc to dc boost coverter is illustrated i Fig.. Figure, the iput source of boost coverter is deoted as V s. The th level of the dc to dc coverter iductace, diode, switch ad capacitor are deoted as, D, S ad C respectively. The, the N th level of the coverter compoets are deoted as, D, S ad C respectively. Whe the switches (S, S 2 S ) ON i Fig., the iductors, 2,. are coected to the iput 46
Fig. : Structure of cascade DC-DC boost coverter voltage (Vs). The output voltage of C is smaller tha voltage through D 2, D. At the same time, the egative level of voltages of C 2, C is equal to the positive level value of C. Hece, the total voltage across C 2..C is smaller tha C. Durig the turs off coditio of switches, the iductor curret is closed to D of all switched diodes. Throughout the switch off coditio, the iductor curret closes D chargig C ad the output voltage level is resulted as the coverter voltage. The voltage o the C is equal to the summig up voltage o the iput source ad the voltage level of C 2..C. Thus, it is possible to achieve high voltage gai agaist the duty cycle. But, whe iclude the switched iductor circuit; the switchig frequecy level is limited with high gai (iu et al., 203). Therefore, the proposed coverter is suitable for chargig power i photovoltaic applicatios (Deivasudari et al., 203). Moreover, the peak curret of iductor is limited by switched iductor so o additioal protectio circuit is required (Che, 203). Accordig to the cosideratio of geeral coverter operatio, these coverters work i the steady state with the coditio of Cotiuous Coductio Mode (CCM). Here, the coductio duty ratio is deoted as, the switchig frequecy is, the switchig period is T = ad the load is R load. The iput voltage ad f curret are deoted as Vi ad I i respectively. The output voltage ad curret are V O ad I O. Durig the 47 coversio process, the coversio output without power loss is V I = V I. The voltage trasfer i i out ratio gai is deoted as which is described as followig them: out V G = o () Vi The equivalet circuit diagram o oe level boost coverter circuits durig switch-on ad switch-off are illustrated i Fig. 2 as follows: The charged voltage across the capacitor C is deoted as V O. The curret flowig through the iductor is deoted as i. The curret (i ) flowig through iductor icreases with voltage V i durig switch-on period DT ad decreases with voltage V V ) durig switch-off period ( D)T. ( o i Hece, the ripple of the iductor curret is expressed as follows: VIN Vo Vi i = DT = ( D)T (2) The, the average curret through the iductor is expressed as follow: i V ( D) o R = (3)
This value is substitute i equatio () ad the gai equatio is described as follows: G = (7) D Similarly, the output voltage variatio ( ) is determied. That is expressed as follows: (a) Vo 2 D ε = = (8) V o 2 RfC where, = The duty cycle = The frequecy i Hz The above described equatios are the correspodig equatio of sigle stage DC to DC boost coverter. (b) Fig. 2: Equivalet circuit of (a) switch-on ad (b) switch- OFF From the above expressio, the iductor curret variatio ( ε ) is determied. The iductor curret variatio is the ratio of the ripple curret of the iductor ( ) ad the average curret of the iductor ( i ) i which is expressed as followig them: i 2 ε = (4) i I the above equatio, the values of i ad i are substitute. The, the equatio is expressed as follow: CASCADE MUTIEVE DC-DC BOOST CONVERTER WITH H-BRIDGE SWITCHED INDUCTOR The, the multilevel cascade boost DC to DC coverter with H-bridge switched iductor topology is described. Here, the purpose of the switched iductor is used to reduce the switchig frequecy of the coverter. Hece, the power loss is reduced durig coversio process, so the power quality got improved. The switched iductor provided a very large output voltage with differet output DC levels which makes it suitable for multilevel applicatio. The H-bridge switched iductor based multilevel boost coverter topology is illustrated i the followig Fig. 3. For multilevel th stage boost coverter, the output voltage, the gai, curret variatio ad the voltage variatio equatios are writte as follows: Vo = V (9) IN D ε V = o V i ( D) V o D R T 2 (5) I the above equatio, the output voltage is expressed as follows: Vo = V (6) IN D 48 G = (0) D V o Vi ( D) i ii T 2( + ) 2 2 i ε = = () i V i Vo 2 D = = Vo 2 RfC ( D) o R ε (2)
Fig. 3: Proposed H-bridge switched iductor base cascade dc-dc boost coverter (a) 49
Fig. 4: H-bridge switched iductor base cascade dc-dc boost coverter while (a) Mode I operatio ad (b) Mode II operatio I the proposed multilevel DC to DC boost coverter model, the iductor resistace R ad the capacitor resistace are described as below: dvc i C = dt ( S ) i di i = SVi dt V IN D i R io D ( S ) V IN Rii RVCi R R V C 0 = + R + RC R + RC ( S ) i i ) i o (3) (4) (5) where, i,2, K. The, S i is the switch which used i the coverter topology. C i is the i th capacitor ad i is the i th iductor. The V O ad i O are the output voltage ad curret, respectively. (b) 50 The above described switched iductor operatio is same as the traditioal cascade coverter. But, here the switched iductor operatio is oly differet from the omial circuit operatio. The switched iductor is operated by iductive priciple which cosists of two operatio modes. The mode of operatio of switched iductor is based o the D s, ad S. The detailed descriptio of H-bridge switched iductor is give i the followig sectio. Mode of operatio of h-bridge switched iductor circuit: The switched iductor simple switchig dual structures, formed by either two 2-3 diodes, or two iductors ad 2-3 diodes are defied. These circuit blocks ca provide either a step-dow of the iput voltage or a step-up of it. They are iserted i classical boost coverters to provide ew power supplies with a steep voltage coversio ratio. As their complexity i terms of circuit elemets is comparable to that of the quadratic coverters, their performaces (voltage ratio, stresses, efficiecy) will be compared to that of available quadratic circuits. Accordig to the coductio of iductor ad diode, the mode of operatio of switched iductor is categorized ito two types which are illustrated i Fig. 4.
Mode I: I mode I operatio (Fig. 4a), the diodes are coducted, ot coducted ad also, the curret flows through the both iductors. Durig this mode, the switches are directly coducted ad the capacitor is charged idirectly. The curret flows through the switched iductor (Mode I) is expressed as below: i t = i ( V + i 2 di RV i Ci = dt R + R 0 + V ) VD 2 S2 3 t ( V + V2 ) V ( DS + DS ) 3 = + 0 2 C RRC + R + R C (( S )) (6) (7) The Eq. (7) is the output voltage of multilevel cascade boost coverter with switched iductor. Where, DS is the combiatio of diode D ad 2 3 S D, S 2 is the combiatio of iductor ad respectively. 2 Mode II: I mode II operatio (Fig. 4b), the diodes, are ot coducted ad is coducted. The, the curret flows through the both iductors. Durig this mode, the switches are OFF stage so, the capacitor is charged directly. The curret flows through the switched iductor (Mode II) is expressed as below: i t = i ( V + i 2 RVCi Vo = R + R 0 C = t + V ) VD ( V + V ) VD 2 S2 + 0 2 R RC + R + R 2 S2 2 C (( S )) (8) (9) The switch S is rotated ON; the diodes D S-3 are furthermore rotated ON at the similar time i the suggested coverter. Over through this operatig state, the diodes D S ad D S3 are offered a cosecutive curret path for correspodig iductors of the th stage of the coverter. O the subsequet phase, the switch S is tured OFF, the diodes D S2 is furthermore tured ON at Fig. 5: Simulik model of H-bridge switched iductor with multilevel DC to DC boost coverter topology 5
the similar time. The diodes D S2 supply a cosecutive curret path for correspodig iductors of the th stage of the coverter through this operatig coditio; whereas i this operatig coditio, diodes D S ad D S3 are rotated OFF. Hece, the operatio of the multilevel cascade is the same at the fial level of the coverter ad the resultig coversio proportio is foud out. IMPEMENTATION RESUTS AND DISCUSSION The proposed H-bridge switched iductor based DC to DC boost coverter topology was simulated i MATAB/Simulik workig platform. The, the coversio performaces of sigle level, multilevel ad H-bridge switched iductor topologies are aalyzed. The switchig frequecies of IGBT switchig voltage are aalyzed by differet simulatio time. Also, the voltage coversio capability of the proposed topology is aalyzed with coversio gai ad duty cycles correspodigly. The performace of the cascade bridge circuit was tested with five level output series cascadig capacitor bridges. The simulik model of H- bridge switched iductor based cascade DC to DC boost coverter topology is illustrated i Fig. 5. The implemetatio parameters of the DC to DC boost coverter model is described i Table as follow. Table : Implemetatio parameters ad values Compoets Parameters Values Series iductace 400 e-6h IGBT Resistace (R o) 0.0 Ohms Forward voltage (V f) V Curret 0% fall time e-6 sec (T f) Curret tail time (T t) e-6 sec Subber resistace (R s) 0000 Ohms Diode Resistace (R o) 0.05 Ohms Forward voltage (V f) 0.8 V Subber resistace (R s) e5 Ohms Switched iductor Series iductace ( 400e-6 H ad 2) Diode (D s, D s2 ad D s3) Resistace (R o) 0.05 Ohms Forward voltage (V f) 0.8 V Subber resistace (R s) e5 Ohms From the simulik model, the performace of iductor curret, capacitor curret, diode curret, load voltage ad switchig voltage of the IGBT are examied. The performaces of sigle level model, multilevel model ad H-bridge switched iductor model are illustrated i Fig. 6 to 9 respectively. The compariso of coverter voltage is illustrated i Fig. 0. The, the gais of the sigle level, multilevel ad H- bridge level (proposed) topologies are aalyzed at differet duty cycles. The duty cycle ad gai are tabulated i Table 2. After that, the performace of the gai vs. duty cycle ad the deviatio chart are give i Fig. 6: Theoretical performace of; (a): Iductor curret (I ); (b): Capacitor curret (I C ); (c): Diode curret (I d ); (d): oad voltage (V ce ) ad; (e): IGBT switchig voltage (V R ) 52
Fig. 7: Performace of iductor curret (I ), capacitor curret (I C ), load voltage (V ce ), diode curret (I d ) ad IGBT switchig voltage (V R ) by sigle level dc-dc boost coverter Fig. 8: Performace of iductor curret (I ), capacitor curret (I C ), load voltage (V ce ), diode curret (I d ) ad IGBT switchig voltage (V R ) by multilevel dc-dc boost coverter 53
Fig. 9: Performace of iductor curret (I ), capacitor curret (I C ), load voltage (V ce ), diode curret (I d ) ad IGBT switchig voltage (V R ) Voltage (V) 45 40 35 30 25 20 5 0 5 0 0 0.002 0.004 0.006 0.008 0.00 Time (sec) Fig. 0: Compariso of coverter voltage Sigle model Multi model Proposed model Table 2: Duty cycle ad gai Output gai of differet model Duty cycle ---------------------------------------------------------------- i (%) Sigle model Multi model H-bridge model 0. 0.0 0.20 0.25 0.2 2.0.50 2.50 0.3 3.4 3.20 5.40 0.4 5.5 5.30 9.50 0.5 8.5 8.40 25.0 0.6 24.0 23.00 33.50 0.7 30.0 30.50 4.00 0.8 46.0 46.05 56.05 0.9 90.0 9.50 95.50 Fig. a ad b. The theoretical periodic sigal with symmetric property of iductor curret, capacitor curret, diode curret, load voltage ad IGBT Switchig Voltage of DC-DC coverter is aalyzed at the steady state poits which are illustrated i Fig. 6. The coverter output voltage is obtaied at the simulatio time 0.0 sec. Whe cosider the settlig time ad the steady state of Fig. 0, the output voltage stability of proposed coverter is ehaced ad the time to reach the stability level of proposed coverter is less whe compared to multi-level ad sigle level topologies. Therefore, the traditioal coverters eed stabilizig cotroller to maitai the stability ad desig of stabilizig cotroller is difficult. The iductor curret (I ), capacitor curret (I C ), load voltage (V ce ), diode curret (I d ) ad IGBT switchig voltage (V R ) of the proposed topology is aalyzed. Whe the switch is tur o, two iput iductor is chargig i parallel which is show as i the iductor curret characteristics. Therefore, the iput curret equal to 2.5 A ad whe IGBT tur off the iput iductor coect i series that described as show i Fig. 4b. Because of that, the iput curret of the circuit is decreased to half of the actual value. So, the voltage stress is reduced by the proposed topology whe compared to other topologies due to the iclusio of switch iductor. The voltage stress o a switch is 54
Gai 00 90 80 70 60 50 40 30 20 Sigle model Multi model Proposed model 0 0. 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Duty cycle (a) (b) Fig. : Compariso Performace of (a) Voltage gai ad duty cycle ad (b) Deviatio of switched iductor model Fig. 2: Performace of load voltage uder trasiet aalysis equal to 96.7 volt ad the output is equal to 230 volt. I additio to that, the voltage stress o a switch i switched iductor boost coverter is 230 volt. I Fig. 0, the coversio output oscillatio of switched iductor based topology is reduced whe compared to other two topologies. The compariso shows that, the proposed topology is achieved high DC voltage gai (230V/30V) which is proved by the proposed topology. Figure a, the proposed H-bridge switched iductor topology is providig better gai whe compared with other topologies. I the study, the PWM modulatig frequecy is selected as0khz to aalyze the performace of all topologies. Uder this switchig frequecy, the oscillatio of coverter output is reduced. Whe varyig the modulatig frequecy from khz to 0kHz, the performace of the coverter 55 curret is affected such as, iductor curret, capacitor curret ad diode curret respectively. But, the switched iductor based circuit reduces the effect of switchig frequecy ad improves the coverter curret. I the switched iductor circuit, the diodes make sure the iductor ad the capacitor are charged i parallel ad discharged i series. The reaso for improvig the gai, the switchig frequecy effect of the coverter is reduced by switched iductor which improved the coversio output. From Table 2, the coversio of the switched iductor based model how much deviated from the multilevel ad sigle level model is aalyzed. The aalyzed coversio deviatio is plotted i bar chart. The performace of deviatio shows i Fig. b, the proposed switched iductor based model better tha compared to sigle level ad multilevel model.
The, the trasiet respose of the proposed model is aalyzed by chagig the load value from the actual value. Uder this chagig coditio, actual load value is reduced as 50% from 600 sec to 200 sec ad the load voltage performace is give i Fig. 2. The performace shows that, the proposed model have good settlig respose ad reached the stead state level with less overshoot after 200 sec. CONCUSION The proposed cascade multilevel DC to DC boost coverter topology with H-bridge switched iductor was implemeted i MATAB workig platform. The, the coversio performace of proposed topology was aalyzed at differet gai ad duty cycle level. Five level series cascadig circuit was used to aalyze the performace of proposed topology. The coversio performace of proposed topology was compared with sigle level ad multilevel DC-DC coverter topologies. The mode of operatio of switched iductor with cascade model was aalyzed durig switch ON ad OFF coditio. From the duty cycle ad gai compariso, the voltage coversio of proposed topology is aalyzed ad compared with traditio topologies. The compariso result shows that, the proposed topology was better for DC to DC for boostig purpose without usig ay drivig circuit. The switchig frequecy effect of the coverter is reduced by the switched iductor circuit ad so the coversio gai of the circuit is improved. Also, the stability of the coverter is icreased ad the switchig stress is reduced. I additio, the proposed model has good respose ad reached steady state uder trasiet aalysis. REFERENCES Res. J. App. Sci. Eg. Techol., 9(3): 45-57, 205 Axelrod, B., Y. Berkovich ad A. Ioiovici, 2008. Switched-capacitor/switched-iductor structures for gettig trasformer less hybrid DC-DC PWM coverters. IEEE T. Circuits-I, 55(2): 687-696. Cecati, C., F. Ciacetta ad P. Siao, 200. A multilevel iverter for photovoltaic systems with fuzzy logic cotrol. IEEE T. Id. Electro., 57(2): 45-425. Che, S.Y., 203. Block diagrams ad trasfer fuctios of cotrol-to-output ad lie-to-output for peak curret-mode cotrolled boost coverters. IET Power Electro., 6(): 60-66. Deivasudari, P.S., G. Uma ad R. Poovizhi, 203. Aalysis ad experimetal verificatio of Hopf bifurcatio i a solar photovoltaic powered hysteresis curret-cotrolled cascaded-boost coverter. IET Power Electro., 6(4): 763-773. Hwu, K.I. ad Y.T. Yau, 2009. Two types of KY buckboost coverters. IEEE T. Id. Electro., 56(8): 2970-2980. 56 Hwu, K.I. ad Y.T. Yau, 200. Voltage-boostig coverter based o charge pump ad couplig iductor with passive voltage clampig. IEEE T. Id. Electro., 57(5): 79-727. Jiao, Y. ad F.. uo, 20. N-switched-capacitor buck coverter: Topologies ad aalysis. IET Power Electro., 4(3): 332-34. Karugaba, S., O. Ojo ad M. Omoigui, 2008. Switchig fuctio based modelig of flyig capacitor DC- DC coverters. Proceedig of IEEE Power Electroics Specialists Coferece (PESC, 2008), pp: 225-222. Kouro, S. ad B. Wu, 2009. Cotrol of a cascaded H- bridge multilevel coverter for grid coectio of photovoltaic systems. Proceedig of 35th Aual Coferece of IEEE Idustrial Electroics (IECON '09), pp: 3976-3982. ai, J.S. ad F.Z. Peg, 996. Multilevel coverters-a ew breed of power coverters. IEEE T. Id. Appl., 32(3): 509-57. eyva-ramos, J.., M.G. opez,.h. Saldiera ad M.M. Cruz, 20a. Average curret cotrolled switchig regulators with cascade boost coverters. IET Power Electro., 4(): -0. eyva-ramos, J.., J.A. Saldaa,.H. Saldiera ad M.G. opez, 20b. Processig eergy from fuel cell modules usig cascade coverters. Proceedig of IET Coferece o Reewable Power Geeratio (RPG, 20), pp: -5. iu, C., P. Su, J.S. ai, Y. Ji, M. Wag, C.. Che ad G. Cai, 202. Cascade dual-boost/buck activefrot-ed coverter for itelliget uiversal trasformer. IEEE T. Id. Electro., 59(2): 467-4680. iu, S.,. Zhou ad W. u, 203. Simple aalytical approach to predict large-sigal stability regio of a closed-loop boost DC DC coverter. IET Power Electro., 6(3): 488-494. opez, M.G., J.. Ramos, E.E. Gutierrez ad J.A. Saldaa, 2008. Modellig ad aalysis of switchmode cascade coverters with a sigle active switch. IET Power Electro., (4): 478-487. Mayo-Maldoado, J.C., J.C. Rosas-Caro ad A. Gozalez-Rodriguez, 200a. State space modelig ad cotrol of the DC-DC multilevel boost coverter. Proceedig of 20th Iteratioal Coferece o Electroics, Commuicatios ad Computer (CONIEECOMP), pp: 232-236. Mayo-Maldoado, J.C., R.S. Cabrera, H. Ciseros- Villegas ad M. Gomez-Garcia, 200b. Modelig ad cotrol of a DC-DC multilevel boost coverter. Proceedig of the World Cogress o Egieerig ad Computer Sciece (WCECS, 200). Sa Fracisco, USA. Mayo-Maldoado, J.C., R.S. Cabrera, J.D. Morales, E.N. Cabrera, R. Castillo-Gutierrez, J.E. Martiez- Beral ad D. Soto-Moterrubio, 20a. O the output curret estimatio of a DC-DC multiplier coverter. Proceedigs of the World Cogress o Egieerig ad Computer Sciece, Vol..
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