March 1, 2005 Texas Instruments THS7530PWP Gain Amplifier Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Device Summary 1.5 Major Findings 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process 3.1 General 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Thin Film Resistors 3.7 Fuses 3.8 Polysilicon Resistors 3.9 Polysilicon Capacitors 3.10 NPN Bipolar Transistors 3.11 PNP Bipolar Transistors 3.12 Isolation and Substrate 3.13 References 4 Materials Analysis 4.1 SIMS Analysis 4.2 FESEM-EDS Materials Analysis 4.3 TEM-EDS Analysis of Transistor Metals 5 Critical Dimensions 5.1 Horizontal Dimensions 5.2 Vertical Dimensions
Structural Analysis 6 References Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Pin Layout 2.1.2 Top Package Photograph 2.1.3 Bottom Package Photograph 2.1.4 Package X-Ray Top View 2.1.5 Die Photograph 2.1.6 Die Markings a 2.1.7 Die Photograph at Metal 2 2.1.8 Die Photograph at Metal 1 2.1.9 Die Photograph at Poly 2.1.10 Die Photograph at Substrate 2.2.1 Die Corner a 2.2.2 Die Corner b 2.2.3 Die Corner c 2.2.4 Die Corner d 2.2.5 Bond Pad 2.2.6 Minimum Pitch Bond Pads 3 Process 3.1.1 Die Photograph Showing Location of Cross-Sections and Features Analyzed 3.1.2 General Structure 3.1.3 Die Edge 3.1.4 Die Seal Structure 3.2.1 Plan-View Image of Bond Pad and ESD Structure 3.2.2 Bond Pad and Ball Bond Overview 3.2.3 Inter-Metallic Detail 3.2.4 Bond Pad Left Edge 3.2.5 Bond Pad Right Edge 3.2.6 Plan-View Image of ESD Protection Structure 3.2.7 ESD Protection Structure 3.2.8 ESD Protection Structure Detail 3.3.1 Passivation 3.3.2 IMD 2 3.3.3 IMD 1
Overview 1-2 3.3.4 PMD 3.3.5 PMD, STI, DTI and BOX 3.4.1 Plan-View Image of Minimum Pitch Metal 3 3.4.2 Metal 3 3.4.3 Minimum Pitch Metal 2 3.4.4 Minimum Pitch Metal 1 3.4.5 TEM Image of Metal 1 3.5.1 Minimum Pitch Via 2 s 3.5.2 Minimum Pitch Via 1 s 3.5.3 Minimum Pitch Contacts to Poly 3.5.4 Typical Contacts to Substrate and Poly 3.6.1 Plan-View Image of NiCr Thin Film Resistor 3.6.2 NiCr Thin Film Resistor 3.6.3 NiCr Thin Film Resistor Contact Detail 3.6.4 NiCr Thin Film Resistor Detail 3.7.1 Plan-View Image of Metal 2 Fuse 3.7.2 Metal 2 Fuse 3.8.1 Plan-View Image of Polysilicon Resistors 3.8.2 Polysilicon Resistors 3.8.3 Polysilcion Resistors Detail 3.8.4 Polysilicon Resistor Lengthwise 3.8.5 Polysilicon Resistor Contact 3.8.6 TEM Image of Polysilicon Resistor Contact 3.9.1 Plan-View Image of Poly Capacitors 3.9.2 Poly Capacitors 3.9.3 SCM Image of Poly Capacitor NBL 3.9.4 Poly Capacitor Contact to Poly 3.10.1 Plan-View Image NPN and PNP Transistors (Metal 3) 3.10.2 NPN and PNP Transistor General Structure 3.10.3 Plan-View Image of NPN Transistors (Metal 1) 3.10.4 Plan-View Image of NPN Transistors (Poly) 3.10.5 Plan-View Image of NPN Transistors (Substrate) 3.10.6 NPN Transistor Overview: Emitter Contact 3.10.7 SCM Image of NPN Transistor: Emitter Contact 3.10.8 NPN Transistor: Emitter Contact and Base 3.10.9 NPN Transistor: Emitter Contact and Base Detail 3.10.10 TEM Image of NPN R
Overview 1-3 3.10.11 TEM Image of NPN Transistor: Emitter Contact and Base Detail 3.10.12 TEM Image of Emitter and Extrinsic Base 3.10.13 SCM Image of NPN Transistor: Emitter Contact and Base Detail 3.10.14 NPN Transistor Overview: Base and Collector Contacts 3.10.15 SCM Image of NPN Transistor Overview: Base and Collector Contacts 3.10.16 NPN Transistor: Base and Collector Contacts Detail 3.10.17 NPN Transistor: Base Contact Detail 3.10.18 TEM Image of Collector 3.10.19 TEM Image of Collector Detail 3.10.20 Plan-View Image of NPN Transistor with Four Emitter Stripes (Metal 1) 3.10.21 NPN Transistor with Four Emitters Overview 3.10.22 SCM Image of Multiple-Emitter NPN Transistor with Four Emitters Overview 3.11.1 Plan-View Image of PNP Transistors (Metal 1) 3.11.2 Plan-View Image of PNP Transistors (Poly) 3.11.3 Plan-View Image of PNP Transistors (Substrate) 3.11.4 PNP Transistor: Emitter Contact 3.11.5 PNP Transistor: Base and Collector Contacts 3.11.6 TEM Image of PNP Transistor Overview: Emitter Contact 3.11.7 SCM Image of PNP Transistor 3.11.8 PNP Transistor: Base and Emitter Contact 3.11.9 PNP Transistor: Base and Emitter Contact Detail 3.11.10 TEM Image of PNP Transistor: Base and Emitter Contact 3.11.11 TEM Image of PNP Transistor: Base and Emitter Contact Detail 3.11.12 TEM Image of PNP Transistor: Base and Emitter Detail 3.11.13 TEM Image of PNP Transistor: Extrinsic Base 3.11.14 SCM Image of PNP Transistor: Base and Emitter Contact 3.11.15 PNP Transistor: Base and Collector Contacts Detail 3.11.16 TEM Image of PNP Transistor: Collector Contact 3.11.17 PNP Transistor Base Contact Lengthwise 3.11.18 Plan-View Image of PN Diode 3.11.19 PN Diode 3.12.1 Minimum Width STI 3.12.2 DTI and BOX 3.12.3 TEM Image of DTI and BOX
Overview 1-4 4 Materials Analysis 4.1.1 Cross-Section Through Dielectrics 4.1.2 SIMS Profile of the Dielectric Layers 4.2.1 FESEM-EDS Spectrum of Ball Bond 4.2.2 FESEM-EDS Spectrum of NiCr Thin Film Resistor 4.2.3 FESEM-EDS Spectrum of NiCr Contact Pad 4.2.4 FESEM-EDS Spectrum of Metal 1 4.2.5 FESEM-EDS Spectrum for Metal 1 Cap 4.2.6 FESEM-EDS Spectrum for Metal 1 Barrier 4.2.7 FESEM-EDS Spectrum for a Tungsten Contact 4.2.8 FESEM-EDS Spectrum of NPN SiGe Base 4.2.9 FESEM-EDS Spectrum of PNP SiGe Base 4.3.1 TEM-EDS Spectrum of Emitter Window Nitride 4.3.2 TEM-EDS Spectrum of Base Silicide 4.3.3 TEM-EDS Spectrum of NPN Base (Emitter vs Collector Side) 4.3.4 TEM-EDS Spectrum of PNP Base 5 Critical Dimensions 6 References Report Evaluation 1.2 List of Tables 2.1.1 Pin Assignments 2.2.1 Package and Die Dimensions 3.3.1 Dielectric Composition and Vertical Dimensions 3.4.1 Metallization Vertical Dimensions 3.4.2 Minimum Metallization Horizontal Dimensions 3.5.1 Minimum Via and Contact Horizontal Dimensions 3.8.1 Minimum Polysilicon Vertical Dimensions 3.10.1 NPN Transistor Vertical Dimensions 3.11.1 PNP Transistor Vertical Dimensions 3.12.1 Isolation Horizontal Dimensions 4.1.1 Summary Dielectric Composition from SIMS and FESEMS R
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