RADIO FREQUENCY (RF) COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) ULTRA WIDEBAND (UWB) TRANSMITTER AND RECEIVER FRONT-END DESIGN.

RADIO FREQUENCY (RF) COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) ULTRA WIDEBAND (UWB) TRANSMITTER AND RECEIVER FRONT-END DESIGN A Dissertation by MENG MIAO Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY May 008 Major Subject: Electrical Engineering

RADIO FREQUENCY (RF) COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) ULTRA WIDEBAND (UWB) TRANSMITTER AND RECEIVER FRONT-END DESIGN A Dissertation by MENG MIAO Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Approved by: Chair of Committee, Committee Members, Head of Department, Cam Nguyen Steven Wright Laszlo Kish Reza Langari Costas Georghiades May 008 Major Subject: Electrical Engineering

iii ABSTRACT Radio Frequency (RF) Complementary Metal-Oxide Semiconductor (CMOS) Ultra Wideband (UWB) Transmitter and Receiver Front-end Design. (May 008) Meng Miao, B.S., Nanjing University, People s Republic of China; M.S., Nanjing Research Center of Electronics Engineering, People s Republic of China; M. Eng., National University of Singapore Chair of Advisory Committee: Dr. Cam Nguyen The low-cost low-power complementary metal-oxide semiconductor (CMOS) ultra wideband (UWB) transmitter and receiver front-ends based on impulse technology were developed. The CMOS UWB pulse generator with frequency-band tuning capability was developed, which can generate both impulse and monocycle pulse signals with variable pulse durations. The pulse generator integrates a tuning delay circuit, a square-wave generator, an impulse-forming circuit, and a pulse-shaping circuit in a single chip. When integrated with the binary phase shift keying (BPSK) modulator, the transmitter front-end can generate a positive impulse with 0.8 V, negative impulse with 0.7 V, as well as the positive/negative monocycle pulse with 0.6 0.8 V, all with tunable pulse durations. The UWB receiver front-end including the template pulse generator, low noise amplifier (LNA), and multiplier was developed. The cascoded common-source inductively degenerated LNA, with extended ultra-wideband ladder matching network, as well as shunt-peaking topology, was selected to form the impulse-type UWB LNA. The structure-optimized and patterned ground shield (PGS) inductors were also studied and used in LNA design to improve the LNA performance. The maximum gain of 1.4 db was achieved over the band. For the 3-dB bandwidth,.6 9.8 GHz was achieved. The average noise figure of 5.8 db was achieved over the entire UWB band of 3.1-10.6 GHz. The UWB multiplier based on the transconductor multiplier structure was

iv investigated, with the shunt-peaking topology applied to achieve the pole-zero cancellation and extend the multiplier bandwidth from GHz to 10 GHz. A low-cost, compact, easy-to-manufacture coplanar UWB antenna was developed that is omni-directional, radiation-efficient and has a stable UWB response. It covers the entire UWB frequency range of 3.1 10.6 GHz, with the return loss better than 18-dB. This novel uniplanar antenna was integrated with the developed CMOS tunable pulse generator to form the UWB transmitter front-end module. This UWB module can transmit the monocycle pulses and the signals having shape similar to the first derivative of the monocycle pulses, all with the tunable pulse durations. The proposed UWB front-ends have the potential application in short-range communication, GPR, and short-range detections.

To my family v

vi ACKNOWLEDGEMENTS I would like to express my deepest gratitude to my advisor, Dr. Cam Nguyen, for his advice, encouragement and support throughout this research. I would also like to thank my committee members, Dr. Steven Wright, Dr. Laszlo Kish, and Dr. Reza Langari for their valuable time and advice. I am also grateful to my wife, Qingmei Lu, daughters, Hannah and Cathy, and to my parents and relatives for their encouragement and support over these years. This research was supported in part by the National Science Foundation, in part by the Texas Advanced Research Technology Program, and in part by Dell Computer.

vii TABLE OF CONTENTS CHAPTER Page I INTRODUCTION... 1 II FUNDAMENTALS OF UWB SYSTEMS... 5.1 UWB Basics... 5.1.1 UWB Definitions... 5.1. UWB Advantages... 7.1.3 UWB Applications... 8. UWB Pulse Signals... 10..1 Gaussian Impulse... 11.. Gaussian Monocycle Pulse... 11..3 Gaussian Doublet Pulse... 13.3 Basic Modulation Topologies... 14.3.1 PPM... 15.3. PAM... 16.3.3 OOK... 16.3.4 BPSK... 16.4 Impulse-type UWB Structures... 17.4.1 UWB Transmitter... 18.4. UWB Receiver... 0.5 UWB Antennas... 3.5.1 Introduction... 3.5. Antenna Types... 3.5.3 Simulation Tools... 5.5.4 Measurement Techniques... 6 III UWB TRANSMITTER DESIGN... 8 3.1 Basic Components Overview... 30 3.1.1 CMOS Inverter Basics... 30 3.1. Inverter Switching Characteristics... 33 3.1.3 Two-input NOR/NAND Gate Blocks... 36 3.1.4 Tunable Delay Cell... 37 3. Tunable Pulse Generator Design... 39 3..1 Tuning Delay Component... 39 3.. Square Wave Generator... 41 3..3 Impulse-forming Block... 44 3..4 Pulse-shaping Circuit... 45

viii CHAPTER Page 3..5 Tunable Pulse Illustration... 46 3..6 Simulation and Measurement Results... 47 3.3 BPSK Modulator Design... 59 3.4 Tunable Transmitter Design... 63 IV UWB RECEIVER DESIGN... 70 4.1 UWB LNA... 71 4.1.1 LNA Design... 71 4.1. Inductor Optimization... 88 4.1.3 LNA Fabrication and Test... 93 4. UWB Correlator Design... 99 4..1 DC Analysis... 101 4.. AC Analysis... 104 4..3 Fabrication and Results... 106 4.3 Receiver Front-end... 110 V UWB UNIPLANAR ANTENNA... 11 5.1 Uniplanar Antenna Design... 113 5. Antenna Fabrication and Test... 1 5.3 UWB Transmitter Module... 16 VI CONCLUSIONS... 130 REFERENCES... 133 VITA... 140

ix LIST OF FIGURES FIGURE Page.1 Indoor UWB Systems Spectrum Mask... 5. Power Levels of UWB Signal and a Typical Narrowband (NB) Signal... 6.3 Gaussian Impulse and Frequency Spectrum... 10.4 Gaussian Monocycle Pulse and Frequency Spectrum... 1.5 Gaussian Doublet Pulse and Frequency Spectrum... 13.6 Pulse Position Modulation... 15.7 Pulse Amplitude Modulation... 15.8 On-off Keying... 16.9 Bi-phase Shift Keying... 17.10 Transmitter Top Level Schematic... 18.11 Receiver Top Level Schematic... 1 3.1 CMOS Inverter Circuit and Its Symbol... 30 3. CMOS Inverter Delay-time Definitions... 34 3.3 CMOS NOR Gate Block and Its Symbol... 36 3.4 CMOS NAND Gate Block and Its Symbol... 37 3.5 Shunt-capacitor Delay Element... 38 3.6 Block Diagram of CMOS UWB Tunable Monocycle Pulse Generator Chip... 39 3.7 Circuit Schematics of Tunable Delay Cell (a) and Reference Cell (b)... 40 3.8 Cascade of Inverters Used to Drive a Large Load Capacitance... 4

x FIGURE Page 3.9 Illustration of Signal Shapes at Each Node of Tunable Pulse Generator Shown in Fig. 3.6... 46 3.10 Photograph of the 0.18-µm CMOS Tunable Monocycle Pulse Generator Chip Including Pads for On-wafer Probe Measurement... 48 3.11 Output Signal of Square Wave Generator... 49 3.1 Rising and Falling Edges of Tunable Square Wave Signal... 50 3.13 Transfer Function of Designed Pulse Shaping Circuit... 51 3.14 Pulse-shaping Circuit Performance for Impulse Input... 5 3.15 Measured and Simulated Impulse Signals with Tunable Pulse Duration... 53 3.16 PSD of Tunable Impulse Signal (a) 100 ps. (b) 300 ps... 55 3.17 Measured Impulse Width vs. Tuning Delay Voltage... 56 3.18 Measured Negative Impulse Signals with Tunable Pulse Duration (NAND Gate Block)... 57 3.19 Tunable Monocycle Pulse Generator... 58 3.0 Spectrum of Tunable Monocycle Pulse Signal... 59 3.1 BPSK Diagram Block... 60 3. BPSK Modulation Circuit... 61 3.3 Simulated Insertion Loss and Isolation of BPSK Modulator... 6 3.4 Simulated Time-domain Performance of BPSK Modulator... 63 3.5 Diagram Block of Tunable Impulse Generator with BPSK Modulator... 64 3.6 Photograph of Impulse Generator with BPSK Modulator... 65 3.7 Measured Results of Impulse Transmitter... 65

xi FIGURE Page 3.8 Monocycle Pulse Generator with BPSK Modulator... 66 3.9 Photograph of Monocycle Pulse Generator with BPSK Modulator... 68 3.30 Measured Results of Monocycle Pulse Transmitter... 68 4.1 Various Wideband LNA Topologies... 7 4. Ladder Matched UWB LNA... 74 4.3 Third-order Chebyshev Bandpass Filter... 76 4.4 Performance of Three-section Chebyshev Bandpass Filter... 77 4.5 Noise Model for Transistor M 1... 80 4.6 Source-follower Buffer for UWB LNA... 87 4.7 Inductor π-model... 89 4.8 Layout of Patterned Ground Shield Inductor... 91 4.9 Performance of the Patterned Ground Shield Inductor L 1... 9 4.10 Photograph of LNA Chip... 93 4.11 Return Loss of Input Port for LNA... 94 4.1 Return Loss of Output Port for LNA... 94 4.13 Reverse Isolation of LNA... 95 4.14 Power Gain of LNA with Buffer... 96 4.15 Phase Performance of S 1 for LNA... 97 4.16 Measured LNA Performance in Time-domain... 97 4.17 Noise Performance for LNA... 98 4.18 Correlator in UWB Receiver... 99

xii FIGURE Page 4.19 Schematic of the Proposed Multiplier... 10 4.0 Simplified Small-signal Equivalent Circuit... 105 4.1 Frequency Response for Dominant Pole... 107 4. Frequency Response for Shunt-peaking Inductor Effect... 108 4.3 Photograph of the Fabricated Multiplier... 108 4.4 Conversion Gain and RF Return Loss with the IF Frequency 10 MHz, LO Power is -1 dbm, and RF Power is -0 dbm... 109 4.5 Block Diagram of the Receiver Front-end... 110 4.6 Transient Simulation of the Receiver Front-end... 111 4.7 Layout of the Proposed Receiver Front-end... 111 5.1 Basic Structure of the Uniplanar Antenna... 114 5. Simulated Return Loss of the Designed Uniplanar Antenna... 119 5.3 Simulate Input Reflection of the Designed Antenna in Time-domain... 10 5.4 Simulated Amplitude of Transfer Function... 10 5.5 Simulated Phase of Transfer Function... 11 5.6 Simulated Antenna Patterns... 1 5.7 Photograph of the Developed UWB Antenna along with 50-Ω CPW Feed Line and SMA Connector (on the Left)... 13 5.8 Measured and Simulated Return Loss of Uniplanar UWB Antenna... 14 5.9 Measured and Calculated TDR Responses of Uniplanar UWB Antenna... 15 5.10 Photograph of the Fabricated UWB Transmitter Module... 16

xiii FIGURE Page 5.11 Test Setup for Pulse Transmission Measurement of UWB Transmitter Module... 17 5.1 Measured Received Signals of the Impulses Transmitted by UWB Transmitter Module for Different Control Voltages... 18 5.13 Measured Received Signals of the Monocycle Pulses Transmitted by UWB Transmitter Module for Different Control Voltages... 18

xiv LIST OF TABLES TABLE Page 3.1 The Size of Inverters in Square Wave Generator... 49 3. The Size of NOR Gate Block... 53 3.3 The Size of NAND Gate Block... 57 3.4 The Size of Transistors in BPSK Modulator... 6 4.1 Component Values of Third-order Chebyshev BPF... 77 4. Final Component Values of LNA... 87 5.1 Parameters of 50-Ω Quasi-CPW Feed Line... 116 5. Dimensions of Uniplanar Antenna... 118

1 CHAPTER I INTRODUCTION In the past decades, ultra-wideband (UWB) was mainly used for military communications, radar, and sensing applications. With the approval of Federal Communications Commission (FCC) in February 00, UWB technology pushes the limits of high data-rate, and has been proposed for high-rate, short-range communications [1], such as home networks, in-building communications, and cordless phones. Contrary to the traditional narrowband, sinusoidal wave radio signals, an UWB signal is typically composed of a pulse train of sub-nanosecond pulses modulated either in polarity or in position. The narrowness of the pulses in time corresponds to a wide bandwidth in the frequency domain. Since the total power is spread over such a wide range of frequencies, its power spectral density is extremely low. This effectively produces extremely small or no interference to other existing radio signals while maintains excellent immunity to interference from these signals []-[3]. UWB technology can also be used to achieve other wireless applications, such as through-wall and medical imaging systems, radars, ground penetrating radars (GPRs), and military applications with relatively high emission power levels. The signals of UWB systems can provide all the above applications with penetration and target tracking feasibility that narrow-band signals may not. Currently, two different topologies are widely considered for UWB systems. One is the orthogonal frequency division multiplexing (OFDM) based multi-band UWB, in which the frequency band is divided into tens of hundred-mhz bands; the other is the impulse-based single/dual band system. In multi-band OFDM UWB scheme, data is transmitted using OFDM on different bands in a time-interleaved fashion. Each band has This dissertation follows the style of IEEE Transactions on Microwave Theory and Techniques.

a minimum bandwidth of 500 MHz and frequency hopping is employed to cover a wide bandwidth. Since the device can dynamically select which bands to use for transmission, multi-band OFDM UWB has the advantages of inherent robustness to multi-path, excellent robustness to narrowband interference, ability to comply with worldwide regulations. Compare with multi-band UWB approach, where the up-converter is needed to generate the modulated signal that can transmit effectively, implementing an impulsebased UWB system requires a simpler circuit structure with less power dissipation, no up-conversion circuitry is needed, since UWB signal itself can be used for transmission. Furthermore, an impulse-based UWB system can potentially use a bandwidth of over 7 GHz, reducing the chance of fading in case where the noise exists in a narrow frequency band within the UWB band, resulting in better immunity to destructive channel environments. This is an advantage as compared to the OFDM case, where the noise in a particular frequency channel may disrupt that channel. Additionally, since impulse-based UWB uses very short duration impulse signals, the accuracy of position detection is higher. Based on above facts, the research of this dissertation will focus on the impulsetype UWB technology. The selection of the impulse signal types for the UWB system is one of the fundamental considerations in designing UWB circuits and systems, because the impulse types determine the spectrum characteristics of UWB signals. Many kinds of signals can be used in UWB systems, such as step pulse, Gaussian impulse, monocycle, or multicycle signal with short pulse duration; where the monocycle signal is most often used in impulse-type UWB systems because of its better spectral shape and wider bandwidth characteristic [], [4]-[8]. Several monocycle pulse shapes were introduced in [9], and all of them have wideband spectrums. Among them the Gaussian monocycle pulse has relatively wide 3-dB bandwidth and no DC components, better bit-error-rate (BER) performance, hence fits the FCC emission regulation better than any other pulse, therefore the design of a Gaussian pulse generator is an important work in the whole impulse-type UWB system.

3 Up to now, many existing UWB pulse generators are based on approaches developed for radar applications and involve hybrid circuit techniques [10]-[1]. On the other hand, UWB system prefers radio frequency integrated circuit (RFIC) designs in order to achieve low cost and low power consumption, easy integration with other components, such as digital circuits and planar antennas. Though some expensive IC technologies such as Silicon-Germanium (SiGe) or Gallium-Arsenide (GaAs) have been used to realize transceiver, Complementary-Metal-Oxide-Semiconductor (CMOS) technology is more desirable for a single-chip, low-cost solutions. However, some inherent characteristics of CMOS technology, such as low breakdown voltage, poor passive components, lack of accurate RF models etc, limit the CMOS RFIC applications on such high frequencies and such a wide bandwidth, and make it a challenging work. Fortunately, with the rapid development of current technology scaling and advances of more accurate RF models, CMOS is quickly becoming the preferred choice for RFIC s. In order to use standard CMOS technology to generate sub-nanosecond pulses, new type of integrated-circuit pulse generator, different from the traditional hybrid circuits, should be employed based on CMOS process to produce Gaussian pulse with sub-nanosecond pulse width. Similar research work is also applied to other important RF blocks such as low noise amplifier (LNA) and mixer (correlator) in UWB systems. Since UWB signals cover a relatively wide frequency band, the power density can be extremely low, which avoids causing interference to users at the same frequency. The fractional bandwidth of UWB signal normally exceeds 5%, which brings great challenge on the UWB antenna design. Transmitting and receiving of UWB signal not only requires the antenna to be able to radiate the energy over a wide frequency band but also requires a linear phase response over the band to avoid signal distortion [13]. This necessitates an antenna with a fixed phase center for different frequencies in the band. However, many of existing wideband antennas such as tapered slot antennas and log periodical antennas are not suitable for UWB communication because they have floated phase centers for different frequencies. Currently, a few high-quality non-dispersive UWB antennas are commercially available [14]. However, the large size of these

4 antennas makes them less suitable for most commercial applications and not feasible for portable or handheld uses. Therefore, there is great need for a low-cost, compact, easyto-manufacture coplanar UWB antenna that is omni-directional, radiation-efficient and has a stable UWB response. This type of antenna can be easily integrated with UWB CMOS RFIC chips. In this dissertation, novel low-cost low-power CMOS RFIC front-ends of transmitter and receiver based on impulse-type UWB technology are presented, and they are further integrated with the developed compact UWB coplanar antennas. With the help of pulse tuning capability, the transmitter can generate both impulse and monocycle pulse signals with variable pulse durations. This system has the potential application in short-range communication, GPR, and short-range detections. Chapter II begins with an overview of the UWB radio architecture; also, the fundamentals of UWB signal, UWB modulation topology, and UWB antenna type are introduced. In chapter III, the design and implementation of impulse-type UWB CMOS RFIC front-end module of the transmitter with tunable pulse duration, integrated with Bi-Phase Shift-Keying (BPSK) modulator, is presented. Chapter IV describes the design of the impulse-type UWB CMOS RFIC front-end of the receiver. The design of a novel compact UWB uniplanar antenna is presented in chapter V. Chapter VI includes the suggestion to improve the system for future research.

5 CHAPTER II FUNDAMENTALS OF UWB SYSTEMS In this chapter, a review of the basic concepts of UWB systems is presented, with particular emphasis on impulse radio (IR) techniques. The types of UWB pulse signal, commonly used modulation topologies, and typical UWB antennas are also described..1 UWB Basics.1.1 UWB Definitions Fig..1. Indoor UWB systems spectrum mask. The FCC has defined UWB signals as that, over 3.1GHz to 10.6 GHz band, 10- db bandwidth of the signal occupies an absolute bandwidth greater than 500 MHz or a fractional bandwidth greater than 0.0. However, one of the important conditions is that the power levels of the UWB signal in this spectrum must be low enough to avoid

6 interference with the already existing technologies. The FCC specifies the power emission levels suitable for co-existing with other technologies in the UWB allocated band. The spectrum mask for in-door applications is shown in Fig..1, where part 15 limit is the maximum allowed power spectral density of unintentional radiators, which is -41.3 dbm/mhz. Here the fractional bandwidth is the bandwidth expressed as a fraction of the center frequency. Assume f H is the highest frequency limit and f L is the lowest frequency limit of the 10-dB bandwidth, the fractional bandwidth of the UWB signal is defined as Fractional Bandwidth = ( f f ) f H H + f L L 0% (.1) NB Power Spectral Density UWB 10-dB Bandwidth f L f c f H Frequency (Hz) Fig... Power levels of UWB signal and a typical narrowband (NB) signal.

7.1. UWB Advantages For impulse-type UWB technology, the impulse radio communication systems and impulse radars both utilize extremely short duration pulses, normally in the order of subnanoseconds, instead of continuous waves to transmit information. The pulse directly generates a very wide instantaneous bandwidth signal, and the duty cycle of the pulses can be as low as 1%. Therefore the pulse spreads the energy over a wide frequency band, which is shown in Fig... Compare with narrow-band signal, the UWB signal is noise like which makes interception and detection quite difficult. Due to the low-power spectral density, UWB signals cause very little interference with existing narrow-band radio systems. Compare with conventional narrow-band systems, impulse-type UWB systems have many advantages. 1. Low complexity and low cost: Unlike traditional narrow-band radio systems, the impulse-type UWB system produces a very narrow timedomain pulse, which is equivalent to a carrier-less baseband signal and is able to propagate without further mixing with carrier signal. Hence the additional up-conversion and amplification circuit is not needed. This means the omission of local oscillator, the associated complex delay and phase tracking loops. Therefore, the impulse-type UWB systems can be implemented in low cost, low power, integrated circuit process, such as CMOS technology.. Low probability of interception: As shown in Fig.., the UWB signal has much broader bandwidth, therefore much lower energy density than that of the conventional narrow-band radio systems. For the UWB signal, the extreme low energy density over the ultra-wide frequency range appears as the noise to most other wireless devices, which makes unintended detection quite difficult and results in low probability of interception/detection. This characteristic makes UWB a good choice for secure and military applications.

8 3. Excellent immunity to interference from other existing radio signals: Because the pulse signal is very narrow in time-domain, the transmission duration of UWB pulse is shorter than a nanosecond in most cases, the reflected pulse has an extremely short window of opportunity to collide with the line of sight (LOS) pulse and cause signal degradation, hence very high multi-path resolution is achieved. Since UWB spectrum covers a vast range of frequencies from near DC to several gigahertz and offers high processing gain for UWB signals, the frequency diversity caused by high processing gain makes UWB signals relatively resistant to intentional and unintentional jamming, because no jammer can jam every frequency in UWB spectrum at once. Even if some of the frequencies are jammed, there is still a large range of frequencies that remains untouched. This makes the impulse-type UWB signal resistant to severe multi-path propagation and jamming/interference. Therefore the impulse-type UWB systems offer excellent immunity to interference from other existing radio signals. 4. Good time-domain resolution for location and tracking applications: The very narrow time-domain pulses make the UWB radios able to offer timing precision much better than global positioning system (GPS) and other radio systems. Along with good substrate penetration characteristics, the impulse-type UWB systems offer opportunities for short-range radar applications such as rescue and anti-crime operations, as well as in surveying and in the mining industry such as GPR. The inherent advantages of the impulse-type UWB systems offer the good time-domain resolution for location and tracking applications..1.3 UWB Applications The wide spectrum of UWB system provides a wireless channel with high spatial capacities, according to well-known Shannon s channel capacity theorem

9 ( SNR) C = B log 1+ (.) where C is the channel capacity in bits/second, B is the bandwidth in Hertz, and SNR is the Signal-to-Noise ratio. (.) shows that the channel capacity is in linear relation with bandwidth and logarithmic relation with SNR. Because of its inherent ultra wideband property, the UWB system can achieve high data rates while operating below the noise floor. The inherent high data rates and low power as well as attractive features like excellent multipath immunity and good immunity to external interference make the UWB technology a good candidate in vast applications. Some of the potential application areas of the UWB technology are listed below. 1. Communications: The major commercial UWB application is for communication, since it has very high data transfer rate for short distance. UWB transceivers can send and receive high-speed data with very low power at relatively low cost. UWB communication systems are often advantageous in short-range wireless market. Currently, UWB technologies are primarily targeting at indoor applications of short-range at bit rates up to hundred of megabits per second, such as home networking, high speed wireless local area networks (LAN), and personal area networks (PAN) communications.. Radars: Due to its precise time resolution, UWB technique may also be used for both indoor and outdoor 3-D positioning. This makes the impulse-type UWB GPR useful equipment for detecting internal structure under the ground. Another important application is imaging like microwave remote sensing, in which UWB signals pass through the doors and walls and hence can detect the objects inside the building. 3. Location finding: The good performance of UWB devices in multi-path channels can provide accurate location capability for indoor and environments where GPS receivers cannot work. One such application is

10 radio frequency identification (RFID). The major use of RFID is the tracking device, which can be attached to the objects in the office, lab, warehouse, etc, for locating or tracking inventory. Another application is employee identification cards, which can be used to access the offices. Because of the low power required and relatively low data rate, these devices can be made to have a long lifetime on a single battery at a relatively low cost.. UWB Pulse Signals Since the impulse-type UWB system employs the very short pulses, pulse generation and pulse shaping are among the most fundamental problems in the design of UWB systems. Currently, three types of UWB pulses have often been used in the impulse-type UWB systems, i.e., Gaussian impulse, Gaussian monocycle pulse, and Gaussian doublet pulse. 1 1 Voltage Amplitude (V) 0.5 0-0.5 Normalized Amplitude 0.8 0.6 0.4 0. -1-0. -0.1 0 0.1 0. Time (ns) 0 0 4 6 8 10 1 14 16 18 0 Frequency (GHz) Fig..3. Gaussian impulse and frequency spectrum.

11..1 Gaussian Impulse A Gaussian impulse has a shape of Gaussian distribution as shown in Fig..3 and is expressed as a t y( t) = Ae (.3a) where A is the amplitude of the Gaussian impulse, a is the time constant. The power density spectrum of the Gaussian impulse is Y ( ω) ω 4a A = e (.3b) a The corresponding frequency with peak value of power density spectrum is f = 0 (.3c) c Therefore, the 3 db bandwidth can be derived as a Δ f = 0.836 (.3d) π.. Gaussian Monocycle Pulse Gaussian monocycle pulse is the first derivative of the Gaussian impulse signal, which is shown in Fig..4. Its general formula is shown as follows y( t) a t = a Ate (.4a)

1 where A is the amplitude of the Gaussian monocycle pulse, a is the time constant. The power density spectrum of the Gaussian monocycle pulse is Y ( ω) ω 4a iaω = e (.4b) a The corresponding frequency with peak value of power density spectrum is a f c = (.4c) π And the 3 db bandwidth can be derived as a Δ f = 1.155 (.4d) π 1 1 Voltage Amplitude (V) 0.5 0-0.5 Normalized Amplitude 0.8 0.6 0.4 0. -1-0. -0.1 0 0.1 0. Time (ns) 0 0 4 6 8 10 1 14 16 18 0 Frequency (GHz) Fig..4. Gaussian monocycle pulse and frequency spectrum.

13 1 1 Voltage Amplitude (V) 0.5 0-0.5 Normalized Amplitude 0.8 0.6 0.4 0. -1-0. -0.1 0 0.1 0. Time (ns) 0 0 4 6 8 10 1 14 16 18 0 Frequency (GHz) Fig..5. Gaussian doublet pulse and frequency spectrum...3 Gaussian Doublet Pulse Gaussian doublet pulse is the second derivative of the Gaussian impulse signal, which is shown in Fig..5. Its general formula is shown as follows y( t) = a Ae a t ( 1 a t ) (.5a) where A is the amplitude of the Gaussian doublet pulse, a is the time constant. The power density spectrum of the Gaussian doublet pulse is Y ( ω) ω Aω 4a = e (.5b) a The corresponding frequency with peak value of power density spectrum is a f c = (.5c) π And the 3 db bandwidth can be derived as

14 a Δ f = 1.155 (.5d) π The waveforms of above three pulse signal show that Gaussian impulse has no zero crossing point, Gaussian monocycle pulse has one zero crossing, and Gaussian doublet pulse has two zero crossings. The power density spectra of the three pulse signals are also compared. According to (.3c), for Gaussian impulse, majority frequency components of power density spectrum are low-frequency ones and close to DC, which brings the greater challenge to the transmission antenna of UWB system. For the Gaussian monocycle pulse and Gaussian doublet pulse, the 3dB bandwidths are same, and there are no major low-frequency components, which makes the signal transmission through the antenna much easier..3 Basic Modulation Topologies There are several of modulation techniques that can be used to create modulated UWB signals, and these topologies modulate information bits directly into very short pulses [15]. Since there is no intermediate frequency (IF) processing in such systems, they are often called base-band or impulse radio systems. For impulse-type systems, the typical UWB modulations can be divided into mono-phase techniques and bi-phase techniques. The three most popular mono-phase UWB approaches are pulse position modulation (PPM), pulse amplitude modulation (PAM), and on-off keying (OOK). In these techniques, data signal 1 is differentiated from 0 either by the size of the signal or when it arrives in time but all the pulses generated have the same shape. For the more efficient bi-phase case, bi-phase shift keying (BPSK) is one of the most popular topologies. This modulation transmits a single bit of data with each pulse; with positive pulse representing 1, and negative pulse representing 0. Following will give brief description for each of these modulation topologies.

15 1 0 0 1 Fig..6. Pulse position modulation..3.1 PPM PPM is one of the common modulation technologies used in impulse-type UWB systems. In this technique, both pulses (indicating digital data bit 1 or 0 ) have the same amplitude, and the system transmits the same pulse in one of two positions in the time domain in order to represent a 0 or 1. This method may require a more complex receiver in order to determine the precise position of the received pulse. An example of PPM is shown in Fig..6, where the position of the pulses representing 1 leads that of the pulses representing 0. 1 0 1 0 Fig..7. Pulse amplitude modulation.

16.3. PAM PAM works by separating the tall and the short pulse waves. The amplitude of the pulse is varied according to the different digital data information, where largeamplitude pulse represents 1 and small-amplitude pulse for 0. Fig..7 illustrates the PAM technique. 1 0 1 0 Fig..8. On-off keying..3.3 OOK For OOK modulation, the pulse amplitude of information bit 1 is set to the same amplitude of that UWB pulse, which is equivalent to on; while the pulse amplitude of information bit 0 is set to zero, which is equivalent to off. By setting the pulse on and off, binary information bits, 1 and 0, are being sent out. An example of OOK is shown in Fig..8, where 1 is when there is pulse and 0 is when there is no pulse..3.4 BPSK The most common bi-phase approach used in impulse-type UWB systems is BPSK. Bi-phase differentiates 1 with a positive pulse and 0 with a negative pulse. Comparing with PPM, where the series of ultra-wideband circuits are needed to generate very accurate time steps, this approach is simple and only requires two kinds of pulses

17 be generated, and requires less processing at receiver side. BPSK offers several advantages such as power efficiency and smooth spectrum with smaller-amplitude spikes over above-mentioned mono-phase techniques like PPM, OOK, and PAM that have larger amplitude spikes. These spikes are caused by the multi-pulse occurring periodically, the most significant of which is a two times improvement in overall power efficiency than OOK or PPM [15]. This makes the bi-phase UWB approach extremely efficient for high data rate, portable applications. An example of BPSK is shown in Fig..9. 1 0 1 0 Fig..9. Bi-phase shift keying..4 Impulse-type UWB Structures Impulse-type UWB systems have several advantages over conventional narrowband systems and multi-band OFDM systems. First is its relatively simple structure, because some complicated components such as up-converter related frequency synthesizer and local oscillator used in traditional radio systems are not necessary. This reduces the cost and makes the system compact. In addition, since there is no power consumed on the up-converter circuit like the traditional narrow-band case, impulse-type UWB consumes less power; therefore the life time of battery is much longer. Furthermore, the large bandwidth of impulse signal makes the interception quite difficult for unintended detectors.

18 In this section, the basic architectures of the proposed impulse-type UWB system, which include the front-end modules of UWB transmitter and receiver, are introduced and investigated. In particular, the concentration will focus on the design and implementation of pulse generator, the critical part for both transmitter and receiver, which can generate pulse with narrow duration. For the impulse-type UWB receiver, the research will focus on the LNA and correlator design, which are the central parts of the correlation-based UWB receiver..4.1 UWB Transmitter Compare with continuous-wave transmitters, one of the great advantages of the impulse-type UWB transmitter is that there is no complex RF modules such as the power amplifier (PA) and frequency synthesizer, which contain circuits such as the phaselocked-loop (PLL), voltage-controlled oscillator (VCO) and mixers []-[3]. All these components make the traditional transmitters relatively difficult and expensive to design and implement. In contrast, an impulse-type UWB transmitter costs not that much and moderately easy to design and implement because of its simpler structures. Transmitter Front End Antenna PRF Oscillator Pulse Generator Modulator Data In Fig..10. Transmitter top level schematic.

19 At the block level, the impulse-type transmitter is very simple, and its block diagram is shown in Fig..10. It consists of a pulse generator and a digital-controlled modulator circuit that controls the timing or polarization of the transmitted pulse signal. The local oscillator, either crystal oscillator or custom designed oscillator, determines the pulse repetition frequency (PRF) of the system. The pulse generator can produce the desired waveform, such as impulse, monocycle pulse, etc. The modulator circuit modulates the pulse signal with incoming digital data information using abovementioned BPSK or PPM topology, depending on the timing or polarization modulation requirement. For the pulse generator design, there are many ways to generate the short pulse signals with different technologies. Existing methods for generating subnanosecond pulses are generally based on hybrid circuit design topologies, requiring different kinds of discrete components, therefore resulting in large-size circuits and increased cost. These existing pulse generators normally are not optimized for power consumption and the feasibility of integrating them into a wireless device. Some of the pulse generators were developed using spark gaps [16], which are not an option for consumer electronics due to their size. Another method of generating subnanosecond impulse and monocycle pulses involves the hybrid circuits based on Schottky diode, step recovery diode (SRD), and planar transmission lines [10]-[1], which are also not suitable for RFIC applications. In addition to the above-mentioned pulse generation in time-domain, the pulse signal can also be generated with frequency-domain topology, which should be very accurate in theory [17]-[18]. The fundamental of this topology is to use the Fourier series based method to implement the waveform generation in frequency domain. By expanding the desired waveform into Fourier series, the corresponding sinusoidal components are generated and transmitted to obtain the signal in frequency-domain by summing the low power harmonics, and the resulted pulse signal should be very accurate. However, the Fourier series expansion contains an infinite amount of terms; in

0 reality the transmitter only transmits a finite number of harmonic terms, depending on the desired performance. Although in theory this method can generate extremely accurate pulse signal with any shape, it requires a very complex transmitter design because of the large amount of harmonic components. In addition, the receiver will have to receive all of the generated harmonics, resulting in the complicated receiver. Due to the complex nature of the design, it is not suitable for most wireless UWB applications. Unfortunately, all the design topologies mentioned above have one common problem, relatively large circuit size, therefore high cost. This problem makes them not the good choice for the compact UWB applications. With the development of semiconductor technology, more and more UWB designs focus on CMOS RFIC technology because of its low cost and low power consumption, easy integration with other components, such as digital circuits and planar antennas. In this dissertation, the novel tunable pulse generator based on commercial CMOS technology is developed to produce both Gaussian impulse and monocycle pulse with tunable duration. Furthermore, this pulse generator is integrated with BPSK modulator together to form the transmitter front-end module. The design details of the impulse-type UWB transmitter will be described in chapter III..4. UWB Receiver The impulse-type UWB receiver directly converts the received RF signal into a baseband output signal. The corresponding block diagram is shown in Fig..11. The receiver examined here consists of a LNA, a correlation circuit, and a template pulse generator. The local oscillator drives the pulse generator and determines the PRF of the system. To maximize the processing gain and SNR, the template waveform should have similar shape to that of the received signal. After passing LNA, the received pulse signal is coherently correlated with the template pulse waveform through front-end crosscorrelator, and the input pulse train is converted to baseband signal in one stage.

1 Therefore no intermediate frequency stage is needed, thus greatly reducing the system complexity. Antenna LNA Receiver Front End Integrator S/H Data Out Correlator Pulse Generator PRF Oscillator Fig..11. Receiver top level schematic. The correlation circuit is the essential element of the impulse-type UWB receiver. It consists of the multiplier, integrator, and sampling/holding (S/H) circuit. The multiplier multiplies the received signal with the template waveform. The result of the multiplier is integrated over several periods of the received pulse train to maximize the received signal power and to minimize the noise component. Having a train of pulses to integrate over, the correlated signal is raised from the noise. Therefore if more pulses are used for each symbol, it will result better SNR, since more correlated energy is integrated over the duration of each symbol. Considering the unique feature of the impulse-type UWB, there is a stringent requirement for the correlation speed. That means both multiplier and integrator must be fast enough to process each pulse. This brings great challenge to the correlator design. Like most spread spectrum systems, where energy generated in a particular bandwidth is deliberately spread in the frequency domain, resulting in a signal with a wider bandwidth, processing gain (PG) is also an important characteristic in an UWB

system. To combat noise and interference, a group of N pulses are used to transmit each symbol, hence the energy of the symbol is spread over N pulses and processing gain can be achieved. The processing gain in db derived from this procedure can be defined as [19] PG 10 ( N ) 1 = 10log (.6) Furthermore, the pulse signal only occupies a very small part of the entire period. This means the duty cycle of the pulses can be extremely low, sometimes less than 1%. Therefore the receiver is only required to work for a small fraction of the period between pulses, and the impact of any continuous source of interference is reduced so that it is only relevant when the receiver is attempting to detect a pulse. Hence the processing gain due to the low duty cycle is given by [19] T f = 10 log (.7) Tp PG 10 where T f is the period time and T p is pulse width. Total processing gain PG is the sum of the two processing gains [19] T f = PG + = ( ) + 1 PG 10 log10 N 10log (.8) Tp PG 10 For an impulse-type UWB, suppose the period time is 100 ns and the pulse width is 00 ps, the PG from the duty cycle will be about 7 db. Since the UWB uses multiple pulses to recover each bit of information, if one digital bit is determined by integrating over 100 pulses, then the PG 1 will be another 0 db. The total PG for the

3 UWB system is about 47 db. Since PRF of the pulse is 10 MHz and each bit covers 100 pulses, the resulting data rate is 100 Kbps as obtained from (.8)..5 UWB Antennas.5.1 Introduction Unlike traditional narrow band systems, where antennas are often considered as non-distortion device in system analysis, UWB antennas play a very important role in signal analysis of UWB system. Because of the very large bandwidth of an UWB signal, the antenna has a strong impact on parameters such as impedance matching, radiation pattern as well as gain variations in UWB than in narrow band systems. For such very wideband antennas, issues of linearity of antenna transfer function, radiation efficiency and impedance match across the band present difficult problems. Therefore, an effective UWB antenna is a critical part of an overall UWB system design..5. Antenna Types Considering the traditional ultra wideband antennas, a lot of them are multinarrowband antennas, which means the operational band of the antennas at specific time is actually narrowband channel, such as AM broadcast antenna, the real effective fractional bandwidth is only very small amount value, and only one channel can be received at a time. On the contrary, in UWB systems, the ultra wideband requirement brings great challenges to the antenna design. For impulse-type UWB systems, this demanding is especially strict, as the antenna needs to cover the entire frequency range of 3.1 10.6 GHz and radiates or receives all the frequency components coherent simultaneously. Thus, antenna behavior and performance must be consistent with no obvious variations and predictable across the entire band. Ideally, pattern and matching should be constant and no variations across the entire band. Furthermore, the transmitted and received UWB signals require antennas not only radiating energy efficiently but also having linear phase response over the ultra

4 wide frequency band, so clean, temporally non-dispersed waveforms can be achieved with very precise timing accuracy. Unfortunately, many conventional ultra wide antennas cannot meet these requirements; one such example is the log-periodic antenna. It is one kind of frequency-independent antennas, but it is dispersive. The smallest antenna part radiates the highest frequency component while the largest antenna part radiates the lowest frequency component. The result is a chirp-like, dispersive waveform with different shape at different azimuthal angles around the antenna because of the dispersion variations depending on the different direction and ranges. Obviously it is not suitable to UWB applications. Antennas currently used in UWB systems normally can be classified as directional or omni-directional. Directional antennas include TEM horn and its variants, Vivaldi, and reflector antennas [14], [0]-[3], while the omni-directional antennas include dipoles, loops and their variants [4]-[6]. The directional antennas have the common properties of high gain, narrow field of view, and relatively larger size; which find applications in outdoor base station communications, GPRs. On the other hand, an omni-directional antenna has relatively low gain, a wide field of view, and smaller size, therefore is suitable for use in short range, low power indoor UWB radio systems. Currently, a few high-quality non-dispersive UWB antennas are commercially available [7]. However, the large size of these antennas makes them less suitable for most commercial applications and particularly not feasible for portable or handheld uses where space is at a particular premium. Therefore, there is a great need for low-cost, compact, easy-to-manufacture UWB antennas that are omni-directional, radiationefficient, and have low distortion. These antennas should also facilitate integration with UWB CMOS RFIC chips. Since a small element antenna not only tends to be nondispersive, but also more compact, small element antennas are preferred in many applications.

5.5.3 Simulation Tools UWB antenna simulations can be performed in both time domain and frequency domain, since time and frequency domain are connected through Fourier transform. But considering the unique characteristic of UWB signal, very narrow width in time domain and ultra wideband in frequency domain, the time-domain simulation should be the better option. Since conducting analysis in the frequency domain requires the calculation of far-field values for both amplitude and phase, and it must be done over a very wide frequency range to be able to accurately extract the shape of the radiated pulse, which makes certain calculations very time consuming or, due to lack of memory, impossible to perform. Typically, the electromagnetic simulation software available to UWB antenna analysis can be classified as following categories: 1. Finite-element method: The software based on finite-element method (FEM) can simulate antennas with arbitrary shape and material, such as Ansoft HFSS [8]. Hence they are the three-dimensional (3D) software. However, when the antenna structure is complicated, FEM mesh number is too large to consume all the computer resource. In addition, the technique only works on single frequency at a time, implying that the huge simulation time for ultra wideband simulation.. Method of moments: The software based on method of moments (MoM) runs much faster than that of FEM technique, especially for planar antenna structure with regular shapes. MoM based software such as Zeland IE3D [9] and Agilent MOMENTUM [30] do not use adaptive meshing, instead user-defined grid density is used, therefore the simulation time is reduced. One of the limitations is that most MOM codes can only support planar structures with infinite dielectric layers. Therefore sometimes they are called two and half dimensional (.5D) software, not suitable for the objects with arbitrary three-dimensional shape.

6 3. Finite-difference time-domain: The finite-difference time-domain (FDTD) and other time-domain methods are inherently applicable for antenna simulation with the ultra-short pulses. Software like CST Microwave Studio [31] can simulate antennas with arbitrary shape and material based on finite integration. So they are also 3D software. With improved grid generation methods as well as increased computing capacity, time-domain methods have the superior advantage for UWB simulations..5.4 Measurement Techniques UWB antenna-to-antenna time-domain transmission response measurement can be performed in both frequency-domain and time-domain [3]-[33]. Following is the brief description for each method. As for the measurement techniques of impedance matching performance of UWB antenna, chapter V will present the detailed description. 1. Frequency-domain measurement: In frequency-domain, UWB antenna can be measured using frequency sweeping technique with standard vector network analyzer (VNA). This makes the measurement set-up quite simple. Both amplitude and phase of the transmission are measured and the time-domain performance is derived through Fourier transform. Before measurement, the VNA should be calibrated over the whole UWB frequency range to avoid artificial distortion of the waveform due to aliasing. The frequency band that can be measured depends on the frequency range of VNA.. Time-Domain measurement: Typical time-domain antenna measurement consists of a pulse generator and a digital sampling oscilloscope. The pulse generator produces the pulse signal with very short rising and falling times and excites the transmitting antenna; the received waveform is captured by the oscilloscope which connected to the receiving antenna. If the exciting pulse bandwidth is much larger than

7 the antenna system bandwidth, then the measured signal is a good approximation of the system impulse response. Otherwise, deconvolution process is required to get actual transmission response of UWB antenna when the bandwidth of excitation signal is comparable to that of the antenna [3].

8 CHAPTER III UWB TRANSMITTER DESIGN * Impulse-type UWB transmitter normally consists of two fundamental parts: pulse generator and modulator. The pulse generator is a key component for both the transmitter and receiver. Based on the specific requirements, the pulse generator can generate the impulse or monocycle pulse. Moreover, the generated UWB signal should also meet the other specifications of the impulse UWB systems. As for the modulator, depending on the different applications, PPM or BPSK modulation techniques can be selected to modulate information bits directly into very short pulses. The most essential specification of the pulse generator is the duration of the output pulse. Small duration of the output pulse can provide very accurate resolution for target detection or range accuracy. The generated pulse signal should also have good shape with small distortion and minimum ringing tails. Another desirable function of pulse generator is the tuning capability to generate pulse signals of different durations. For instance, tunable pulse generators produce flexibility for UWB impulse radar [34]. Tuning ability is also useful for compensating variations caused by CMOS process. In a tunable pulse signal, the wider pulse contains large low-frequency components, which can propagate more deeply into a medium due to relatively low propagation loss at low frequencies. The shorter pulse, on the other hand, has more high-frequency components, thus making feasible higher range resolution. Therefore, a pulse that can change its duration, especially by an electronic means, would have both advantages of increased penetration (or range) and fine range resolution and is attractive for UWB systems. The polarimetric video impulse radar described in [7] and [8] is a good example showing the usefulness of tuning capability of the pulse generator. UWB tunable impulse and * 006 IEEE. Parts of this chapter are reprinted, with permission, from Meng Miao and Cam Nguyen, On the development of an integrated CMOS-based UWB tunable-pulse transmit module, IEEE Transactions on Microwave Theory and Techniques, vol. 54, pp.3681-3687, October 006.

9 monocycle pulse transmitters have been recently developed using step-recovery and PIN diodes and hybrid circuits [11]-[1]. Most existing UWB pulse generators are based on approaches developed for radar applications and involve hybrid circuit techniques. Commercial UWB systems, particularly those for wireless communications and sensors, prefer CMOS RFIC design for low cost, low power consumption, and easy integration with digital ICs (and hence better potential for complex system-on-chip). To this end, new types of integrated-circuit pulse generators, different from the traditional hybrid circuits, should be employed based on CMOS processes to produce pulses with sub-nanosecond pulse-width. Recently, several CMOS pulse generator topologies were proposed for UWB communications using IBM 0.18-µm BiCMOS [35], TSMC 0.18-µm CMOS [36]-[37], and CSM 0.18-µm CMOS/BiCMOS [38] process. However, no experimental results were presented for these circuits. The calculated pulse-widths and amplitudes of the output pulses are around 300 ps and 0 mv [35], 300 ps and.97 mv [36], 380 ps and 650 mv [37], and 00 ps and 7 mv [38]. Furthermore, a square-wave and a 1.5-GHz clock signal were used externally as the input in [35], [38] and [36] for simulations, respectively. In this chapter, a novel fully integrated impulse-type UWB transmitter is presented. The tunable monocycle-pulse generator [39] and a BPSK modulator were designed and fabricated using a standard low-cost CMOS process. The pulse generator component produces 0.7 0.75 V peak-to-peak monocycle pulse with 140 350 ps tunable pulse duration. Without the pulse-shaping circuitry, it can also generate 0.95 1.05 V peak-to-peak Gaussian-type impulse signal with 100 300 ps tunable pulse duration. These pulse signals can be used for various UWB systems. An external clock signal operating at a low frequency of only 10 MHz is needed. BPSK modulator controls the pulse generator to generate positive or negative pulse signal depending on the 1 or 0 digital data information. This chapter is arranged as follows. First, some basic components used in the transmitter design, such as CMOS inverter, delay cell, and NOR/NAND gate block will

30 be briefly described. Then come with the tunable pulse generator design as well as BPSK modulator design. At last the tunable impulse-type transmitter with fully integrated tunable pulse generator and BPSK modulator is presented. 3.1 Basic Components Overview 3.1.1 CMOS Inverter Basics CMOS inverter is the essential element in the tunable pulse generator design, and plays an important role in the delay cell and square-wave generator. In fact, the CMOS inverter is a basic building block for digital circuit design. However, the operation of the CMOS inverter in tunable pulse generator design is somewhat different with that of the digital case. As shown in Fig. 3.1, the CMOS inverter consists of a pair of enhancementtype NMOS and PMOS transistors, operating in complementary mode. The input voltage V in is connected to the gates of both transistors. The substrate of the NMOS transistor is connected to the ground, while the substrate of the PMOS transistor is connected to the power supply voltage V dd, to reverse-bias the source and drain junctions. Since V SB = 0 for both transistors, there will be no substrate-bias effects. V dd V in V out V in V out Fig. 3.1. CMOS inverter circuit and its symbol.

31 Comparing with other inverter configurations, such as MOS current mode logic (MCML), the CMOS inverter has two important advantages. The first and the most important one is its virtually negligible steady-state power dissipation, except for small power dissipation due to the leakage currents. While in other inverter structures like MCML, a nonzero constant steady-state current is drawn from the power source when the driver transistor is turned on, which results in a significant DC power consumption. The other advantage of the CMOS configuration is that the voltage transfer characteristic (VTC) exhibits a full output voltage swing between 0 V and V dd MCML has the much lower swing voltage than V dd driving voltage and is not suitable to our tunable pulse generator design.. On the contrary,, which cannot provide enough The inverter threshold voltage V th, which is considered as the transition voltage and defined as the point where V in = V out, is an important parameter characterizing the steady-state input-output behavior of the CMOS inverter [40]. V th = V T 0, n + 1 k R 1 + ( V + V ) 1 k dd R T 0, p (3.1) where V dd is the power supply, V T 0, n is the NMOS threshold voltage, V T 0, p is the PMOS threshold voltage, and k R is defined as [40] k n k R = (3.) k p Here the transconductance parameters are [40]

3 k n W = μ n Cox (3.3a) L k p W = μ p Cox (3.3b) L where μ n is the electron surface mobility in the NMOS transistor, mobility in the PMOS transistor, μ p is the surface hole C ox is the gate oxide capacitance, W and L are the channel width and length respectively. Since CMOS inverter is fully complementary structure, to achieve completely symmetric output signal, the threshold voltages are set as V T 0 = V T, n Therefore [40] 0 = V T 0, p. k k n p symmetric inverter = 1 (3.4) From [40] k k n p μ nc = μ C p ox ox W L W L n p W μ n L = W μ p L n p (3.5) The unity-ratio condition for the ideal symmetric inverter requires that W L W L n p μ p = μ n (3.6)

33 Since μ p (30 cm / V s ) is much smaller than μ n (580 cm / V s ) [40], to achieve symmetric input-output performance in our CMOS inverter design, we select the ratio of PMOS transistor to NMOS transistor as: W L W L p n = 3 (3.7) For the condition of same minimum gate length L for both PMOS and NMOS transistors, W = 3W. p n 3.1. Inverter Switching Characteristics First some commonly used delay time definitions are introduced. As shown in Fig. 3., the propagation delay times τ PHL and τ PLH determine the input-to-output signal delay during the high-to-low and low-to-high transitions of the output, respectively. τ PHL is the time delay between the V50% -transition of the rising input voltage and the V50% - transition of the falling output voltage. Similarly, τ PLH is defined as the time delay between the V50 % -transition of the falling input voltage and the V50 % rising output voltage [40]. -transition of the The rising time τ rise is defined as the time required for the output voltage to rise from the V 10% level to V 90% level. Similarly, the falling time τ fall is defined as the time required for the output voltage to drop from the V 90% level to V 10% level [40].

34 Fig. 3.. CMOS inverter delay-time definitions. Assuming the input signal waveform is a step pulse with zero rise and fall times, the propagation delay time for high-to-low output transition τ PHL of CMOS inverter can be expressed as: [40] ( V V ) = C V 4 load T, n dd T, n τ + ln ( ) 1 PHL (3.8a) kn Vdd VT, n Vdd VT, n Vdd

35 Similarly, the propagation delay time from low-to-high output transition τ PLH of the CMOS inverter is [40]: ( V V ) C V 4 load T, p dd T, p τ = + ln 1 PLH (3.8b) k ( ) p Vdd VT, p Vdd V V T, p dd where C load is the load capacitance which combines capacitance at the output node [40]. Comparing the above time delay expressions, for τ PHL = τ PLH, we have the condition of V, = V T, p and k n = k p. T n Considering the situation where the input voltage waveform is not an ideal pulse waveform, but has finite rising and falling times, τ r and τ f, the corresponding propagation delay times can be empirically expressed as [40]: τ r ( ) ( ) τ PHL actual = τ PHL stepinput + (3.9a) τ f τ ( ) ( ) PLH actual = τ PLH stepinput + (3.9b) where τ ( step input) and ( stepinput) PHL τ are the propagation delay time values for PLH step pulse input waveform given in (3.8). Assuming the input voltage of the CMOS inverter is an ideal step waveform with negligible rising and falling times, the average power dissipation of the CMOS inverter can be written as: [40] P avg = C load V dd f (3.10)

36 From (3.10) we can find that the average power dissipation of the CMOS inverter is proportional to the switching frequency f. Since in our pulse generator design the frequency of the clock signal is only 10 MHz, comparing with MCML structure, where the static power consumption is average power dissipation. V dd I, hence the CMOS inverter has the much smaller 3.1.3 Two-input NOR/NAND Gate Blocks Fig. 3.3 shows the circuit diagram of a two-input CMOS NOR gate block. The circuit consists of series-connected complementary PMOS transistors and parallelconnected NMOS transistors. The input voltages V A and V B are applied to the gates of one NMOS and PMOS transistors respectively. V dd V A V out V A V out V B V B Fig. 3.3. CMOS NOR gate block and its symbol. For NOR gate block, the output voltage is high only at the condition that both input signals V A and V B are low voltages. For all the other conditions, the output voltage is always low. Based on this characteristic, NOR gate block can be used to generate

37 positive impulse signal in our pulse generator design by adjusting the time difference between two low-voltage input signals to a very small value. Fig. 3.4 shows the circuit diagram of a two-input CMOS NAND gate block. The circuit consists of parallel-connected PMOS transistors and series-connected complementary NMOS transistors. The operating principle is exact dual of the CMOS NOR gate block. Therefore for NAND gate block, the output voltage is low only at the condition that both V A and V B are high voltages. For all the other conditions, the output voltage is always high. Hence the NAND gate block can be used to generate negative impulse signal in pulse generator design by controlling the time difference between two high-voltage input signals to a small value. V dd V A Vout V A V out V B V B Fig. 3.4. CMOS NAND gate block and its symbol. 3.1.4 Tunable Delay Cell Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in ICs. There are three different kinds of delay element architectures in CMOS VLSI design: transmission gate based, cascaded inverter based, and voltage controlled based [41]. Here we select the voltage-controlled shunt-capacitor

38 delay element as the tuning delay cell in the tunable pulse generator design because of its relatively simple structure [4]-[43]. Fig. 3.5 shows the basic circuit of the voltage-controlled shunt-capacitor delay element. It consists of a shunt-controlled transistor M1 and the shunt MOS capacitor M. The control voltage V ctrl adjusts the resistance of the shunt transistor M1, which connects the load capacitance M to the output of a logic stage. Tuning voltage V ctrl modulates the resistance of shunt transistor M1, which is equivalent to changing the effective shunt capacitor value to the output of the inverter. Larger value of V ctrl decreases the resistance of the shunt transistor M1, so the effective shunt capacitance at the logic gate output is bigger, producing a larger time delay. By selecting a suitable size shunt capacitor M with respect to the specific output capacitor load, the desired continuous time tuning range can be achieved. The tunable capability of this shuntcapacitor delay element plays an important role in our tunable pulse generator design, and the details will be described in next section. V in M1 V out V ctrl M Fig. 3.5. Shunt-capacitor delay element.

39 3. Tunable Pulse Generator Design Pulse generator is a fundamental component in impulse-type UWB systems. It can function as a source for the transmitter or an internal source for the template signal in the receiver. The continuous tunable advantage makes this pulse generator immune to the CMOS process variations and temperature changes. Fig. 3.6 shows the block diagram of the proposed CMOS UWB tunable monocycle pulse generator. It integrates a tuning delay circuit, a square-wave generator, an impulse-forming circuit, and a pulseshaping circuit in a single chip. Tuning delay Square wave generation Impulse forming Pulse shaping Input Tunable delay cell Reference cell A B NOR C D Output Fig. 3.6. Block diagram of CMOS UWB tunable monocycle pulse generator chip. 3..1 Tuning Delay Component The tuning delay component includes a pair of parallel tunable delay cell and reference cell using shunt-capacitor delay elements [43], as shown in Fig. 3.7. M is a NMOS-type capacitor. The NMOS transistor M1 controls the charging and discharging current to the capacitor M. The only difference between the circuits of the tunable delay cell and reference cell is the gate voltage of the shunt transistor M1, which controls the charge current. For the tunable delay cell, variable control voltage V ctrl between 0 V and V dd is applied to the gate of transistor M1 to produce continuous delay variation. On the

40 other hand, for the reference cell, the gate of the transistor M1 is directly connected to the ground, so the gate voltage of M1 is fixed to zero, therefore the time-delay is constant and provides a reference position to the tunable delay cell. V in M1 V out V in M1 V out V ctrl M M (a) (b) Fig. 3.7. Circuit schematics of tunable delay cell (a) and reference cell (b). The advantage of using two identical delay structures is that the relative timedelay between the two paths can be easily controlled. Another reason is that for single delay cell situation, under the perfect condition, the delay cell is equivalent to an infinitesimal capacitor when the gate voltage of the shunt transistor M1 is 0 V. However, in reality, there always exists the leak current inside the shunt transistor M1 and makes the effective capacitor a finite value. That means for the method where only single delay cell is used, an inherent minimum absolute time delay always exists caused by the nonperfect delay cell, and the value of this time delay sometimes is much larger than the minimum pulse width required to achieve. Therefore single delay cell topology prevents us to design the pulse generator with extremely narrow pulse signal, even it occupies less die area. With the adoption of the parallel delay elements, this parasitic time delay effect can be totally eliminated, and the minimum relative time difference achieved can be as small as possible. This advantage guarantees the designed pulse generator to produce the pulse signal with extremely small pulse width. The larger the value of capacitor M, the

41 broader the tuning range of the generated pulse width. Hence by tuning the gatecontrolled voltage V ctrl within the range of 0 V to V dd, the pulse signal with different pulse width can be achieved. Another issue concerning the delay element is that the pair of parallel delay cells is located at the first stage of the entire pulse generator circuit, directly in front of the square wave generator. This arrangement helps reduce the strict requirement for the delay element design. As the input signal of the pulse generator is the sinusoidal signal with the frequency of only 10 MHz, which is much lower comparing to the maximum operating frequency of the CMOS inverter and delay cell. The extra capacitor load introduced by the tuning delay cell has negligible effects on the rising and falling times of the final output signal of the CMOS inverter, with the reasonable tuning range of the time delay around 500 ps. If the tuning delay cells succeed the square wave generator and precede the impulse-forming circuit, which seems a straightforward topology to generate tunable delay at the first glance, it actually brings other potential problems on the delay cell design. The reason is very clear, the signals produced by square wave generator have the very sharp rising and falling edges, normally in the order of less than 100 ps, which correspond to the frequency components of more than 10 GHz. After passing the delay cell, the signal should keep the same rising and falling times, which means the operating frequency of the delay cells should be more than 10 GHz; this makes the delay cell design a really difficult work. Furthermore, the input capacitor of the next stage impulse-forming circuit is very large because of the driving capability requirement; to achieve the same time delay range of 500 ps, the size of the shuntcapacitor M should increase dramatically. 3.. Square Wave Generator For the tunable pulse generator design, the tunable delay cells that can produce the extremely short relative time difference between two signal paths are certainly important to generate the pulse signal with very narrow pulse width, but it is still not enough if only these components are involved in pulse generation. There are also other

4 factors affecting the final pulse signal performance, and these parameters are the rising and falling times of the generated square wave signals. The function of the square-wave generator is to produce a square-wave signal with very short rising and falling times when a sinusoidal clock signal is fed to the circuit. Sharp rising/falling time is needed as the minimum width of the impulse signal generated in the subsequent stage is determined by the rising and falling times of the feed square-wave. The succeeding stage of square wave generator is the impulseforming block, whose size should be large enough to provide the driving capability for the next stage circuit, therefore the input capacitor of the impulse-forming block is very large. To drive this large capacitance effectively without sacrificing rising/falling edge performance, a series of CMOS inverters with increasing size for each step, i.e., a buffer circuit, is used to increase the drive capabilities and shorten the rising and falling times of the square-wave signal. A 0 (W p1 /W n1 ) A 1 (W p1 /W n1 ) A N-1 (W p1 /W n1 ) In...... Out 1 N C load Fig. 3.8. Cascade of inverters used to drive a large load capacitance. Consider the cascade circuit of N inverters driving a load capacitance C load, which is shown in Fig. 3.8, where A is the constant larger than 1, W p1 and W n1 are the channel widths of the PMOS and MOS of the first CMOS inverter respectively. Each inverter is A times larger than the previous one, therefore each inverter s input capacitance is larger than the previous inverter s input capacitance by a factor of A [44]:

43 C N 1 = A C, Cin3 = A Cin 1, K K, CinN = A Cin 1 in in1 (3.11) The corresponding effective switching resistances are [44]: Rn, p1 Rn, p1 Rn, p1 Rn, p =, Rn, p3 =, K K, R n, pn = (3.1) N 1 A A A where the effective switching resistance of the first CMOS inverter R n, p1 is defined as [44] R n, p1 = μ C n ox V dd n1 p ox p1 ( V V ) ( ) dd THN L W + μ C V V dd dd V THP L W (3.13) Therefore, for each stage of the buffer, same delay of Rn, p1 Cin 1 is achieved. Typically, assume the load capacitance input capacitance of the last inverter of the buffer [44]: C load has the following relation with C load N = A CinN = A Cin1 (3.14) We can determine the factor A: A C C in1 1/ N load = (3.15) Therefore the total delay of the inverter buffer can be found from [44] ( +τ ) =.7 N( R + R )( C + A C ) τ (3.16) PHL PLH total 0 n1 p1 out1 in1

44 where C out1 is the total capacitance on the output of the first inverter, which includes the sum of the output capacitance of the inverter, any capacitance of interconnecting lines, and the input capacitance of the following stage. For the square wave generator in the tunable pulse generator design, minimum time delay is not an essential parameter, so the value of factor A can be selected other than =.7 (corresponding to minimum time delay condition) [44] to reduce the stage number of the square wave generator. During the square wave generator design, the size of the inverters sets the rising and falling times; however, there are some constraints that should be considered. First, the size of the first stage inverter should be chosen with a small value, so that the input capacitance C in1 of the CMOS inverter is small enough to maintain the large enough ratio of C shunt to in1 C, where C shunt is capacitor M of tuning delay cell. Therefore the broad enough tuning range is achieved. If the size of the first stage inverter increases too much, to keep the same time-delay tuning range, the size of the shunt-capacitor in tuning delay element has to increase accordingly. This will consume more die area. Another problem is that if too large inverters are used, according to equation (3.1), the number of buffer stages N in the square wave generator must be increased, which increases the power consumption. The last demand was that the rising and falling times should be approximately the same, which is important to the symmetric pulse signal generation. This was accomplished by making the PMOS transistor about 3 times larger than the NMOS transistor in each inverter because of the different carrier surface mobility in PMOS and NMOS [44]. 3..3 Impulse-forming Block The impulse-forming block can be designated to generate positive or negative impulse signal, depending on which gate block was selected as the impulse-forming core. If the NOR gate block is used in the impulse-forming block, the output signal is positive impulse; for the NAND gate block, the negative impulse signal is generated. From now on, only impulse-forming block with positive impulse will be described, the

45 analysis of the impulse-forming block with negative impulse signal can follow the similar design topology. The impulse-forming block is made up of an inverted delay stage and a NOR gate block, as shown in Fig. 3.6. The main purpose of the NOR gate block is to generate a positive impulse-like signal and provide driving capability to the next stage. This impulse should also be able to evoke the impulse response of the succeeding component to further produce a monocycle pulse (or other kind of pulse waveforms as needed for UWB systems). The function of the inverted delay stage is to provide one input of the NOR gate block with a square wave signal, which is the reverse replica of the other input signal. As the signal produced by square wave generator has the extremely-narrow symmetric rising/falling edges, the size of this inverter should be selected to provide enough driving capability to maintain the same rising/falling edges for the output signal. With the help of the previous stage tuning delay component, the time difference between two input signals of NOR gate block can be adjusted continuously to generate the positive impulse signal with tunable pulse width. 3..4 Pulse-shaping Circuit The last stage of the tunable monocycle pulse generator is the pulse-shaping circuit, which consist of a shunt on-chip spiral inductor and a series metal-insulatormetal (MIM) capacitor, operating as a high pass filter (HPF). The on-chip octagonal shape spiral inductor was designed using the EM software IE3D [9] to achieve the improved quality factor Q comparing with the inductor library model provided in foundry design kit. By optimizing the values of spiral inductor and MIM capacitor, the pulse-shaping circuit functions approximately like a differentiator for the designed tunable impulse signal. As a result, a monocycle pulse signal with tunable duration can be generated when the impulse-like signal from the impulse-forming circuit is fed to the pulse-shaping circuit.

46 3..5 Tunable Pulse Illustration Fig. 3.9 illustrates the voltage variations at different nodes A, B, C, and D of the tunable monocycle pulse generator designated in Fig. 3.6 when a 10-MHz sinusoidal clock signal is fed to the generator. Tunable delay A B C D Fig. 3.9. Illustration of signal shapes at each node of tunable pulse generator shown in Fig. 3.6. As shown in Fig. 3.6, the input clock signal is divided equally into two paths: one signal passing through the tunable delay cell in the top path and another going through the reference cell in the bottom path. At node B, a square-wave signal (0 V to V dd ) with very short rising and falling times is generated and functions as one of the inputs to the following NOR gate block. For the tunable delay cell, by choosing a suitable control

47 voltage V ctrl between 0 V and V dd, another square wave with a different delay time is generated at node A. This signal is the reversed replica of that at node B with a certain time difference and acts as another input signal to the NOR gate block. The output of the NOR gate block is at high state ( V dd ) only when the inputs to the NOR gate are both at low state (0 V). For all the other input states, the output are always low (0 V). When these two reversed square waves at A and B are fed to the NOR gate block, a narrow impulse-like signal is generated at node C. The width of this impulse signal depends on the relative time difference between these two square-wave signals and the widths of their rising and falling edges. The impulse signal at node C, therefore, can be easily generated with a continuously tuning duration. A smaller time difference between nodes A and B generates a narrower impulse with a smaller peak-topeak voltage on node C, while a larger time difference produces a broader impulse with a higher peak-to-peak voltage. When the tunable impulse signal is sent to the pulseshaping circuit, a monocycle pulse signal with different durations is achieved at node D. 3..6 Simulation and Measurement Results All the chips designed in this dissertation were fabricated using the standard, low-cost TSMC 0.5-µm, 0.18-µm, or Jazz 0.18-µm CMOS process [45]-[47]. For TSMC 0.5-µm, a single.5-v low supply voltage was used for the whole circuits, while for TSMC 0.18-µm and Jazz 0.18-µm, a single 1.8-V low supply voltage was applied. The design and simulation were performed using the Agilent Advanced Design System (ADS) [48], Cadence Design Systems [49], TSMC 0.5-µm, 0.18-µm, and JAZZ 0.18-µm CMOS process Design Kit [45]-[47]. Fig. 3.10 shows the photograph of the tunable CMOS monocycle pulse generator fabricated using Jazz 0.18-µm CMOS process. Comparing to the pulse generator fabricated with TSMC 0.5-µm in [39], the proposed circuit achieves the improved performance on pulse width and pulse tuning range, with the more compact size. The monocycle pulse generator core itself occupies an area of 40 µm 160 µm. The CMOS tunable monocycle pulse generator circuit and other accessory components were

48 measured on-wafer in both time and frequency domains using a probe station, digitizing oscilloscope, and spectrum analyzer. Fig. 3.10. Photograph of the 0.18-μm CMOS tunable monocycle pulse generator chip including pads for on-wafer probe measurement. To verify the design concept of each component inside tunable monocycle pulse generator, several separate components were fabricated and measured. All the measurements are performed under the condition of 50-Ω load unless otherwise specified.

49 First the square wave generator integrated with tunable delay cell is measured, with the 10-MHz sinusoidal clock signal as the input. The capacitor value of shuntcapacitor M of the tuning delay cell was optimized through simulation with ADS [48] based on the structure parameters shown in Table 3.1, to achieve 500 ps around delay tuning range. The final capacitor value of the shunt-capacitor M was chosen as 0. pf in simulation. The sizes of the inverters in corresponding square wave generator are shown in Table 3.1. Table 3.1. The sizes of inverters in square wave generator. First stage inverter Last stage inverter Transistor NMOS PMOS NMOS PMOS Width (µm) 5 15 80 40 Length (µm) 0.18 0.18 0.18 0.18 1.5 1.5 Output Signal (V) 1 0.75 0.5 0.5 0 0 50 100 150 00 50 300 Time (ns) Fig. 3.11. Output signal of square wave generator.

50 The measured output signal of the tunable square wave generator with the abovementioned structure parameters is shown in Fig. 3.11, with the period of 100 ns. The calculated pattern is presented in Fig. 3.1 for comparison purpose. The rising and falling edges of the generated square wave signal, corresponding to the delay tuning voltage V ctrl of 0 V and 1.8 V respectively, are presented in Fig. 3.1 as well in details. Fig. 3.1. Rising and falling edges of tunable square wave signal. As shown in Fig. 3.11, the generated waveform from tunable square wave generator is symmetric and has the good square wave shape, which validates the design of this component. In addition, Fig. 3.1 presents the important information about delay tuning range and rising/falling edges, which are the critical factors in tunable pulse generator design. As shown in Fig. 3.1, the measured tuning range of this tunable square wave generator is around 400 ps, which is a little narrower than the simulated one. Since the delay tuning range is in proportional to the ratio of the shunt-capacitor to the input capacitor value of the first stage inverter of the square wave generator, the parasitic capacitor associated with the inverter makes the overall input capacitor value larger than the simulated one, which results in the reduced capacitor ratio, therefore, the smaller tuning range. However, the 400 ps delay tuning range still can meet the

51 requirement of the tunable pulse generator design. The details of rising and falling edges in Fig. 3.1 also confirm the symmetry of the generated square wave. Comparing with simulation results, measured rising and falling edges (10% to 90%) have the width of around 40 ps, which is close to the simulated results. The difference between two results is caused by the parasitic capacitors associated with stage inverters of the square wave generator. The parasitic resistance makes the high-level voltages of the measured results a little lower than the simulation. Because of the very compact structure, extremely short interconnecting lines, and large enough vias used in the circuit, the resulting parasitic resistance is not big, hence the difference is not much. 0-5 Magnitude (db) -10-15 -0-5 -30-35 0 5 10 15 0 Frequency (GHz) Fig. 3.13. Transfer function of designed pulse shaping circuit. Next, the performance of the pulse shaping circuit was checked, in both frequency-domain and time-domain. The designed shunt on-wafer spiral inductor has the inductor value of 0.53 nh, and the selected series MIM capacitor is 0.4 pf. Fig. 3.13

5 shows the simulated transfer characteristics of this high pass filter (HPF). The corresponding measured time-domain results for input impulse signal with different pulse widths are shown in Fig. 3.14. Here the commercial pulse generator was used to generate the positive impulse signal with different pulse widths. As shown in Fig. 3.13, the pulse-shaping circuit effectively attenuates the lowfrequency components of the input signal below 3GHz. The measured time-domain performance of the pulse-shaping circuit also confirmed the design validity as shown in Fig. 3.14. The input signals are impulses generated by the commercial pulse generator with 1 V p-p and pulse widths of 100, 00, and 300 ps, respectively. The output signals from the pulse-shaping circuit are clearly the monocycle pulse signals with amplitude of 0.8 V p-p and almost symmetric positive and negative shapes. Therefore the proposed pulse-shaping circuit can work effectively to generate the monocycle signal when the input impulse signal is within the pulse width range of 100 to 300 ps, which is the operating range of the proposed pulse generator. Fig. 3.14. Pulse-shaping circuit performance for impulse input.

53 Table 3.. The size of NOR gate block. Transistor NMOS PMOS Width (µm) 80 30 Length (µm) 0.18 0.18 To verify the design concept for generating tunable impulse, a separate chip without the pulse-shaping circuitry was first measured. The parameters of the impulseforming component of the circuit, i.e. NOR gate block as shown in Fig. 3.3, are given in Table 3.. Large size transistors were selected to provide enough driving capability for the external 50-Ω load. To reduce the parasitic capacitor and resistor effects, multiplefinger gate structure was applied to all the transistors of the circuit to improve the high frequency performance and output power of the generated impulse signal. Fig. 3.15. Measured and simulated impulse signals with tunable pulse duration.

54 The measured and calculated impulse signals with different durations are shown in Fig. 3.15 for a 50-Ω load condition, and are expectedly similar to the illustrated voltage waveforms at node C shown in Fig. 3.9. Impulse signals having 0.95 1.05 V peak-to-peak voltage with 100 300 ps tunable pulse duration were measured. The pulse duration is defined at 50% of the peak amplitude. The pulse width tunability is achieved by varying the gate control voltage V ctrl of the tunable delay cell within the range of 0 V to V dd. Fig. 3.15 also shows clearly that the generated impulse signals have a common rising edge, whose position is only determined by the falling edge of the square wave at node B; while the position of the falling edge of the generated impulses is determined by the rising edge of the square wave at node A and the tunable relative time offset between nodes A and B. It is noted that the measured waveforms are very symmetrical with almost no distortion. Good symmetry and low distortion are important for most pulse applications. As can be seen, the measured results are well matched to the simulated ones. Comparing to the previous work using TSMC 0.5-µm in [39], the tuning duration range with constant pulse amplitude improves a lot. It should note that the final impulse signal generated generally consists of three parts: rising edge, tunable relative time offset, and falling edge, as shown in node C of Fig. 3.9. For impulse with very narrow pulse width, only part of the rising and falling edges of the square waves are involved in the pulse forming, resulting in amplitude much smaller than those for wider pulses do. When the pulse width reaches a certain value, the full rising and falling edges of the square waves and tunable relative timeoffset part all contribute to the pulse generation, so the amplitude of the generated impulse signal does not change anymore, and different tuning relative time-offsets will only change the final pulse width. Consequently, there is not much difference in amplitude for different impulse signals if the pulse width exceeds the certain value. As for the situation where the impulse signal with minimum pulse width is desired, there is a compromise between the minimum pulse width and the signal amplitude, since the too narrow pulse will sacrifice too much pulse energy. Using a better technology such as 0.13-µm RFCMOS process would improve the tuning range of pulses with uniform

55 amplitude and the amplitude of the minimum width pulse, because the better process will achieve the much sharper rising/falling edges of the square wave, which means the pulse with much narrower minimum width. Hence the corresponding pulse tuning range with constant pulse amplitude is extended. To verify the frequency response performance of the generated impulse signals, the power spectral density (PSD) of the impulse signal was also measured using a spectrum analyzer which can cover the frequency of 9 KHz to GHz. Fig. 3.16 displays the measured PSD of the impulse signals with 100 ps and 300 ps pulse durations respectively. The measured results clearly show that, for impulse signals, major PSD components always concentrate on low-frequency range approximately to DC. Accordingly, the bandwidth of the impulse signal was changed simply by tuning the control voltage of the delay cell. For 100 ps impulse in Fig. 3.16(a), the first null frequency of the PSD appears at 8 GHz, while for 300 ps impulse in Fig. 3.16(b), the first null frequency is around 3.5 GHz. Therefore the above results verified the design of the tunable impulse generator module. The proposed tunable impulse generator can be used further to generate tunable monocycle pulses. -40-40 Power Density (dbm) -45-50 -55-60 Power Density (dbm) -45-50 -55-65 0 4 6 8 10 1 Frequency (GHz) -60 0 4 6 8 10 1 Frequency (GHz) (a) (b) Fig. 3.16. PSD of tunable impulse signal (a) 100 ps. (b) 300 ps.

56 400 350 300 Pulse Width (ps) 50 00 150 100 50 0 0.6 0.8 1 1. 1.4 1.6 1.8 Tuning Voltage (V) Fig. 3.17. Measured impulse width vs. tuning delay voltage. The relation of the impulse width to the tuning delay control voltage V ctrl of the tunable impulse generator is also investigated, and the result is presented in Fig. 3.17. For the tuning voltage below 0.6 V, the transistor M1 is actually off, hence functions as a very large resistor. The equivalent capacitor of the tunable delay cell therefore can be ignored, and the very short relative time-offset between two paths produced the impulse signal with very low amplitude that can not be used in UWB applications. When the tuning voltage was increased from 0.7 V to 1.1 V, the impulse width increased linearly from 45 ps to 90 ps, and the corresponding amplitude of the impulse signal increased from 0.4 V to 0.9 V. Further increasing the tuning voltage to 1.6 V only widened the impulse width from 90 ps to 340 ps, with the much faster width variation, but the amplitude of the impulse signal increased is very little, and can be considered as constant. That s because the transistor M1 entered into the saturation region, the value of the corresponding equivalent shunt capacitor does not change anymore. As shown in Fig. 3.16, from 1.6 V to 1.8 V, the impulse width variation is not much. For the

57 applications where the requirement is that the pulse width variation should be in proportional with tuning voltage variation, the shunt NMOS capacitor can be replaced by other components with extended linear tuning range to meet the requirement. Table 3.3. The size of NAND gate block. Transistor NMOS PMOS Width (µm) 80 40 Length (µm) 0.18 0.18 0. 0-0. 100 ps 00 ps 300 ps Voltage (V) -0.4-0.6-0.8-1 -1. -1.4 1 1.5.5 3 3.5 4 Time (ns) Fig. 3.18. Measured negative impulse signals with tunable pulse duration (NAND gate block). As mentioned-above, when NAND gate block is used as impulse-forming component in tunable impulse generator, the tunable impulse signal with negative amplitude can be generated. The corresponding separate tunable negative impulse

58 generator was also fabricated and tested following the same above-mentioned test conditions. Table 3.3 presents the parameters of the corresponding NAND gate block. Fig. 3.18 shows the measured results of the negative tunable pulse signals. As shown in Fig. 3.18, three impulse signals with pulse width of 100, 00, and 300 ps share the common falling edge, with the amplitude range from 1 V to 1. V. The negative impulse signals also maintain the good symmetric shape. Finally, the measured tunable monocycle pulse signals are shown in Fig. 3.19 for 50 Ω-load condition. By changing the gate control voltage V ctrl of the tunable delay cell in the range of 0 V to V dd, symmetric monocycle pulses with 0.7-0.75 V peak-to-peak voltage and 140 350 ps tunable pulse duration, at 50% of the peak amplitude, were measured, which are also similar to the pulse shapes at node D of Fig. 3.8. To verify the frequency response performance of the generated monocycle pulses, the PSD was also measured using a spectrum analyzer. Fig. 3.0 displays the measured PSD of the monocycle pulse with 140-ps pulse duration, showing that most of PSD is below -50 dbm over the 3.1 10.6 GHz band. 0.5 0.4 0.3 100 ps 00 ps 300 ps Voltage (V) 0. 0.1 0-0.1-0. -0.3-0.4 4.5 5 5.5 Time (ns) 6 6.5 Fig. 3.19. Tunable monocycle pulse generator.

59-45 Power Density (dbm) -50-55 -60-65 -70 0 4 6 8 10 1 Frequency (GHz) Fig. 3.0. Spectrum of tunable monocycle pulse signal. 3.3 BPSK Modulator Design For impulse-type UWB transmitter design, BPSK modulation normally was chosen to modulate a digital information data sequence to a pulse sequence [38], [50]. For the BPSK modulation, the polarities of the output pulse signals can be controlled by the polarities of the information data levels. BPSK has an advantage over pulse amplitude and position modulation due to the two times improvement in overall power efficiency [15], an inherent 3-dB increase in separation between constellation points. In this section, a simple level triggered pulse modulation circuit is developed to achieve the BPSK modulation, which is fully integrated with the tunable pulse generators proposed in above sections. The block diagram of the proposed pulse modulator is shown in Fig. 3.1, which includes two pulse generators and one switch. The input signal V in (t) of the pulse generators is a 10-MHz clock signal. The pulse generators can produce both positive and negative tunable pulse signals. The control input V ctl (t) to the BPSK modulator is the

60 information data sequence to be transmitted, and the level of this modulation signal will determine the polarities of the final output pulse signal V out (t). When the digital modulation signal is in low level, such as 0, the output signal of the BPSK modulator will be pulse signal with negative amplitude; while for digital information signal with high level of 1, the positive pulse signal will be generated at the output of the BPSK modulator. Positive pulse generator BPSK modulator V in (t) Negative pulse generator V out (t) V ctl (t) Fig. 3.1. BPSK diagram block. The proposed compact BPSK modulation circuit implemented in CMOS technology is shown in Fig. 3., which consists the components of R 1, R, C 1, C, M 1, M, and M 3. V inp is the input pulse signal with positive amplitude, and V inn is the input pulse signal with negative amplitude. V ctl is the input digital information data sequence to be transmitted, which can be low level 0 or high level 1. V out is the output signal of the BPSK modulator, which is loaded by the external 50-Ω resistor not shown in the circuit. NMOS transistors M 1, M, and M 3 together form the multiplixer, where M 1 and M are used as two transmission gates and biased by the complimentary control voltages controlled by M 3. Thus at one time only one input signal can pass

61 through the transmission gate M 1 or M, and feed to the 50-Ω load to generate the modulated positive or negative pulse. V dd R R 1 V ctl M 3 V inp V inn C 1 M 1 M C Vout Fig. 3.. BPSK modulation circuit. As shown in Fig. 3., when the modulating digital data is high level 1, the corresponding control signal V ctl is V dd, hence the gate voltage of both M 1 and M 3 is V dd. Therefore, transmission gate M 1 is in the on condition, and transistor M 3 is on in the saturation region. Hence the gate voltage of M is close to zero. This makes the transmission gate M in the off condition. So only the positive pulse signal V inp is passed to the output of BPSK modulator. For the digital data information of low level 0, the corresponding control signal V ctl is zero, hence the gate voltage of both M 1 and M 3 is zero. So transmission gate M 1 and M 3 are both off, and the gate voltage of

6 M is close to V dd, resulting the on condition of M, and the negative pulse signal V inn is generated at the output of BPSK modulator. For BPSK modulator, the transmission gates M 1 and M should drive 50-Ω load effectively. As larger transmission gate transistors mean smaller on-resistance [44], the transmission gates M 1 and M should be selected large enough to avoid amplitude degradation. Table 3.4 provides the parameters of corresponding NMOS transistors. Table 3.4. The size of transistors in BPSK modulator. Transistor M1 M M3 Width (µm) 160 160 0 Length (µm) 0.18 0.18 0.18 Fig. 3.3. Simulated insertion loss and isolation of BPSK modulator.

63 Fig. 3.3 and 3.4 present the simulated performance of BPSK modulator in frequency-domain and time-domain. 1.5 db insertion loss was achieved on the entire UWB band, while the isolation is below 0 db over most of the frequency range. As shown in Fig. 3.4, the output signals keep the same shape as the input pulses for both 1 and 0 conditions. Fig. 3.4. Simulated time-domain performance of BPSK modulator. 3.4 Tunable Transmitter Design In this section, the tunable impulse-type UWB transmitter front-ends, integrating the tunable pulse generator with BPSK modulator on a single CMOS chip, were presented based on the tunable impulse generator or monocycle pulse generator and BPSK modulator design described in previous sections.

64 Oscillator (PRF) Tunable Impulse Generator Inverter BPSK Modulator V ctl V out Fig. 3.5. Diagram block of tunable impulse generator with BPSK modulator. First, the tunable impulse generator integrated with BPSK modulator is presented in Fig. 3.5. The proposed UWB transmitter consists of the tunable impulse generator, CMOS inverter, and BPSK modulator. The tunable impulse generator driven by the 10- MHz input clock signal produces the impulse with tunable duration, which is divided equally into two paths: one impulse signal is directly sent to BPSK modulator, funcitoning as the positive impulse input signal V inp, as shown in Fig. 3.; another path signal goes through the CMOS inverter to the BPSK modulator to generate the negative pulse signal, therefore the impulse signal V inn with negative amplitude is fed to the modulator. Considering the extremely narrow rising and falling edges of the impulse signal, the CMOS inverter with large size was chosen to provide enough driving capability for the impulse, otherwise the generated negative impulse V inn at the output of CMOS inverter degrades the pulse width and amplitude performance. The output signal V out of the transmitter is determined by the external modulating signal V ctl to generate the tunable impulse signal with positive or negative amplitude. The layout of the impulse generator integrated with BPSK modulator is shown in Fig. 3.6, which is fabricated with Jazz 0.18µm RFCMOS technology. The overall size of the circuit is 580 µm 550 µm, including the RF pads and DC pads for on-wafer measurement purpose. The external modulating signal was fed to on-wafer pad of the circuit through DC probe. The measurement results of the output modulated impulse

65 signals are shown in Fig. 3.7 for different modulation signals, where V ctl = V dd is high level, and V ctl = 0 is low level. Fig. 3.6. Photograph of impulse generator with BPSK modulator. (a) (b) Fig. 3.7. Measured results of impulse transmitter. (a) High level, (b) low level.

66 Fig. 3.7(a) shows the positive tunable impulse signal with pulse width 100 ps and 300 ps for the condition of high level modulation signal. The pulse widths are comparable with simulated results, while the measured amplitude is somewhat lower than simulated one, which caused by extra parasitic resistance from interconnection lines that not fully included in the simulation. Comparing with the impulse signal in Fig. 3.15 generated by tunable impulse generator, the modulated impulse signals have the smaller amplitude of 0.8 V, and they still keep the symmetric shape and similar pulse width. As for the negative impulse signals shown in Fig. 3.7(b) for the condition of low level modulation signal, the amplitude is reduced to 0.7 V, with some distortion at the top of the pulse waveform at the bottom pulse peak position. The reason is that the input negative impulse to the modulator is produced by the CMOS inverter, which in practice attenuates the pulse amplitude, and expands the pulse width to some extent. The alterative way is to replace the CMOS inverter generated negative impulse with the NAND gate block based negative impulse generator, which will provide the good negative impulse signal as shown in Fig. 3.18, with large enough amplitude to the BPSK modulator. Of course the consumed power also increased accordingly. Oscillator (PRF) Tunable Impulse Generator Inverter BPSK Modulator V ctl V out Fig. 3.8 Monocycle pulse generator with BPSK modulator. For the tunable monocycle pulse generator integrated with BPSK modulator, there are two configurations that can be used for circuit realization. One setup is to put the BPSK modulator succeeding two monocycle pulse generators that can generate positive or negative monocycle pulse signals (here the positive monocycle pulse is

67 defined as the monocycle pulse with left positive peak and right negative peak, while the negative monocycle pulse is the signal with left negative peak and right positive peak.), which seems a straightforward way to produce the modulated monocycle pulse signal. However, two monocycle pulse generators occupy too much die space, and power consumption of double monocycle pulse generators is another concerning issue. The other topology of monocycle UWB transmitter is to succeed the previous designed impulse transmitter with pulse-shaping module. So the modulated impulse signal with positive or negative amplitude was shaped to the modulated monocycle pulse signal with positive or negative amplitude. Since only one pulse-shape component is used comparing with the first topology, the occupied die area of the circuit reduced a lot. Hence the second configuration is selected and the final structure of the monocycle BPSK transmitter is shown in Fig. 3.8. The monocycle UWB transmitter consists of the tunable impulse generator, CMOS inverter, BPSK modulator, and pulse-shaping component. 10-MHz clock signal drives the tunable impulse generator to produce the impulse with tunable duration. Positive impulse signal directly from the tunable impulse generator and negative impulse signal from CMOS inverter were fed to BPSK modulator. Depending on the high or low external modulating signal V ctl, the positive (high level modulation) or negative (low level modulation) modulated impulse output of BPSK modulator was sent to pulseshaping circuit. Finally the modulated positive or negative monocycle pulse signal was generated at the output of the pulse-shaping circuit. The photograph of the final monocycle transmitter with BPSK modulator is shown in Fig. 3.9, which is fabricated with Jazz 0.18µm RFCMOS technology [47]. The overall size of the circuit is 60 µm 550 µm, including the RF pads and DC pads. The measurement results of the output modulated monocycle pulse signals are shown in Fig. 3.30 for different modulation signals where V ctl = V dd is high level, and V ctl = 0 is low level.

68 Fig. 3.9. Photograph of monocycle pulse generator with BPSK modulator. Fig. 3.30. Measured results of monocycle pulse transmitter. (a) High level, (b) low level. As shown in Fig. 3.30, the modulated monocycle pulse signals with pulse width of 100 ps and 300 ps have the peak-to-peak amplitude of 0.6-0.8 V, and the symmetry

69 of the signal shape is somewhat degraded compared with simulation results while the pulse widths keep the same. The unsymmetrical problem is caused by BPF succeeding the BPSK modulator.

70 CHAPTER IV UWB RECEIVER DESIGN The function of impulse-type UWB receiver is to receive the transmitted UWB pulse signal through the receiving antenna and down-convert this input signal to the baseband signal. Since the received pulse signal covers such a wideband, the design of the impulse-type receiver that can down-convert the input signal and recover the downconverted signal waveform in the same form as the RF input signal would be the challenging work. As shown in chapter II, the architecture of the impulse-type UWB receiver is much simpler than conventional narrow-band system and MB-OFDM UWB receivers. It only consists of the UWB LNA, down-conversion mixer (or in other term, correlator), template pulse generator, and other accessory circuits. Among these components, UWB LNA and correlator are two essential circuits. The specifications of LNA and correlator directly determine the final performance of the UWB receiver. In impulse-type UWB systems, not matter what kind of modulation technique used, the corresponding correlator and LNA with minimum NF are always indispensable components for detection of the receiver. For wireless mobile devices, to reduce the cost and power consumption, it is necessary to integrate all the UWB components on a single chip. Considering the UWB frequency range involved from 3.1 GHz to 10.6 GHz, this requirement represents a big challenge for current VLSI technology. In this chapter, impulse-type UWB receiver based on RFCMOS technology was investigated, with the focus on the module of LNA and correlator. Furthermore, the structure-optimized and patterned-ground-shield (PGS) inductors were also studied to replace the low-q inductor model provided in foundry library. First, the individual UWB LNA and correlator circuits employing optimized PGS inductors were designed and implemented to verify the design topology. Then the integrated CMOS UWB receiver front-end including UWB LNA, correlator, and template pulse generator was presented.

71 4.1 UWB LNA 4.1.1 LNA Design A wideband LNA operating over the whole UWB band of 3.1 to 10.6 GHz is definitely an essential component in both MB-OFDM and impulse-type UWB receivers. This amplifier should exhibit the performance of wideband input matching to the 50-Ω antenna, flat gain, good linearity, minimum possible noise figure (NF) over the entire bandwidth and low power consumption. For wireless communications systems, the first step of LNA design is to select the transistors with fast speed and low-noise features. Traditional wideband amplifiers employ the composite semiconductor such as GaAs transistors because of the intrinsic superior frequency characteristics; while silicon technology is used to design and implement amplifiers with less strict requirements, such as narrow-band systems operating in lower frequency band, where smaller gain and larger parasitic effects are acceptable. With the rapid development of technology scaling and advances of more accurate RF models, CMOS is quickly becoming the preferred choice for RFIC s, and more and more high-frequency wideband amplifiers employ the silicon transistors. In this section, an individual LNA was designed and implemented over the UWB band with Jazz 0.18- µm RFCMOS process. To facilitate the measurement, the output buffer was also included to drive the external 50-Ω load. Lately, the LNA core without the buffer will further integrate with UWB correlator to form the essential module of the impulse-type UWB receiver. There are many different options for the high-frequency wideband amplifiers design depending on the requirements and applications. Typical methods include classic shunt feedback amplifier, distributed amplifier, the cascaded common-source (CS), or common-gate (CG) circuit topologies, as shown in Fig. 4.1 [51]. First, the advantages and disadvantages of these topologies are briefly described concerning the power consumption, die area, and noise figure, which will facilitate our UWB LNA topology selection and design.

7 V dd Vdd V dd V dd R L Z 0 R L R L V in R F R S V out......... V out V g V in V out I source V in V g V out V in Z0 L s (a) (b) (c) (d) Fig. 4.1 Various wideband LNA topologies. (a) Shunt feedback. (b) Distributed amplifier. (c) Common-gate. (d) Cascoded common-source. Shunt Feedback LNAs For the shunt feedback amplifiers, the negative feedback achieves the simultaneous impedance match at both input and output ports, and produce the relative constancy of input and output impedances over a broad frequency range [51]. However, as shown in Fig. 4.1(a), inherent larger C gs of CMOS transistor results the larger parasitic input capacitance, which means the limited input impedance match bandwidth at higher frequencies [5]. Furthermore, the resistive feedback network generates its own thermal noise and the overall noise figure of the amplifier generally exceeds the device F min by a considerable amount [51]. Therefore, the shunt feedback structure cannot provide sufficiently low NF and high gain while consuming low power, which is the important specification in UWB LNA design. Distributed LNAs In contrast with typical amplifier cascades, the overall gain of the distributed amplifier depends linearly on the stage numbers; hence the distributed amplifier can operate at substantially higher frequencies and achieve ultra wideband performance. However, the cost of the power consumption is several times higher than in a singlestage amplifier. As shown in Fig. 4.1(b), the number of inductors used in the structure

73 results the large die area usage, which also makes this type of amplifier less attractive to UWB applications. Common-gate LNAs The common-gate amplifier seems to be the good choice for UWB radio in terms of power dissipation and die area. As shown in Fig. 4.1(c), the wideband input match can be achieved simply by proper selecting device size and adjusting the bias current such that 1 of the amplifying transistor is nearly 50 Ω over the broad frequency range g m [51], and no area-intensive, LC input matching network is needed. However, the lower bound of noise figure for CG amplifier is about 3 db [51], and will be even worse at high frequencies and when gate current noise is taken into account. Hence the presence of noisy resistances in the signal path such as channel resistance results in noise figure degradation [51], and limits the minimum possible noise figure, which is an adverse effect in UWB system. Cascoded Common-source LNAs The cascoded CS topology, shown in Fig. 4.1(d), is often used in wideband LNA design for the ease of achieving a low noise figure and a high gain. The structure is based on a narrowband inductively degenerated cascoded LNA that is extended to large bandwidths by including the band pass filter (BPF) at the input, where the reactive part of the input impedance is resonated over the BPF frequency range [5]. The main feature of this topology is the ability to match the NF close to NF min while also achieving power match. These characteristics make the cascoded CS topology the preferred option for UWB LNA design. The disadvantage is that the wideband LC matching network contains multiple on-chip spiral inductors, which occupies much die area.

74 V dd L L R L V dd V out Z IN M R S C 1 L 1 L G M 1 V in L C C P L S Z IN L C R Fig. 4.. Ladder matched UWB LNA. Comparing the above-mentioned several wideband LNA topologies in terms of noise figure, power dissipation, and die area, the cascoded common-source inductively degenerated LNA, with extended ultra-wideband ladder matching network, was selected to form the impulse-type UWB LNA. As shown in Fig. 4., the structure is based on the narrow-band cascoded inductively degenerated common-source LNA [51]. The cascoded configuration of transistors M 1 and M reduces the Miller-effect and improves the input-output reverse isolation as well as frequency response. Because of the reverse isolation achieved by cascoded structure, the effects of M, R L, and L L to the input impedance can be negligible. The input impedance of the NMOS transistor M 1

75 with inductive source degeneration shown in Fig. 4. is equivalent to the impedance of a series RLC circuit, and R is given by [51] R = ω T L S (4.1) ω = g / C + C = g / C is the cut-off frequency of the transistor. To make where T m ( gs P ) m T the UWB LNA design more flexible, an on-chip spiral inductor L G is placed in series with the gate of M 1, and external MIM capacitor M 1. written as [5] C P is placed in parallel with C gs of Hence the input impedance of M 1 with inductive source degeneration can be Z IN = jω 1 ( C + C ) gs P + jω ( LS + LG ) + ωt LS (4.) where the real part of Z IN is chosen to be equal to the source resistance of R S, and the reactive part of the input impedance is resonated at the operating frequency with nearly optimal NF [51]. The bandwidth of the narrowband inductively degenerated cascoded LNA is extended by adding the series inductor-capacitor ( L 1, C 1) and parallel inductor-capacitor ( L, C ) to match the topology of a third-order Chebyshev bandpass filter, as shown in Fig. 4.3, where R is the load of 50-Ω. Since the reactive elements of the filter, i.e., L 1, C 1, L, C, L, and C determines the bandwidth and ripple of the passband, assume 0 db power loss in the passband with ripple of ρ P, the input reflection coefficient can be written as [5]

76 1 Γ = 1 (4.3) ρ P Z FILT R S C 1 L 1 L C L C R = 50 Ω Fig. 4.3. Third-order Chebyshev bandpass filter. In the passband of the Chebyshev BPF, if the input reflection coefficient is smaller than -10 db, the tolerable ripple of less than 0.5 db can be derived from (4.3). For the impulse-type UWB applications, assuming the filter passband of 3.1 10.6 GHz, the three-section Chebysheve BPF structure was selected considering the compromise between filter complexity and component values. The module Filter Design Guide of ADS [48] was employed as the simulation tool to quickly derive the initial ideal component parameters of the three-section Chebyshev bandpass filter for 50-Ω input and output matching, which is shown in Fig. 4.3. The component values of the three-section Chebyshev BPF are presented in Table 4.1, where = L G LS, and C C gs + CP L + =. The simulated return loss and insertion loss of the three-section Chebyshev BPF are shown in Fig. 4.4, which cover the UWB band of 3.1 10.6 GHz. The components of three-section Chebyshev BPF will later be replaced with on-chip MIM capacitors and EM-optimized spiral inductors to achieve the fully integrated LNA structure.

77 Table 4.1. Component values of third-order Chebyshev BPF. L 1 (nh) 1 C (pf) L (nh) C (pf) L (nh) C (ph) 1.65 0.47 1.64 0.47 1.65 0.47 0-5 -10 Return Loss Insertion Loss Amplitude (db) -15-0 -5-30 -35-40 4 6 8 10 1 Frequency (GHz) Fig. 4.4. Performance of three-section Chebyshev bandpass filter. As shown in Fig. 4., in order to achieve the flat gain over the whole UWB band, the shunt-peaking topology was employed, which include the series inductor resistor R L as the load [51]. The value of L L and L L should be large enough to provide the large gain at the higher frequency edge, and in the meantime, it must be small so that the resonating frequency generated by L L and C OUT is much higher than the operating frequency band, where C OUT is the total capacitance between the drain of M and ground [5]. As for R L, the zero frequency ω Z = R L / LL should be close to the lower frequency edge of the band to improve the gain at the lower frequencies. R L is limited

78 by an upper value above which the voltage drop is such large that reduces the voltage V dd supplied to the drain of M. Next step is to analyze the voltage gain of UWB LNA over the whole frequency band. First assume the input network of the LNA, i.e. the Chebyshev BPF filter, has the transfer function that is approximately unity in the passband, therefore the input impedance can be considered as R S over the passband, as shown in Fig. 4.. Hence the current to amplifying transistor M 1 is i = v / R. In addition, the CMOS transistor in in S functions as the current amplifier at the high frequency, with the current gain of β = g m /( jωct ) [51]. expressed as: Considering the shunt-peaking load of R L and L L, the overall output load can be Z LOAD 1 RL + jωll = ( RL + jωll ) jωc = (4.4) OUT 1+ jωcout ( RL + jωll ) Using (4.4) and current gain expression β = g m /( jωct ), the overall voltage gain of the amplifier can be written as [5]: v v out in Z LOAD g m RL + jωll = β = (4.5) R jωc R + jωc ( R + jωl ) S T S 1 OUT L L Above equation clearly shows that, at lower frequencies, R L plays an important role in voltage gain determination; while at higher frequencies, the current gain roll-off is compensated by load inductor C OUT with L L has to be kept out from the passband. L L. Furthermore, the spurious resonance introduced by For calculation of the noise performance of LNA, normally two major noise contributors should be considered: the losses associated with the input network and the

79 noise generated by amplifying component M 1. For the input network, as shown in Fig. 4.3, the MIM capacitors have the much higher quality factor than those of the on-chip spiral inductors. Hence the noise contribution of the three-section Chebyshev BPF is mainly due to the limited quality factor of the on-chip spiral inductors. To reduce this part of noise, the structure of the inductors should be optimized with EM simulation and PGS topology, to achieve the highest Q for the specific inductance value. The detailed design topology and final inductor parameters of input network will be presented in next section. As for the noise contribution from M 1, for specific bias current, the corresponding transistor width should be selected in order to achieve the optimum noise value. Considering the ultra wideband feature in our case, the noise performance of the amplifier over the whole UWB band should be studied. Hence both minimum NF and average in-band NF should be investigated in order to achieve the optimum noise performance. During the noise analysis, typical two-port system topology was followed represented by input-referred noise current and voltage source. Also, 1 / f noise will be ignored because of the amplifier s high operating frequency. Shown in Fig. 4.5(a) is the MOS transistor noise sources including the loading effect of the local feedback inductor L S. ing is the induced gate noise due to the coupling of the fluctuating channel charge into the gate terminal, while i nd is the drain noise current due to the carrier thermal agitation in the channel. The corresponding induced gate noise and drain current noise are expressed respectively as [51]: i ng Δf = 4kTδg g (4.6) i nd Δf = 4kTγg d 0 (4.7)

80 where k is Boltzmann s constant, T is the absolute temperature in degrees Kelvin, g g ω C gs =, δ = 1.33 4 and γ = 0.67 1. 33 are excess noise parameters, and g d 0 is g 5 d 0 the channel conductance at V = 0 [51]. DS M 1 v n M 1 i ng C P i nd i n C P L S L S (a) (b) Fig. 4.5. Noise model for transistor M 1. (a) M 1 noise sources. (b) Input-referred equivalent noise generators. Employing the conventional input-referred topology in [51], the noise sources of M 1 were replaced with two correlated noise generators of i n and v n, which are shown in Fig. 4.5(b) [5]. As seen in Fig. 4.5(b), when the input is short-ended, only noise generator i n exists. As the transistor can be considered as current amplifier [51], for noise source i nd, assume the input-referred noise current is i nd,input, we have the following relation between them [51]:

81 i nd Δf = g m jωc T i nd, input Δf (4.8a) where have 1 / jωc is the output impedance caused by output parasitic capacitor, hence we T i nd, input Δf = jωc g m T i nd Δf (4.8b) Therefore the total noise current generator i n can be derived from above formula as: i n Δf = i ng Δf i + nd, input Δf = i ng Δf + jωc g m T i nd Δf (4.8c) As shown in Fig. 4.5(b), when the input is open-ended, the noise generator v n can be expressed as: v n Δf = v n,1 Δf + v n, Δf (4.9a) where v n,1 is the input-referred noise from transistor M 1, and i n. The corresponding equations are: v n, is from L S caused by v n,1 Δf = g m i nd Δf (4.9b)

8 and v n, Δf = jωl S i n Δf (4.9c) From (4.9a) to (4.9c), the equivalent noise voltage generator is: v n Δf = g m i nd Δf + in jω LS (4.9d) Δf Normally, the input-referred noise voltage source the input-referred noise current source i n. Hence v n is partially correlated with v n can be expressed as the sum of two components, one fully correlated, v n,c, and the other, v n,u, uncorrelated to the noise current source i n as follows: vn Δf vn, c = Δf vn, u + Δf (4.10) and the corresponding correlation impedance Z c can be expressed as [5]: Z c vn, c 1 1+ c pαχ = = jωls + (4.11) i jωc 1 c pαχ ( pαχ ) T + + n where [5]

83 * ingind c = j0.395 (4.1a) i i ng nd C gs p = (4.1b) C T δ χ = (4.1c) 5γ g = g m α (4.1d) d 0 In the above formula, c is the noise correlation coefficient between the gate noise and the drain noise; α represents the short-channel effects and was used to estimate the transconductance reduction due to the velocity saturation and mobility decrease for vertical fields. The other two important parameters in NF calculation are the uncorrelated noise sources i n and v n,u, and the corresponding equivalent noise resistance or conductance can be expressed in the following formula respectively [5]. G in = Δf γ (4.13) ( ) ( ωc ) 1+ c pαχ ( pαχ ) n = T + 4KT α g d 0 R u v n, u ( pαχ ) ( 1 c ) Δf γ = = (4.14) KT ( p ) 4 α g d 0 1+ c pαχ + αχ

84 Following the conventional two-port system noise analysis, the NF of the LNA can be written in terms of these parameters [51]: F Ru + Z c + Z S Gn = 1+ (4.15) R S where Z = R + jx is the source impedance. S S S When the source impedance was selected as minimum NF can be realized, and the corresponding Z = Z = R + jx, the S opt opt opt Z opt can be expressed in the following manner [51] R opt ( pαχ ) 1 c ( 1+ c pαχ + ( pαχ ) ) Ru = + Rc = (4.16a) G ωc n T and X opt 1 1+ c pαχ = X c = ωls + (4.16b) ωc 1+ c pαχ + T ( pαχ ) From (4.1), c = 0. 395, p < 1, α 1, and χ < 1, therefore the coefficient of 1 ωc T in (4.16b) is close to one, hence the optimum source impedance can be roughly achieved if the series combination of C T and L S can be resonated over the interested frequency band [5]. With the help of three-section Chebyshev BPF input network, the overall input reactance looking into the filter is resonated over a wide bandwidth, so = 0 is generated over the wide bandwidth, hence quasi-minimum NF can be realized X opt

85 over the entire LNA bandwidth, and the corresponding NF can be simplified from (4.15) as [5]: R 1 GnRS (4.17) R u F + + S With the help of above derived equivalent noise parameters, the final expression of NF can be derived by inserting (4.13)-(4.16) into (4.17) as: F ( pαχ ) ( 1 c ) γ 1+ + T S αχ αg mrs 1+ c pαχ + ( pαχ ) ( ) ( ωc R ) 1+ c pαχ + ( p ) (4.18) For CMOS transistor, the transconductance g m can be derived from the following saturation drain current equation that is applicable for both long and short channel devices [51]: ( V V )( [ V V )( LE )] μ ncox W ρ I D = gs t gs t sat = WLCoxvsat Esat (4.19) L 1+ ρ where E sat is the filed strength at which the carrier velocity has dropped to half the value extrapolated from low-field mobility, V t is the threshold voltage, and μ =, n v sat Esat V gs t od ρ = = (4.0) LE V sat V LE sat Hence the transconductance is obtained from (4.19) as:

86 g m I D 1+ ρ / W W = μ ncox Vod = α μ ncox Vod = αg d 0 V L L (4.1) gs ( 1+ ρ) From (4.1), p < 1, α 1, and χ < 1. From (4.18), the larger transconductance will produce the better noise performance. Also, as shown in (4.1), for the fixed smaller size transistor results bigger α, hence the better NF is achieved. From W g m = μ ncox I D [51], for fixed g m, smaller transistor means larger L larger bias current is preferred for NF performance. g m, I D, therefore During the noise analysis for transistor M 1, the average NF value over the entire operating frequency band is also an important parameter to evaluate because of the ultra wideband of LNA. Hence for the specific bias current I bias, there is an range for the width of the amplifying transistor M 1 that can be chosen to achieve the minimum average NF. Therefore, in the UWB LNA design, as long as the noise performance is mainly limited by the contribution of M 1, which is the case as cascoded topology is used [5], the better noise performance of the system can be achieved if the larger bias current is applied, as shown in (4.18). In the proposed LNA design, the bias current I bias = 5 ma is assumed, and the minimum length of 0.18 µm was selected for both transistors M 1 and M. Considering the balance between the thermal drain noise and induced gate noise, the size of the amplifying transistor M 1 was selected as 60 µm using (4.18). While for the cascoded transistor M, in order to reduce the parasitic capacitances, the smaller size is preferred, on the other hand, a lower limit to the width of M is set by its noise contribution because the smaller size transistor produces the higher noise [5]. And the final width of 60 µm is selected for M. As the on-chip spiral inductor model in Jazz 0.18µm CMOS design kit only provides the rectangular structure with low quality factor, which is not suitable for the

87 UWB LNA application, it is necessary to generate the integrated spiral inductors with optimized Q and inductor value over the operating band to replace the low Q inductor model. Hence electromagnetic simulation was performed based on the multiple-layer CMOS structure, and this part of inductor optimization work was described in next section. On the above circuit analysis, the gate-drain capacitance of M 1 C gd was first omitted for the analysis simplicity. However, at the high frequency, the presence of C gd complicates the input impedance Z IN and make it differ from the simple series RLC model assumed. During schematic simulation, C gd is included, so the values of on-chip components were optimized through the circuit simulation, and the finalized component parameters are presented in Table 4.. Table 4.. Final component values of LNA. L 1 (nh) C 1 (pf) L (nh) C (pf) L G (nh) C P (pf) L S (nh) L L (nh) R L (Ω) 1.08 0.65 1.63 0.45 1.3 0.06 0.61.65 85 V dd V out M 3 V dd I 0 V' out Fig. 4.6. Source-follower buffer for UWB LNA.

88 For the UWB LNA, to facilitate the on-wafer measurement, the typical sourcefollower buffer was also included to drive the external 50-Ω load, which is shown in Fig. 4.6, where 50-Ω load is connected to the source of M3. The buffer consists of transistor M 3 and current mirror to provide the independent biased current source of 5 ma. The parameters (length and width) of the two transistors in current mirror were optimized to produce the higher output impedance. The size of M 3 was selected as 60 µm to achieve the transconductance of g 1/ R 1/ 50 S. As the output voltage of the buffer is m3 = ext = only half of that produced by LNA without buffer, the gain of the final LNA structure with buffer is 6 db lower than that of the LNA core. The performance of the designed UWB LNA was presented in section 4.1.3. 4.1. Inductor Optimization To meet the various requirements for today s consumer and military communication systems, integrated spiral inductors with compact structure, high Q, and high self-resonant frequencies are highly desired. However, for silicon-based RFIC s, the quality factor of the inductor degrades at high frequencies because of the energy dissipation in the silicon substrate. Hence inductor design becomes a major bottleneck for the RF CMOS design. The typical structures of the spiral inductors on CMOS can be square, octagonal, or circular shapes. Some inductors have tapered width as a function of the particular turn. Furthermore, the structure can be single metal layer, parallel multiple metal layer and serial multiple metal layers. Among them, the single-layer square spiral inductor is most commonly used because of its area efficiency and drawing easiness, just like the case of Jazz 0.18 µm RFCMOS Design Kit [47]. Unfortunately, the quality factor for the square inductor is not the optimal compared with other geometries. Another problem is that the noise coupling from the silicon substrate is potentially big due to the large occupied die size. Therefore, selecting optimal structure and decoupling the inductor from the substrate will enhance the overall performance of the spiral inductor. Based on above consideration, the octagonal-shape inductors with patterned ground shield were

89 designed to replace the Design Kit model. This topology is fully compatible with standard CMOS technology and has the advantage of increasing Q and improving isolation. C 1 R S L Port 1 Port C P C P C sb R sb R sb C sb Fig. 4.7. Inductor π-model. The typical electrical model of an inductor on silicon is shown in Fig. 4.7, which is usually being called inductor π-model. The physical elements of this two-port network consist of C 1, R S, L, C P, R sb, and C sb [51]. The series feedforward capacitance C 1 represents the capacitance due to the overlaps between the spiral and the center-tap underpass, and its value is determined by the space between two metal sections. R S is the resistance from metal trace and its value is controlled by the sheet resistance and the length/width ratio of the metal traces. This resistance is due to the energy losses of the skin effect in the spiral interconnect structure, as well as the induced eddy current in any conductance media close to the inductor. C P represents the parasitic

90 oxide capacitance between inductor and silicon substrate. R sb and C sb stand for the substrate parasitic resistance and capacitance loss, respectively. Since the resistance in the inductor metal traces causes the primary energy loss, reducing the resistance of the conductors R S increases the Q of the inductor. The same approach can be applied to reduce the substrate loss due to magnetic coupling and electrical coupling to increase the quality factor. To reduce the resistance, a wider metal trace is usually used. Multi-layer metals can also be used to reduce the inductor area or increase the inductance per area. However, the disadvantage of multi-layer is the parasitic capacitance between each layer that tends to reduce the self-resonant frequency [51]. From Fig. 4.7, it can be seen that the inductor s parasitic effects of the substrate are a very important factor for inductor performance. To reduce the parasitic uncertainty, a ground shield between inductor and substrate can be considered. For the solid ground shield condition, the inductor s magnetic field was disturbed and induced the eddy current in the solid ground shield, which flowed in the opposite direction of the current in the spiral. This negative mutual coupling results the reduced inductance, which makes it not a good choice. To increase the resistance to the eddy current, the patterned ground shield with slots orthogonal to the spiral was introduced, therefore the eddy current loss is reduced. The corresponding structure is shown in Fig. 4.8, where the slots act as an open circuit to cut off the path of the induced eddy current [53]. To effectively cut the eddy current, the slots should be narrow enough so that the vertical electric field cannot penetrate through the patterned ground shield into the underlying silicon substrate. To prevent negative mutual coupling, the ground ring under the spiral inductor was intentionally broken into several sections, to reduce the current loop effects [53]. To minimize the impedance to ground, the ground ring should be grounded to the true ground as close as possible [53].

91 Fig. 4.8 Layout of patterned ground shield inductor Based on the Jazz 0.18 µm RFCMOS process, the top metal layer M6 with the thickness of.81 µm was selected to construct the octagonal spiral inductors. Comparing with other five metal layers (0.57 µm), the corresponding resistance in the inductor metal traces is much smaller. The Metal layer M1 was selected to form the patterned ground shield, which has the structure as shown in Fig. 4.8. EM software Zeland IE3D [9] was used to optimize the parameters of the top layer spiral inductors as well as the patterned ground plane, to achieve the desired quality factor and the inductance value over the operating frequency band. The spiral inductors of the designed LNA, i.e., L 1, L, L G, L S, and L L, were optimized using the above design topology. They were also fabricated separately on the same LNA chip for the design verification. To measure the S parameters of the inductors, calibration components including interconnect and pad metals were fabricated and open and short patterns were measured on the same wafer to de-embed the pad effect. Two-port S parameters were measured on the fabricated inductors using the

9 HP8510C network analyzer and RF probe station over the frequency range of 1 GHz. The parameter extraction was performed by IE3D with the de-embedded S parameters to generate the measured Q and inductance values over the entire frequency band. All five optimized inductors of LNA were measured. To make the context concise, here only the measured and simulated results for the designed spiral inductor L 1 are presented in Fig. 4.9. For the quality factor, the maximum value appears around 6 GHz, and Q is larger than 10 over the whole UWB band as shown in Fig. 4.9(a). From Fig. 4.9(b), it is clear that the inductance is almost independent to the frequency variations. Comparing to the inductor model in design kit with same inductance value, Q of the optimized spiral inductor has the obvious improvement. The better Q of the spiral inductor indicates the improved NF for the final LNA, therefore enhance the LNA performance. 0 Measured Simulation Measured Simulation 15 1.5 Q 10 L (nh) 1 5 0.5 0 4 6 8 10 1 Frequency (GHz) (a) 0 4 6 8 10 1 Frequency (GHz) (b) Fig. 4.9 Performance of the patterned ground shield inductor 1 L. (a) Quality factor Q. (b) Inductance L.

93 Fig. 4.10. Photograph of LNA chip. 4.1.3 LNA Fabrication and Test The picture of the designed LNA fabricated in Jazz 0.18-µm RFCMOS process is shown in Fig. 4.10, with the overall size of 0.88 mm 0.7 mm, including the corresponding on-wafer RF and DC-bias pads. All the measurements are performed on wafer. First, S parameters of LNA were measured over the operating frequency band. Fig. 4.11 shows the measured and simulated return loss of input port, which agrees each other reasonably well. The bandwidth of.9 1 GHz where the return loss is below -10 db was achieved, which validated the input matching network design.

94 0-5 Measured Simulation Return Loss (db) -10-15 -0-5 -30-35 -40 4 6 8 10 1 Frequency (GHz) Fig. 4.11. Return loss of input port for LNA. 0-5 Measured Simulation Return Loss (db) -10-15 -0-5 -30 4 6 8 10 1 Frequency (GHz) Fig. 4.1. Return loss of output port for LNA.

95 Fig. 4.1 presents the measured and simulated return loss of output port, and they match very close. The bandwidth of 1 GHz where the return loss is below -10 db was achieved, which validated the output buffer design. -30-35 Measured Simulation Isolation (db) -40-45 -50-55 -60 4 6 8 10 1 Frequency (GHz) Fig. 4.13. Reverse isolation of LNA. For the reverse isolation of LNA, the measured and simulated results are shown in Fig. 4.13 and they are very close. Over the frequency band, -40 db isolation was achieved, which proved the effectiveness of the cascoded LNA structure. Fig. 4.14 presents the gain performance of the LNA including buffer stage. The maximum gain of 1.4 db was achieved over the band. For the 3-dB bandwidth,.6 9.8 GHz with the minimum gain of 9.4 db was achieved with the help of shunt-peaking topology. Furthermore, the ripple of the power gain is very small over the whole band. The difference between the measured and simulated results at the high-frequency end is caused by extra parasitic capacitance from output buffer, which was not fully considered

96 during the simulation, hence only partially compensated by the shunt-peaked inductor load. 0 15 Measured Simulation Gain (db) 10 5 0-5 -10-15 -0 4 6 8 10 1 Frequency (GHz) Fig. 4.14. Power gain of LNA with buffer. Another important parameter for UWB LNA design is phase linearity of S 1 over the operating frequency band, which is shown in Fig. 4.15. It indicates that the phase performance with good linearity was achieved over the entire UWB band, and matched with simulation result, which will help to generate the pulse signal with less distortion at the LNA output.

97 300 00 Measured Simulation Phase (degree) 100 0-100 -00-300 4 6 8 10 1 Frequency (GHz) Fig. 4.15. Phase performance of S 1 for LNA. Amplitude (V) 0. 0.15 0.1 0.05 0-0.05-0.1-0.15 Input Output (Simulation) Output (Measured) -0. 0 1 3 4 5 6 Time (ns) Fig. 4.16. Measured LNA performance in time-domain.

98 To verify the UWB LNA performance in time-domain, on-wafer time-domain measurement was also performed with the digitalized oscilloscope, and the results are shown in Fig. 4.16. The input signal is the monocycle pulse, with the 3 db pulse width of 150 ps and peak-to-peak amplitude of nearly 0.1 V, generated by the commercial pulse generator. The output signal has the peak-to-peak voltage of 0.3 V, with the almost symmetric pulse shape and relatively small ripple. Compared to simulated result, there is some pulse-width expansion because of the gain roll-off at high frequency part. Fig. 4.17 shows the noise performance over the entire UWB band, the measured values follow the simulated one. The measured minimum NF is 4 db at the frequency of 5. GHz, while the average NF over the entire UWB band is around 5.8 db. 11 10 9 8 NF (db) 7 6 5 4 Simulation Measured 3 4 6 8 Frequency (GHz) 10 1 Fig. 4.17. Noise performance for LNA.

99 To make the designed LNA robust, the package topology should be selected to replace the on-chip structure for the future work, which means the parasitic effects caused by package should be included in the input matching network design [54]. Therefore the parasitic inductance of the input pin and corresponding bonding wires can be absorbed into the component of L 1, while the parasitic values of power-supply pin and bonding wires of package can be taken account into the shunt-peaked components of L L and R L. Fig. 4.18. Correlator in UWB receiver. 4. UWB Correlator Design Comparing to the traditional narrow band receiver, the complexity of the UWB receiver front-end has been greatly reduced. In a simplest topology, the receiver frontend is only composed of a wideband LNA, a wideband correlator, and a high frequency analog-to-digital converter (ADC) [55]. The basic function of the correlator is to convert the received RF signal from LNA to baseband for detection. The correlator normally consists of a multiplier followed by an integrator, as shown in Fig. 4.18. The two inputs

100 to the correlator, or the multiplier, are the input monocycle pulse signal from LNA and its template signal generated on the chip. The received monocycle pulse signal is correlated with the local template monocycle pulse during a certain period, normally the pulse repetition period or several pulse periods used for one symbol and its output is sampled and held to detect whether there is a signal in the observing window. In theory, the correlator can be implemented either in analog or digital format. However, for digital format, although a correlator can be realized for high data rates of up to 100 Mbps at high bandwidth, direct sampling of 3.1 10.6 GHz frequency signals is ultimately required, which is almost impossible for current ADC techniques. Furthermore, the digital correlator normally consumes more power and is lower in efficiency when compared with its analog counterpart. Considering above factors, analog correlator is the preferred choice. For the analog correlator, the advantage is that it can process signals in real time and provide a continuous output at low frequency, and thereby can remove the need for special requirements for the ADC in the receiver [56]. Analog correlators are therefore well suited for UWB front-end implementation, where the analog multiplier is required to have a good linearity for low distortion. As the correlator is used to detect the signal presence with known waveform in a noisy background, the output will be zero for noise only condition []. For the correlated input sigal, it is integrated with local template signal over the pulse duration and achieve the certain output voltage. The cross-correlation function can be expressed as: f = t = t t = t 0 0 + T RF( t) LO( t) dt (4.) where LO (t) is the local template signal, RF (t) is the input RF signal of the correlator, and T is the integration period. In UWB receiver design, the multiplier is required to have wide bandwidth up to 10.6 GHz, which assures the output waveform preserve the input pulse shape. This brings the great challenge to the design of CMOS analog multipliers. Currently, most of

101 the published CMOS analog multipliers can only operating at low frequencies [57]-[60]. Although some works on UWB mixer design can achieve very broad bandwidth [61]- [6], the information of the time-domain performance is not provided, while this specification is the important consideration in impulse-type UWB receiver design. In this section, an ultra wideband four quadrant multiplier is introduced, which can be used for the correlator of UWB receiver. 4..1 DC Analysis The schematic of the proposed multiplier, which is based on the transconductor multiplier structure proposed in [63], is shown in Fig. 4.19. The central component of this four quadrant multiplier is CMOS programmable transconductors. As a currentmode element, it converts the input voltage signals into differential current to realize the multiplication. As shown in Fig. 4.1,9, the differential structure was selected, hence the even order terms generated by the nonlinear components were cancelled, therefore enhance the linearity of the multiplier. In order to reduce the leakage of the input RF signal to the output, a pair of NMOS transistors M 9 and M 10 is inserted between the outputs of the transconductor M 5 M 8 and the multiplier output. To compensate the gain roll-off at the high frequencies, the shunt-peaking topology was employed, just like the case in UWB LNA design. Two inductors L 1 and L with optimized values are added in series with load resistors at the output (drain of M 9 and M 10 ), hence the gain performance at the high-frequency end was improved and the wide bandwidth was achieved. Two source-follower buffers were also included to facilitate the intermediate frequency (IF) signal measurement.

10 V dd V dd V dd V dd IF- L 1 M 11 M 1 L IF+ R 1 - V o + R V b I o1 I o M 9 M 10 I 1 I 4 Y+y I I 3 Y-y M 5 M 6 M 7 M 8 X+x M 1 X-x M M 3 M 4 X+x Fig. 4.19. Schematic of the proposed multiplier. As shown in Fig. 4.19, the RF signal x enters the lower branches formed by transistors M 1 M 4, which operate in the linear region through the bias voltage of X. While for the transistors M 5 M 8 used for LO template signal y, operating in saturation region was achieved when proper DC bias voltage Y was provided. Under the condition of the triode region, the large signal model of the MOS transistor was applied to M 1 M 4, and the corresponding current flowing through each of the lower branches, I 1 to I 4, can be expressed as [19], [64] I i = K X ± x V tn V dsi V dsi (4.3)

103 W where K = μ n Cox, V tn is the NMOS threshold voltage, and V dsi is the drain-source L voltage of the i-th MOS transistor. For the MOS transistor, the value of the transconductance g m is dependent on the dc bias conditions. As g m of the transistor in the saturation region is much larger than that of the transistor in the triode region, the upper transistors ( M 5 M 8 ) operating in the saturation region can be considered as the source followers. Therefore, for the lower branch transistors M 1 M 4, the corresponding drain-source voltage V dsi can be expressed as [64] V = V y (4.4) dsi ds + for M 1 and M, and V dsj = V y (4.5) ds for M 3 and M 4, respectively. Here V ds is the drain-source voltage of the transistor at the bias point under the condition of x = y = 0. As shown in Fig. 4.19, the total output current I o can be derived as [64] I o ( I + I ) ( I + I ) = ( I I ) + ( I ) = I = (4.6) o1 I o 1 3 4 1 3 I 4 where Vds + y I1 = K X + x Vtn ( Vds + y) (4.7a)

104 Vds + y I = K X x Vtn ( Vds + y) (4.7b) Vds y I 3 = K X x Vtn ( Vds y) (4.7c) Vds y I 4 = K X + x Vtn ( Vds y) (4.7d) Hence the final output current is ( V + y) Kx( V y) Kxy I o = Kx ds ds = 4 (4.8) where we assumed all the size of the transistors ( M 1 M 4 ) are equal, therefore K is same to all transistors. Hence the multiplication function was achieved, and the corresponding output voltage of the multiplier can be expressed as [64] V = I Z = 4KxyZ (4.9) o o o o where Z o is the output load between the + and output. 4.. AC Analysis Fig. 4.0 presents the simplified small-signal equivalent circuit used for bandwidth analysis. First, the transconductor ( M 1 to M 8 ) was assumed to be an ideal current source with the parasitic capacitance of C at its output. Furthermore, to simplify the circuit analysis, the output resistance is omitted because of its much larger value compared with the impedance seen from the source of the cascoded transistors such as M 9 and M 10. In Fig. 4.0, the L and R L are the load inductor and load resistor (i.e., L 1

105 and L, and R 1 and R shown in Fig. 4.19), output resistance of M 9 or M 10 g m and r ds are the transcondctance and, and v gs is the gate-source voltage of transistor M 9 or M 10. As shown in Fig. 4.19, in order to improve the bandwidth, the shunt-peaking topology was employed, where the output load resistance R L is in series with the inductor L to compensate the gain roll-off at the high-frequency end. For the output, under the condition of the open circuit, the parasitic capacitance at the output can be ignored in the analysis because of its very small value. Typically, the drain node is the dominant pole, because the equivalent resistance seen at the source node is low and approximately1 / g. However, in our case, the parasitic capacitance associated with the m source node could be large, because three transistors are connected to the same node, thus produce the dominant pole [64]. i g m v I gs - C + r v ds gs V o L RL Fig. 4.0. Simplified small-signal equivalent circuit. As shown in Fig. 4.0, the transfer function can be expressed as [64]

106 v i o = ω CL 1+ g r m ds RL + jωl jωc L + 1+ g r ( R + r ) m ds ds + 1 (4.30) Hence the dominant and non-dominant poles can be expressed as follows, assuming that the two poles can be separated from each other [64], g mrds ω p = 1+ 1 (4.31a) ( R + r )C L ds RL + rds ω p = (4.31b) L and the zero is ω z = R L / L. According to schematic simulation ω p1 is around. GHz, while ω p is much higher than ω p1. Hence ω p1 is the dominant pole for this case. In theory, under the condition that the dominant pole ω p1 can be cancelled by the zero ω z [51], the bandwidth of multiplier will be increased dramatically, hence shunt-peaking topology effectively improve the bandwidth performance [51]. 4..3 Fabrication and Results The proposed multiplier is fabricated with 0.18-µm CMOS process. The layout structure was arranged symmetrically to reduce the potential unbalance caused by nonsymmetric structure. The octagonal-shape inductors L 1 and L are optimized to achieve the constant inductance over the frequency range from 3.1 to 10.6 GHz. To calculate the frequency response, the RF and LO ports were fixed to DC, the input signal was directly fed to the source node of M 9 and M 10. First, the frequency response of the multiplier without shunt-peaking inductor and load capacitance at the output was investigated, with the result showing in Fig. 4.1. The 3-dB bandwidth in this case is around GHz. For comparison purpose, an additional 100-fF capacitance was

107 connected to the same source node of M 9 ( M 10 ), as shown in Fig. 4.19, and the bandwidth reduced to about 1 GHz, as shown in Fig. 4.1, which validates the dominant pole assumption. Fig. 4. compares the frequency response between the situations of with output buffer and without output buffer when the shunt-peaking inductors are used. It is obvious that after the inductor of around 30 nh is included, the bandwidth is increased to 10 GHz, indicating that pole-zero cancellation topology really took into effect. In the case where the buffer is included to the output of the multiplier, the simulation result indicates that the bandwidth of multiplier is reduced to 7 GHz, because of the extra capacitive loading from the buffer. -10-15 No Load 100 ff Load Gain (db) -0-5 -30-35 -40-45 -50 10-10 -1 10 0 Frequency (GHz) 10 1 10 Fig. 4.1. Frequency response for dominant pole. Fig. 4.3 shows the fabricated multiplier chip, with the size of 1 mm 0.7 mm, including the RF and dc bias pads for on-wafer measurement purpose. The on-wafer RF

108 probes were used on RF and LO ports, while the IF ports were measured through offchip with package. -10-15 Without Buffer With Buffer Gain (db) -0-5 -30-35 -40-45 -50 10-10 -1 10 0 10 1 10 Frequency (GHz) Fig. 4.. Frequency response for shunt-peaking inductor effect. Fig. 4.3. Photograph of the fabricated multiplier.

109 The measured conversion gain and RF-port return loss were shown in Fig. 4.4, where IF frequency was fixed to 10 MHz and LO power is -1 dbm. The conversion gain is somewhat lower than the simulated one, and has the value of more than 7 db over the band of 3 to 10 GHz, including the output buffer effects. The difference between measurement and simulated one is caused by parasitic resistant loss from shunt-peaking inductor and buffer, also the parasitic capacitor from the buffer. For the RF-port return loss, over the band of 3 to 10 GHz, RF-port return loss of 10 db was achieved, and reasonably matched the simulated result. Fig. 4.4. Conversion gain and RF return loss with the IF frequency 10 MHz, LO power is -1 dbm, and RF power is -0 dbm.

110 4.3 Receiver Front-end The receiver front-end consists of the above-designed template tunable pulse generator, LNA, and multiplier, which is shown in Fig. 4.5. To simulate the time domain response, two monocycle pulses with same width of 0. ns, but different amplitudes are used. The pulse with smaller amplitude is applied to RF input of multiplier through LNA, while the larger pulse is fed to the LO port of multiplier from the template tunable pulse generator. IF signal was generated at the output of the sourcefollower buffer. Fig. 4.6 shows the simulated IF signal in time-domain, where the output of the multiplier depends on the polarity of the received RF signal. When the RF pulse is in-phase with LO pulse, the output is positive, as shown in Fig. 4.6(a). When the RF pulse is out-of-phase with LO pulse, the output is negative, which is shown in Fig. 4.6(b). Expected output is obtained at the output of the multiplier, and shows that the multiplier has sufficient bandwidth and is able to work with the sub-nano second pulse inputs. Fig. 4.7 shows the layout of CMOS receiver front-end including the components of template tunable pulse generator, UWB LNA, multiplier as well as RF and dc pads, with the final size of 1.4 mm 0.7 mm. RF input LNA LO Multiplier IF Oscillator (PRF) Template tunable pulse generator Fig. 4.5. Block diagram of the receiver front-end.

111 Input (V) Output (V) 0. 0-0. LO Input RF Input -0.4 0 0. 0.4 0.6 0.8 1 Time (ns) 0.06 0.04 0.0 0-0.0 0 0. 0.4 0.6 0.8 1 Time (ns) (a) Output (V) Input (V) 0. 0-0. LO Input RF Input -0.4 0 0. 0.4 0.6 0.8 1 Time (ns) 0.0 0-0.0-0.04-0.06 0 0. 0.4 0.6 0.8 1 Time (ns) Fig. 4.6. Transient simulation of the receiver front-end. (a) RF and LO pulses are inphase, (b) RF and LO pulses are out-of-phase. (b) Fig. 4.7. Layout of the proposed receiver front-end.

11 CHAPTER V UWB UNIPLANAR ANTENNA * Unlike the narrow band systems, the antenna of the UWB system is a critical element for pulse signal transmission. Many antennas, especially in the telecommunication applications, are resonant elements that are tuned to particular center frequencies and have relatively narrow bandwidths. In contrast, UWB antenna designs seek much broader bandwidths and require non-resonating operation. For the impulsetype UWB system, the antenna should be able to radiate and receive the short pulse signal without undesirable distortion on the transmitting or receiving signal waveform. To fulfill this requirement, the antenna input reflection should be minimized over the entire UWB frequency band. Otherwise the multiple reflections between antenna and transmitter/receiver will produce the clutter-like signals and degrade the system performance. There are several types of UWB antennas that can be used for short pulse transmission, such as TEM horn, bow-tie, Vivaldi and conical antennas [13], [7], [65]- [69]. All of these UWB antennas can transmit and receive short pulse waveforms with much less undesirable distortions. Among them TEM horn antenna and its variants are used often in the impulse-type UWB systems. One of the variants developed in our research group, named microstrip quasi-horn antenna or quasi-horn antenna, has been successfully applied to the subsurface penetrating radars [14], [70]. The quasi-horn antenna uses the non-uniform transmission line (NUTL) structure realized by microstripline structure. Therefore the input feeding structure of the quasi-horn is compatible with the microstrip line, which makes the easy implementation of input feeding possible in most designs without any special transition. The performance of the quasi-horn antenna is similar to the TEM horn antenna, which has the advantage of high gain and linear * 006 IEEE. Parts of this chapter are reprinted, with permission, from Meng Miao and Cam Nguyen, On the development of an integrated CMOS-based UWB tunable-pulse transmit module, IEEE Transactions on Microwave Theory and Techniques, vol. 54, pp.3681-3687, October 006.

113 phase characteristic. In addition, when used as the receiving antenna, the quasi-horn antenna outputs a voltage waveform that is identical to the incident E field in time domain, therefore is a preferred metrology receiving antenna for making a direct measurement of transient EM fields [7]. Hence the quasi-horn antenna will be used as receiving antenna in the following UWB antenna measurement to verify the performance of the designed UWB antenna in time-domain when used as transmitting antenna. For most commercial applications, however, the large size of the abovementioned UWB antennas makes them not feasible for portable or handheld uses. In this chapter, a low-cost, compact, easy-to-manufacture coplanar UWB antenna was developed that is omni-directional, radiation-efficient and has a stable UWB response, which can be easily integrated with the designed tunable UWB CMOS RFIC chips. The developed uniplanar UWB antenna can be considered as the planar variant of the TEM horn antenna, which covers the entire UWB frequency range of 3.1 10.6 GHz. The design procedure also follows the design method of TEM horn antenna [71], optimizing the antenna structure to achieve the minimum reflections over the operating frequency range. The performance of the designed antenna was also investigated to achieve the transmitted pulse signal with the small distortion in time domain. 5.1 Uniplanar UWB Antenna Design In general, an antenna may be viewed as the non-uniform impedance transformer, coupling the energy between the closed transmission system and an open system or the free space around the antenna. Therefore, by varying the TEM characteristic impedance Z 0 of the antenna smoothly, the minimum internal reflections of the antenna input signal over the operating frequency range can be achieved. To facilitate integration with the designed CMOS tunable monocycle pulse generator chip, a compact UWB antenna with uniplanar structure is preferred. Additionally, a center-fed uniplanar structure should be avoided due to the reason that the feed region of this structure lies in the heart of the most intense near-fields

114 surrounding the antenna. Strong coupling between the feed structure and antenna seriously affects the near field and distorts the antenna pattern [7]. y X Conductor x Substrate Input Feed Fig. 5.1. Basic structure of the uniplanar antenna. To overcome potential problems caused by the unwanted coupling between above-mentioned field from feed network and antenna and to meet the requirements for UWB applications, such as ultra-wide bandwidth, reasonable efficiency, satisfactory radiation properties, and linear phase characteristics, the proposed structure of the UWB uniplanar antenna is shown in Fig. 5.1. It is the planar NUTL-based traveling-wave antenna, fabricated on a Duroid substrate having 0.05-in thickness and relative dielectric constant of 10.5. The operation of the antenna is based on the principles of NUTLs [73] and well-known traveling-wave antennas. As this antenna can be

115 considered as the planar variant of the TEM horn antenna, the similar design topology is applied to this planar structure. As shown in Fig. 5.1, the edge feed is used to overcome the center feed disadvantage. In the quasi-uniform section of coplanar waveguide (CPW), most of the energy is confined within the transmission line until it reaches the antenna center, where the energy is coupled from the CPW to the two parallel NUTL slot lines. Assume the source and load impedances are to be matched at x = 0 and X, as shown in Fig. 5.1, we have [71] ( / dx) 0 dz (5.1) 0 = at the input section (x = 0) and the output section (x = X), where Z 0 is the characteristic impedance of NUTL slot line along x direction. For the given maximum allowable input reflection coefficient optimum characteristic impedance variations of the NUTL is [71]: R (0) max, the 1 1 Z 0 ( X ) x log Z 0 ( x) = log[ Z 0 (0) Z 0 ( X )] + log G B, (5.) Z 0 (0) X x where X is the length of NUTL slot line as shown in Fig. 5.1, G B, and its X parameter B are given in [74]. The maximum allowable input reflection coefficient is: B Z 0 ( X ) R (0) = tanh (0.173) log (5.3) max sinh B Z 0 (0)

116 For the given input reflection coefficient R (0) max, parameter B determines the antenna length X. For the special case B = 0, the structure of antenna will be the commonly used exponential taper. As shown in Fig. 5.1, the antenna substrate is Duroid microwave board with h = 0.5 in and ε r = 10.5, and the input feeding of the antenna is the section of quasi-cpw transmission line with 50-Ω characteristic impedance. At the antenna center, the energy is coupled from the 50-Ω CPW to the two parallel slot lines. Based on the substrate parameters, the characteristic impedance of the slot line at the antenna center was chosen as 100-Ω to facilitate the antenna etching, as the characteristic impedance of the slot line less than 100-Ω will result in too narrow slot width. On the other hand, the transition of 50-Ω CPW to two parallel 100-Ω slot lines should be as smooth as possible to minimize the internal reflection. Hence the slot width of the slot line should be close to the gap width of CPW. When designing 50-Ω CPW, another consideration is the package specifications associated to the CMOS RFIC chip. In our case, standard 5-lead LQFP open package was selected to accommodate the CMOS chip, which has 13 leads along each side, with the lead width of 1-mil and gap width between the leads of l4-mil [75]. To achieve the smooth transition from the signal and ground leads of the package accommodating the designed CMOS chip to the path of quasi-uniform 50-Ω CPW feed line, the parameters of quasi-cpw feed line are selected as shown in Table 5.1. Table 5.1. Parameters of 50-Ω quasi-cpw feed line. Z 0 (Ω) Central metal width (mil) Gap width (mil) 50 0 10 For the uniplanar UWB antenna design, the tapered slot lines are used to emulate an impedance transformer from the source impedance Z 0 (0) = 100 Ω to the free space

117 impedance Z ( ) = 377 Ω over the UWB frequency range of 3.1 to 10.6 GHz. 0 X Considering above parameters, and assuming the maximum allowable input reflection coefficient R (0) = 0.1, the design parameter B can be derived as 1.53 from (5.3). max Considering the lower frequency limit of 3.1 GHz, from (5.3), the antenna half-length is selected as X = 600 mils. The initial value of the characteristic impedance Z 0 of the tapered sections were selected using (5.) to produce the minimum internal reflections for the antenna input signal over the UWB frequency range of 3.1 to 10.6 GHz. It should note that the initial value of the terminating characteristic impedance at the open end of the antenna is selected as the intrinsic impedance of free space, i.e. 377 Ω. Since this value only works for spherical wave in free space, which is not the condition in our antenna design, this value is probably not the optimum value for Z ( ) to achieve smooth transition at the end of the antenna. Therefore 3D EM simulator Microwave Studio was used to perform the time-domain EM simulation and to optimize the antenna structure to minimize reflections occurring at the open-end transition. 0 X Another issue concerning the variations of the characteristic impedance Z 0 of NUTL slot lines is the implementation of the tapered slot line. As shown in Fig. 5.1, to achieve the compact structure, the proposed antenna utilizes the smooth-changed contours. This will help to avoid any abrupt transition in the shape across the entire antenna structure to minimize the undesirable reflection. For the NUTL slot line transition sections close to the antenna aperture center, the gap width is much smaller compared to the associated metal widths, therefore conventional characteristic impedance formula of the slot line can be used to derive the gap width for the relatively smaller Z 0. On the contrary, for the NUTL slot line transition sections close to the open end of the antenna, the gap widths are kept on increasing, while the metal widths dropped quickly, so the typical slot line calculation method cannot be applied to the transition structure anymore, instead the EM simulator was used to derive the accurate gap width for the specific metal widths and required Z 0.

118 Based on above-mentioned initial conditions, the structure parameters of the proposed antenna with the variable characteristic impedances are derived from (5.). Considering the abrupt variations of the slot edges around the open end of the antenna, along the x-axis the coordinate points with non-uniform steps are applied to the antenna structure, which is sparse around the antenna aperture center and condensed round the open end to maintain the good variation accuracy. Through EM simulation with IE3D [9], the final optimized characteristic impedance Z ( ), the slot-line gap width g (x), and the metal width W (x) (along the y-direction) are presented in Table 5. for each coordinate value along the x-axis. 0 x Table 5.. Dimensions of uniplanar antenna. x (mil) Z ( ) (Ω) g (x) (mil) W (x) (mil) 0 x 10 100 30 750 58.8 101 3.4 747.4 117.1 103 37. 740.6 174. 107 5.8 75.7 9.6 113 78.6 70.9 8.8 13 108. 675.5 333.3 139 145.6 641.6 380.6 151 190. 601.8 44.3 165 4 556.1 463.8 178 313 498.8 498.9 193 39 435.7 59. 08 477.8 367.5 554.3 6 565.6 97 574. 40 654.8 4.7 588.7 51 748.4 149.3 597.1 57 839.8 74.5 600 60 930 0 To fully investigate the performance of the proposed UWB antenna structure, time-domain simulator CST Microwave Studio [31] was selected, which bases on the

119 fact that the final integrated UWB system operates in the time-domain. Hence the antenna simulation is highly facilitated because of the inherent time-domain feature of Microwave Studio. First, the return loss of the antenna structure shown in Fig. 5.1 is studied, and the result in frequency-domain is presented in Fig. 5.. The simulating result provides the very good return loss for UWB antenna over the frequency range of 3 to 1 GHz, where more than -15 db return loss was achieved. The corresponding time-domain reflection result was also presented in Fig. 5.3, where the Gaussian monocycle pulse with the 50% pulse width of 50 ps was used as the excitation input signal. As shown in Fig. 5.3, the small value of the reflected signal was generated, which validate the optimized antenna structure. Return loss (db) 0-5 -10-15 -0-5 -30-35 -40 4 6 8 10 1 Frequency (GHz) Fig. 5.. Simulated return loss of the designed uniplanar antenna.

10 0.8 0.6 Input signal Reflected signal Amplitude (V) 0.4 0. 0-0. -0.4-0.6-0.8 0 0.5 1 1.5 Time (ns) Fig. 5.3. Simulated input reflection of the designed antenna in time-domain. 0 Relative amplitude (db) -5-10 -15-0 4 6 8 10 1 Frequency (GHz) Fig. 5.4. Simulated amplitude of transfer function.

11 The transfer function performance of the proposed antenna was also simulated with CST Microwave Studio [31], at the position of -inch directly above the center of antenna aperture surface. The simulated results were shown in Figs. 5.4 and 5.5. As shown in Fig.5.4, the transfer function was normalized to make it more easily understand, and the simulated normalized amplitude of antenna transfer function has the band pass property, while the phase of the antenna transfer function indicates the good linearity over the entire UWB band, as shown in Fig. 5.5. The good phase linearity of the proposed antenna means the little distortion effect to the final pulse shape. Phase (degree) 0-500 -1000-1500 -000-500 -3000-3500 -4000-4500 4 6 8 10 1 Frequency (GHz) Fig. 5.5. Simulated phase of transfer function. Fig. 5.6 shows the simulated antenna gain for the designed antenna for the coordinate shown in Fig. 5.1. These results indicate that the maximum antenna boresight gain is normally. dbi at the frequency of 3.1 GHz.

1 150 10 90 5 db 0-5 60 3.1 GHz 6.8 GHz 10.6 GHz 30 150 10 90 5 db 0-5 60 3.1 GHz 6.8 GHz 10.6 GHz 30-10 -10 180 0 180 0 10 330 10 330 40 70 (a) 300 40 70 (b) 300 150 10 90 5 db 0-5 60 3.1 GHz 6.8 GHz 10.6 GHz 30-10 180 0 10 330 40 70 (c) 300 Fig. 5.6. Simulated antenna patterns. (a) E-plane (x-y plane), (b) E-plane (y-z plane), and (c) H-plane patterns for the frequencies 3.1, 6.8, and 10.6 GHz. 5. Antenna Fabrication and Test To facilitate the antenna performance measurement, the individual planar antenna was first fabricated, which is shown in Fig. 5.7, including antenna aperture, SMA fixture, and section of uniform CPW transmission line. The area occupied by the antenna aperture is only 1. in 1.5 in.

13 Fig. 5.7. Photograph of the developed UWB antenna along with 50-Ω CPW feed line and SMA connector (on the left). In the uniform section of CPW connecting to the SMA connector to the antenna, most of the energy is confined within the transmission line until it reaches the antenna center, where the energy is coupled from the CPW to the two parallel 100-Ω slot lines. It should be particularly noted that for impulse UWB applications, as is considered here, the time-domain performance of the antenna is much more critical than its frequency counterpart. The antenna is used for transmitting or receiving UWB time-domain signals (impulse or monocycle pulses as addressed here), not multiple discrete frequency components in CP mode. Another word, the antenna transmits all frequency components simultaneously, not consecutively. Although, from the Fourier series point of view, the frequency and time domain are correlated, and one can then view them as equivalent, they should be distinguished from one to another for UWB time-domain applications. Fig. 5.8 shows the measured and simulated results of return loss in the frequency domain. Measured result shows more than 1-dB return loss over the entire 3.1 10.6 GHz UWB frequency band. As this return loss includes all effects from the designed

14 antenna, CPW feed line, and SMA connector, it is difficult to derive the antenna s actual performance from the frequency-domain results. Fig. 5.8. Measured and simulated return loss of uniplanar UWB antenna. On the contrary, it is relatively very easy to distinguish the antenna performance from other effects in the time domain. Furthermore, as the antenna is intended for radiating impulse or monocycle pulses, as discussed earlier, it is imperative to characterize it in time domain. Fig. 5.9 shows the measured and simulated time-domain reflectometry (TDR) response results in time domain for a 50-ps input impulse signal. It is clear that, from 0 to 0.5 ns, the response corresponds to effects of the SMA connector and CPW feed line. The response after 0.5 ns is cased by the designed antenna aperture

15 and, as can be seen, the measured result matches very well with that simulated, which confirms the antenna design. Fig. 5.9. Measured and calculated TDR responses of uniplanar UWB antenna. The TDR performance also demonstrates excellent time-domain behavior of the designed antenna, which is crucial for UWB time-domain impulse applications. The measured time-domain results indicate that better than 18-dB return loss is achieved for the antenna. Good performance together with small size and uniplanar structure make the designed antenna a very good candidate not only for UWB applications but also for integration with printed-circuit UWB transmitters and receivers.

16 5.3 UWB Transmitter Module Fig. 5.10 shows the photograph of the fabricated tunable UWB transmitter module integrating the previously described CMOS tunable monocycle pulse generator and UWB uniplanar antenna. The CMOS chip is mounted directly onto the edge of the antenna without a feed line. The transmission line connecting the SMA connector and the CMOS chip, used for feeding the external 10-MHz clock signal, and the bias lines are etched onto the same board of the antenna. It is noted that the CMOS chip contains other RFICs besides the pulse generator. Fig. 5.10. Photograph of the fabricated UWB transmitter module. Fig. 5.11 shows the block diagram of the test setup used for pulse transmission measurement of the UWB transmitter module. The quasi-microstrip antenna operating