Roadmap for Board Level Optical Interconnects They re Coming Sooner Than You Think! MIT Microphotonics Center Communications Technology Roadmap Technical Working Group on On-Board Optical Interconnects http://mphotonics.mit.edu/ B. Roe Hemenway, Ph.D. Photonic Controls LLC, Horseheads, New York SEMICON West 10 July 2013 Contributors and Participants Mehdi Asghari - Kotura Doug Butler - Corning Terry Bowen Tyco Electronics Bruce Booth Optical interlinks Bill Bottoms Nano Nexus Shelly Buchter TE Connectivity George Celler - Soitec Yong-Kai Chen Lucent Doug Coleman Corning Dan Evans - Palomar Laura Giovane - Avago Madeleine Glick - APIC Richard Grzybowski Photonic Controls Roe Hemenway Photonic Controls Lionel Kimerling MIT Tremont Miao Analog Devices Ling Liao Intel Hai-Feng Liu - Intel Jifeng Liu Dartmouth Jurgen Michel - MIT Jianwei Mu - MIT Dick Otte - Promex Petre Popescu Sonas Systems Marco Romagnoli CNIT Kapil Shrikhande Force10 Lisa Sinclair - MIT Lee Smith Amkor Vladimir Stojanovic MIT Mark Taubenblatt IBM Mike Tan - HP Mark Tryson TE Connectivity Chris Weaver MIT Yutong Wu McMaster U. 2 1
Overview Electrical links within PCBs (keep) approaching technical limits Optical I/O won the rack, now the shelf and next the PCB Why? Low power devices + component integration + manufacturing scale Board level optics relieve system constraints We asked: What solutions are ready and what challenges remain? Two mature solutions: Silicon microphotonics (SiP or SiOEICs) Vertical Cavity Surface Emitting Lasers (VCSELs) Challenges: full manufacturing integration, optical connectors and packaging Migration of optics from board edge eliminates components, drivers and transmission lines Optical Connection Electrical Connection Transmission Line OE Optronics Pluggable Cage Linecard/PCB MSA AOC Cage Agilent Embedded Reflex Integrated Altera Board Level Fujitsu 2
Figures of Merit Relative Cost Power dissipation Down to 10, 1 and 0.1 pj/bit Density From ~100 Gbps/cm 3 to 200, 400, 800 Gbps/cm 3 Distance Down to 5 and 0.5 cm Up to 10, 100, 1000 meters Integratability Time Domain Scaling - Bit rate - assuming 10G baseline Down to 5 and 1 Gbps Up to to 28, 40, 100 Gbps with advanced modulation formats Optical Domain Scaling Number of wavelengths, polarization, space modes, etc. Space Domain Scaling - Lane Count Parallelism Scaling lane count down to a single lane and up to 32, 48, 64, 128 lanes Manufacturability Functional flexibility Low power optoelectronics + CMOS integration result in lower-cost optical engines Rack-Level Links SER Equalizing Driver E/O O/E TIA LA CDR /DES Optical TxRx Electrical PHY Discrete Electrical PHY ASIC OIF-CEI-28-VSR spec, via K. Matthews of Corning, Inc. Board-Level Links SER + CMOS Driver Low Power E/O O/E CMOS TIA/LA + DES 3
Evolution of board-level optical engines via CMOS integration Chip on Carrier or MCM Assembly Verdiell, Samtec, Inc. Silicon Interposer 3D Assembly 7 Drivers: Photonics Offer Bandwidth Density and Lower Power at Acceptable Cost Bandwidth density Power consumption Design flexibility Mass production learning curve cost 8 4
Generic Compute System Buses Tightly integrated, low power, ~128 lanes, 10G per lane, variable protocols & distances 9 Migration to Board Level Optics Shorter distances, higher bandwidth density, lower power Interconnect Time Frame Reach BW BW Density (Gbps/cm 2 ) Energy (pj/bit) Rack ~2000 20-100m 40-200 G ~100 1000 200 Chassis ~2005 2-4 m 20-100 G ~100-400 400 50 Backplane ~2010 1-2 m 100-400 G ~400 100 25 Board ~2015.01-1 m 0.3 1T ~1250 25 5 Module ~2020 1-10 cm 1 4 T >10000 1.1 Chip ~2025 0.1-3 cm 2-20 T >40000.1.01 10 5
VCSEL vs. Silicon Viable Optical Links Direct modulation to 25 Gb/s 1-3 mw output Wavelengths 850 980 nm Uses multimode waveguides Shared CW InGaAsP laser External silicon mod. to 40 Gb/s 1310-1550 nm wavelength Single mode waveguides 11 Modulated Light Source Roadmap DM VCSELs can scale to 32G+ Ext Mod Silicon to >400G via WDM Today (~2013) 10-25 G Tomorrow (2015-20) 40-100 G Beyond (2021+) >100 G VCSELS Directly modulated VCSELs coupled to multimode waveguides. 10 G is mature, 25 G available commercially, 32 G emerging. High current wear-out 980 nm for efficiency, speed and life. Coarse WDM for 4x25 G solutions Migration to external modulation Multi-spatial mode? Silicon Photonics Edge-emitting shared laser coupled to free carrier phase modulators 25 G On-Off Keyed is standard, 40 G available WDM with few fiber alignments, possible integrated laser source Edge coupled DFB or ECL arrays EAMs in SiGe emerge Lasers shared at system level PAM4, DPSK, DQ-PSK Optical gain integrated into SiP 12 6
Optical Waveguide Roadmap VCSELs leverage easy to couple multimode waveguides Silicon uses single mode, gets distance for free Today (~2013) 10-25 G for VCSELS Bend-resistant multimode silica fiber, 12F ribbons for Silicon Photonics Bend-resistant 9/125 single mode fiber 12F ribbons 50/125 µm 9/125 µm Polymer waveguide sheets/ribbons Hitachi High density single mode fiber array (6/80 core/clad) 6/80 µm Tomorrow (2015-20) 40-100 G Application Specific MMF bend-resistant Polymer waveguides embedded in PCB 80/100 µm Univ. Gent Multiple core single mode fiber Polarization-maintaining SM fiber Corning PLC Beyond (2021+) >100G Mode multiplexing? Free space? PM multicore SMF? Plasmonic waveguides? 13 Optical Coupling Roadmap Trend to passively aligned array coupling Expanded beam lenses for VCSELS for Silicon Photonics Ball or tapered fiber lens Today (2013) 10-25 G 90º bend via plastic lens array 1x12 configuration USConec Expanded mode inverse taper for edge coupling Densmore 08 Butt coupled to large core MMF Surface grating coupler PLC Tomorrow (2015-20) 40-100 G Beyond (2021+) >100 G 4x12 configuration 3D expanded mode taper 90º bend in PCB Passive Alignment Mode multiplexing? Kyocera Mode multiplexing? Self alignment? Ashgari 08 14 7
Optical Connectors Dominant connector is MT / MPO / MTRJ Designed for rack-rack interconnect 12 to 48 fibers on 250 micron pitch Too costly, bulky for board level use Cheaper, denser array connectors are emerging Usconnec MTP / MPO OE-Tek compact MT nanoprecision TE Connectivity 15 Optical Receiver Roadmap Tighter CMOS integration, lower capacitance, WDM Today 10-25 G Tomorrow 40-100G for VCSELS Tombstoned large area GaAs detectors, butt coupled Smaller, lower capacitance detectors CWDM plastic microoptics OSI for Silicon Photonics Tombstoned InGaAs detector arrays, butt coupled GeSi polarization diversity waveguide detectors Single polarization detector arrays with PM fiber Ge PIN/APD? Integrated 4 Channel WDM Beyond 100G+ PAM-4 demodulation Mode demultiplexing? 16-64 channel DWDM Coherent DQ-PSK? 16 8
Integration Roadmap CMOS-compatibility fewer discretes lower power + cost Today 10-25 G Tomorrow 40-100G Beyond 100G+ for VCSELS Discrete VCSEL array, driver, receiver and CMOS chips on MC carrier VCSELS driven directly from integrated CMOS Lower power receivers without CDR, distortion compensation for Silicon Photonics Discrete CMOS, driver and optical engine, all in Si CMOS Embedded optics Si Photonic CMOS interposer with stacked-chip drivers, CMOS logic. Integrated package, fewer parts Monolithic SiP with integrated driver, flip chip CMOS logic 2.5D chip stack Fully monolithic 3D optical chip stack 17 Integration and Packaging Stand-alone at PCB perimeter; pluggable, e.g. Active Optical Cable Stand-alone function, discrete electronics, short PCB transmission lines, connectorized MCM integration with discrete optics, CMOS electronics integrated On-die optics, connectorized or optical PCB 9
Electronic/Photonic Convergence in Silicon Conclusions VCSEL and Silicon based board level optical interconnects are viable Driven by higher BW density, lower power Lower cost through simplicity and integration Board-level optical connectors are emerging Primary challenge is manufacturing integration Industry must optimize mix of solutions and deliver dominant designs Role of standards? 10