SMPS MOSFET Applications l Switch Mode Power Supply (SMPS) l Motor Drive l Bridge Converters l All Zero Voltage Switching l Lead-Free Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Enhanced Body Diode dv/dt Capability PD - 95498A IRFR3412PbF IRFU3412PbF HEXFET Power MOSFET V DSS R DS(on) max I D V 0.025Ω 48A D-Pak IRFR3412 I-Pak IRFU3412 Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 48 I D @ T C = C Continuous Drain Current, V GS @ V 34 A I DM Pulsed Drain Current 190 P D @T C = 25 C Power Dissipation 140 W Linear Derating Factor 0.95 W/ C V GS Gate-to-Source Voltage ± 20 V dv/dt Peak Diode Recovery dv/dt ƒ 6.4 V/ns T J Operating Junction and -55 to 175 C T STG Storage Temperature Range Soldering Temperature, for second 300(1.6mm from case ) Mounting torqe, 6-32 or M3 screw lbf in (1.1N m) Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 48 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 190 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 29A, V GS = 0V t rr Reverse Recovery Time 68 ns T J = 125 C, I F = 29A Q rr Reverse RecoveryCharge 160 240 nc di/dt = A/µs I RRM Reverse RecoveryCurrent 4.5 6.8 A t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) www.irf.com 1 12/03/04
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0. V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 0.025 Ω V GS = V, I D = 29A V GS(th) Gate Threshold Voltage 3.5 5.5 V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 1.0 V µa DS = 95V, V GS = 0V 250 V DS = 80V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage V GS = 20V na Gate-to-Source Reverse Leakage - V GS = -20V Dynamic @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 25 S V DS = 50V, I D = 29A Q g Total Gate Charge 59 89 I D = 29A Q gs Gate-to-Source Charge 21 32 nc V DS = 50V Q gd Gate-to-Drain ("Miller") Charge 17 26 V GS = V, t d(on) Turn-On Delay Time 19 V DD = 50V t r Rise Time 68 ns I D = 29A t d(off) Turn-Off Delay Time 44 R G = 6.8Ω t f Fall Time 37 V GS = V C iss Input Capacitance 3430 V GS = 0V C oss Output Capacitance 270 V DS = 25V C rss Reverse Transfer Capacitance 150 pf ƒ = 1.0MHz C oss Output Capacitance 40 V GS = 0V, V DS = 1.0V, ƒ = 1.0MHz C oss Output Capacitance 170 V GS = 0V, V DS = 80V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 270 V GS = 0V, V DS = 0V to 80V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 160 mj I AR Avalanche Current 29 A E AR Repetitive Avalanche Energy 14 mj Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.05 R θja Junction-to-Ambient (PCB mount)* 50 C/W R θja Junction-to-Ambient 1 Notes: Repetitive rating; pulse width limited by max. junction temperature. (See Fig. 11) Starting T J = 25 C, L = 0.38mH, R G = 25Ω, I AS = 29A, (See Figure 12a) ƒ I SD 29A, di/dt 420A/µs, V DD V (BR)DSS, T J 150 C Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. * When mounted on 1" square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994 2 www.irf.com
I D, Drain-to-Source Current (A) 0 1 0.1 TOP BOTTOM VGS 15V V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C 0.01 0.1 1 V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current (A) 0 TOP BOTTOM VGS 15V V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 4.5V 20µs PULSE WIDTH T J = 175 C 1 0.1 1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 0 3.0 I D = 48A 2.5 I D, Drain-to-Source Current (A) 1 T = 175 J C T = 25 J C V DS= 25V 20µs PULSE WIDTH 0.1 4.0 5.0 6.0 7.0 8.0 9.0 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.0 1.5 1.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 120 140 160 180 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) IRFR/U3412PbF 000 00 V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 20 16 12 I D = 29A V DS = 80V VDS= 50V VDS= 20V Ciss 8 0 Coss 4 Crss 1 V DS, Drain-to-Source Voltage (V) 0 0 20 40 60 80 Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 0.0 0 OPERATION IN THIS AREA LIMITED BY R DS (on).0 T J = 175 C.0 µsec 1.0 T J = 25 C V GS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V SD, Source-toDrain Voltage (V) 1 0.1 Tc = 25 C Tj = 175 C Single Pulse 1msec msec 1 0 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
50 LIMITED BY PACKAGE V DS R D 40 R G V GS D.U.T. - V DD I D, Drain Current (A) 30 20 V GS Pulse Width 1 µs Duty Factor 0.1 % Fig a. Switching Time Test Circuit V DS 90% 0 25 50 75 125 150 175 T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 1 0.1 D = 0.50 0.20 0. 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc T C 0.01 0.00001 0.0001 0.001 0.01 0.1 t 1, Rectangular Pulse Duration (sec) P DM t 1 t 2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
R G V DS 20V V GS tp L D.U.T IAS 0.01Ω Fig 12a. Unclamped Inductive Test Circuit tp 15V DRIVER - V DD A V (BR)DSS E AS, Single Pulse Avalanche Energy (mj) 300 250 200 150 50 TOP BOTTOM I D 12A 21A 29A 0 25 50 75 125 150 175 Starting T, Junction Temperature ( J C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF V GS Q GS Q GD D.U.T. V - DS V GS V G 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET Power MOSFETs www.irf.com 7
D-Pak (TO-252AA) Package Outline D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN THE ASS EMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S EMB LY LOT CODE IRFU120 916A 12 34 PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 16 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S E MBLY LOT CODE IRFU120 12 34 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 16 A = ASSEMBLY SITE CODE 8 www.irf.com
I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: THIS IS AN IRFU120 WITH ASSEMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 1999 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S E MBLY LOT CODE IRFU120 919A 56 78 PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 19 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S E MBLY LOT CODE IRFU120 56 78 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 19 A = ASSEMBLY SITE CODE www.irf.com 9
D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 (.641 ) 15.7 (.619 ) 16.3 (.641 ) 15.7 (.619 ) 12.1 (.476 ) 11.9 (.469 ) FEED DIRECTION 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH NOTES : 1. OUTLINE CONFORMS TO EIA-481. 16 mm Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information.12/04 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/