TM ADVANCED LINEAR DEVICES, INC. EPAD ALD2724E/ALD2724 E N A B L E D DUAL EPAD PRECISION HIGH SLEW RATE CMOS OPERATIONAL AMPLIFIER KEY FEATURES Factory pr-trimmd V OS V OS =25µV @ I OS =.1pA 5V/µs slw rat EPAD (Elctrically Programmabl Analog Dvic) Usr programmabl V OS trimmr Rail-to-rail input/output Compatibl with standard EPAD Programmr Each amplifir V OS can b trimmd to a diffrnt V OS lvl High prcision through in-systm circuit prcision trimming Rducs or liminats V OS, PSRR, CMRR and TCV OS rrors Systm lvl calibration capability Low voltag opration BENEFITS Rady-to-us off-th-shlf standard part Custom automatd trimming optional Rmot controlld automatd trimming In-Systm Programming capability No xtrnal componnts No intrnal clocking nois sourc Simpl and cost ffctiv Small packag siz Extrmly small total functional volum siz Low systm implmntation cost GENERAL DESCRIPTION Th ALD2724E/ALD2724 is a dual monolithic oprational amplifir with MOSFET input that has rail-to-rail input and output voltag rangs. Th input voltag rang and output voltag rang ar vry clos to th positiv and ngativ powr supply voltags. Typically th input voltag can b byond positiv powr supply voltag V+ or th ngativ powr supply voltag V- by up to 3mV. Th output voltag swings to within 6mV of ithr positiv or ngativ powr supply voltags at ratd load. With high impdanc load, th output voltag of th ALD2724E/ALD2724 approachs within 1mV of th powr supply rails. This dvic is dsignd as an altrnativ to th popular J-FET input oprational amplifir in applications whr lowr oprating voltags, such as 9V battry or ±3.25V to ±5V powr supplis ar bing usd. Th ALD2724E/ALD2724 offrs high slw rat of 5.V/µs. Th rail-to-rail input and output fatur of th ALD2724E/ALD2724 xpands signal voltag rang for a givn oprating supply voltag and allows numrous analog srial stags to b implmntd without losing oprating voltag margin. Th output stag is dsignd to driv up to 1mA into 4pF capacitiv and 1.5KΩ rsistiv loads at unity gain and up to 4pF at a gain of 5. Short circuit protction to ithr ground or th powr supply rails is at approximatly 15mA clamp currnt. Du to complmntary output stag dsign, th output can sourc and sink 1mA into a load with symmtrical driv and is idally suitd for applications whr push-pull voltag driv is dsird. APPLICATIONS Snsor intrfac circuits Transducr biasing circuits Capacitiv and charg intgration circuits Biochmical prob intrfac Signal conditioning Portabl instrumnts High sourc impdanc lctrod amplifirs Prcision Sampl and Hold amplifirs Prcision currnt to voltag convrtr Error corrction circuits Snsor compnsation circuits Prcision gain amplifirs Priodic In-systm calibration Systm output lvl shiftr PIN CONFIGURATION -IN A +IN A 1 2 14 13 VE 2A VE 1A N/C 3 12 OUT A ORDERING INFORMATION Oprating Tmpratur Rang C to +7 C C to +7 C -55 C to +125 C 14-Pin 14-Pin 14-Pin Small Outlin Plastic Dip CERDIP Packag (SOIC) Packag Packag ALD2724ESB ALD2724EPB ALD2724EDB ALD2724SB ALD2724PB ALD2724DB * Contact factory for high tmpratur vrsions. V- N/C +IN B -IN B 4 5 6 7 8 TOP VIEW SB, PB, DB PACKAGES 11 1 V+ OUT B VE 1B VE 2B * N/C Pins ar intrnally connctd. Do not connct xtrnally. 9 Rv 2.1 211 Advancd Linar Dvics, Inc. 415 Tasman Driv, Sunnyval, CA 9489-176 Tl: (48) 747-1155 Fax: (48) 747-1286 www.aldinc.com
FUNCTIONAL DESCRIPTION Th ALD2724E/ALD2724 uss EPADs as in-circuit lmnts for trimming of offst voltag bias charactristics. Each ALD2724E/ALD2724 has a pair of EPAD-basd circuits connctd such that on circuit is usd to adjust V OS in on dirction and th othr circuit is usd to adjust V OS in th othr dirction. Whil ach of th EPAD dvics is a monotonically adjustabl programmabl dvic, th V OS of th ALD2724E can b adjustd many tims in both dirctions. Onc programmd, th st V OS lvls ar stord prmanntly, vn whn th dvic powr is rmovd. Functional Dscription of ALD2724E Th ALD2724E is pr-programmd at th factory undr standard oprating conditions for minimum quivalnt input offst voltag. It also has a guarantd offst voltag program rang, which is idal for applications that rquir lctrical offst voltag programming. Th ALD2724E is an oprational amplifir that can b trimmd with usr application-spcific programming or insystm programming conditions. Usr application-spcific circuit programming rfrs to th situation whr th Total Input Offst Voltag of th ALD2724E can b trimmd with th actual intndd oprating conditions. For xampl, an application circuit may hav +5V and -5V powr supplis, and th oprational amplifir input is biasd at +1V, and an avrag oprating tmpratur at +85 C. Th circuit can b wird up to ths conditions within an nvironmntal chambr with th ALD2724E insrtd into a tst sockt connctd to this circuit whil it is bing lctrically trimmd. Any rror in V OS du to ths bias conditions can b automatically zrod out. Th Total V OS rror is now limitd only by th adjustabl rang and th stability of V OS, and th input nois voltag of th oprational amplifir. Thrfor, this Total V OS rror now includs V OS as V OS is traditionally spcifid; plus th V OS rror contributions from PSRR, CMRR, TCV OS, and nois. Typically this total V OS rror (V OST ) is approximatly ±25µV for th ALD2724E. In-Systm Programming rfrs to th condition whr th EPAD adjustmnt is mad aftr th ALD2724E has bn insrtd into a circuit board. In this cas, th circuit dsign must provid for th ALD2724E to oprat in normal mod and in programming mod. On of th bnfits of in-systm programming is that not only is th ALD2724E offst voltag from oprating bias conditions accountd for, any rsidual rrors introducd by othr circuit componnts, such as rsistor or snsor inducd voltag rrors, can also b corrctd. In this way, th in-systm circuit output can b adjustd to a dsird lvl, liminating th nd for anothr trimming function. Functional Dscription of ALD2724 Th ALD2724 is pr-programmd at th factory undr standard oprating conditions for minimum quivalnt input offst voltag. Th ALD2724 offrs similar programmabl faturs as th ALD2724E, but with a mor limitd offst voltag program rang. In is intndd for standard oprational amplifir applications, whr littl or no lctrical porggramming by th usr is ncssary. USER PROGRAMMABLE V OS FEATURE Each ALD2724E/ALD2724 has four additional pins, compard to a convntional dual oprational amplifir which has ight pins. Ths four additional pins ar namd VE1A, VE2A for op amp A and VE1B, VE2B for op amp B. Each of ths pins VE1A, VE2A, VE1B, VE2B (rprsntd by VExx) ar connctd to a sparat, intrnal offst bias circuit. VExx pins hav initial intrnal bias voltag valus of approximatly 1V to 2V. Th voltag on ths pins can b programmd using th ALD E1 EPAD Programmr and th appropriat Adaptr Modul. Th usful programming rang of voltags on VExx pins ar 1V to 4V. VExx pins ar programming pins, usd during lctrical programming mod to injct charg into th intrnal EPADs. Incrasing voltag on VE1A/VE1B dcrass th offst voltag whras incrasing voltag on VE2A/VE2B incrass th offst voltag of op amp A and op amp B, rspctivly. Th injctd charg is thn prmanntly stord. Aftr programming, VExx pins must b lft opn in ordr for ths voltags to rmain at th programmd lvls. During programming, voltags on VExx pins ar incrasd incrmntally to program th offst voltag of th oprational amplifir to th dsird V OS. Not that dsird V OS can b any valu within th offst voltag programmabl rangs, and can b qual zro, a positiv valu or a ngativ valu. This V OS valu can also b rprogrammd to a diffrnt valu at a latr tim, providd that th usful VE1x or VE2x programming voltag rang has not bn xcdd. VExx pins can also srv as capacitivly coupld input pins. Intrnally, VE1 and VE2 ar programmd and connctd diffrntially. Tmpratur drift ffcts btwn th two intrnal offst bias circuits cancl ach othr and introduc lss nt tmpratur drift cofficint chang than offst voltag trimming tchniqus such as offst adjustmnt with an xtrnal trimmr potntiomtr. Whil programming, V+, VE1 and VE2 pins may b altrnatly pulsd with 12V (approximatly) pulss gnratd by th EPAD Programmr. In-systm programming rquirs th ALD2724E application circuit to accommodat ths programming pulss. This can b accomplishd by adding rsistors at crtain appropriat circuit nods. For mor information, s Application Not AN17. ALD2724E/ALD2724 Advancd Linar Dvics 2 of 13
ABSOLUTE MAXIMUM RATINGS Supply voltag, V+ 1.6V Diffrntial input voltag rang -.3V to V+ +.3V Powr dissipation 6 mw Oprating tmpratur rang SB, PB packags C to +7 C DB packag -55 C to +125 C Storag tmpratur rang -65 C to +15 C Lad tmpratur, 1 sconds +26 C CAUTION: ESD Snsitiv Dvic. Us static control procdurs in ESD controlld nvironmnt. OPERATING ELECTRICAL CHARACTERISTICS T A = 25 o C V S = ±5.V unlss othrwis spcifid 2724E 2724 Paramtr Symbol Min Typ Max Min Typ Max Unit Tst Conditions Supply Voltag VS ±3.25 ±5. ±3.25 ±5. V Dual Supply V+ 6.5 1. 6.5 1. V Singl Supply Initial Input Offst Voltag 1 VOS i 25 1 4 15 µv RS 1KΩ Offst Voltag Program Rang 2 VOS ±5 ±7 ±.5 ±2 mv Programmd Input Offst VOS 25 1 4 15 µv At usr spcifid Voltag Error 3 targt offst voltag Total Input Offst Voltag 4 VOST 25 1 4 15 µv At usr spcifid targt offst voltag Input Offst Currnt 5 IOS.1 1.1 1 pa TA = 25 C 24 24 pa C TA +7 C Input Bias Currnt 5 IB.1 1.1 1 pa TA = 25 C 24 24 pa C TA +7 C Input Voltag Rang 6 VIR -.3 5.3 -.3 5.3 V V+ = +5V -2.8 +2.8-2.8 +2.8 V VS = ±2.5V Input Rsistanc RIN 1 14 1 14 Ω Input Offst Voltag Drift 7 TCVOS 5 5 µv/ C RS 1KΩ Initial Powr Supply PSRR i 85 85 db RS 1KΩ Rjction Ratio 8 Initial Common Mod CMRR i 9 9 db RS 1KΩ Rjction Ratio 8 Larg Signal Voltag Gain AV 15 15 V/mV RL =1KΩ V/mV C TA +7 C VO low -4.998-4.99-4.998-4.99 V RL =1MΩ V =5V Output Voltag Rang VO high 4.99 4.998 4.99 4.998 V C TA +7 C VO low -4.96-4.9-4.96-4.9 V RL =1KΩ VO high 4.9 4.95 4.9 4.95 V C TA +7 C Output Short Circuit Currnt ISC 15 15 ma * NOTES 1 through 9, s sction titld "Dfinitions and Dsign Nots". ALD2724E/ALD2724 Advancd Linar Dvics 3 of 13
OPERATING ELECTRICAL CHARACTERISTICS (cont'd) T A = 25 o C V S = ±5.V unlss othrwis spcifid 2724E 2724 Paramtr Symbol Min Typ Max Min Typ Max Unit Tst Conditions Supply Currnt IS 5. 6.5 5. 6.5 ma VIN = V No Load Powr Dissipation PD 65 65 mw VS = ±2.5V Input Capacitanc CIN 1 1 pf Maximum Load Capacitanc CL 4 4 pf Gain = 1 4 4 pf Gain = 5 Equivalnt Input Nois Voltag n 26 26 nv/ Hz f = 1KHz Equivalnt Input Nois Currnt in.6.6 fa/ Hz f =1Hz Bandwidth BW 2.1 2.1 MHz Slw Rat SR 5. 5. V/µs AV = +1 RL = 2KΩ Ris tim tr.1.1 µs RL = 2KΩ Ovrshoot Factor 15 15 % RL=2KΩ CL=1pF Sttling Tim ts 2 2 µs.1% AV = -1 RL= 5KΩ CL = 5pF Channl Sparation CS 14 14 db AV = 1 T A = 25 o C V S = ±5.V unlss othrwis spcifid 2724E 2724 Paramtr Symbol Min Typ Max Min Typ Max Unit Tst Conditions Avrag Long Trm Input Offst VOS.2.2 µv/ Voltag Stability 9 tim 1 hrs Initial VE Voltag VE1 i, VE2 i 1.4 2.5 V Programmabl Chang of VE1, VE2 1.5 2..5 V VE Rang Programmd VE Voltag Error (VE1-VE2).1.1 % VE Pin Lakag Currnt ib -5-5 µa * NOTES 1 through 9, s sction titld "Dfinitions and Dsign Nots". ALD2724E/ALD2724 Advancd Linar Dvics 4 of 13
OPERATING ELECTRICAL CHARACTERISTICS (cont'd) V S = ±5.V -55 C T A +125 C unlss othrwis spcifid 2724E 2724 Paramtr Symbol Min Typ Max Min Typ Max Unit Tst Conditions Initial Input offst Voltag VOS i.7.7 mv RS 1KΩ Input Offst Currnt IOS 2. 2. na Input Bias Currnt IB 2. 2. na Initial Powr Supply PSRR i 85 85 db RS 1KΩ Rjction Ratio 8 Initial Common Mod CMRR i 97 97 db RS 1KΩ Rjction Ratio 8 Larg Signal Voltag Gain AV 1 25 1 25 V/mV RL = 1KΩ Output Voltag Rang VO low -4.9-4.8-4.9-4.8 V VO high 4.8 4.9 4.8 4.9 V RL = 1KΩ ALD2724E/ALD2724 Advancd Linar Dvics 5 of 13
DEFINITIONS AND DESIGN NOTES: 1. Initial Input Offst Voltag is th initial offst voltag of th ALD2724E/ALD2724 oprational amplifir whn shippd from th factory. Th dvic has bn pr-programmd and tstd for programmability. 2. Offst Voltag Program Rang is th rang of adjustmnt of usr spcifid targt offst voltag. This is typically an adjustmnt in ithr th positiv or th ngativ dirction of th input offst voltag from an initial input offst voltag. Th input offst programming pins, VE1A/VE1B or VE2A/VE2B, chang th input offst voltag in th ngativ or positiv dirction, for ach of th amplifirs, A or B rspctivly. Usr spcifid targt offst voltag can b any offst voltag within this programming rang. 3. Programmd Input Offst Voltag Error is th final offst voltag rror aftr programming whn th Input Offst Voltag is at targt Offst Voltag. This paramtr is sampl tstd. 4. Total Input Offst Voltag is th sam as Programmd Input Offst Voltag, corrctd for systm offst voltag rror. Usually this is an all inclusiv systm offst voltag, which also includs offst voltag contributions from input offst voltag, PSRR, CMRR, TCVOS and nois. It can also includ rrors introducd by xtrnal componnts, at a systm lvl. Programmd Input Offst Voltag and Total Input Offst Voltag is not ncssarily zro offst voltag, but an offst voltag st to compnsat for othr systm rrors as wll. This paramtr is sampl tstd. 5. Th Input Offst and Bias Currnts ar ssntially input protction diod rvrs bias lakag currnts. This low input bias currnt assurs that th analog signal from th sourc will not b distortd by it. For applications whr sourc impdanc is vry high, it may b ncssary to limit nois and hum pickup through propr shilding. 6. Input Voltag Rang is dtrmind by two paralll complmntary input stags that ar summd intrnally, ach stag having a sparat input offst voltag. Whil Total Input Offst Voltag can b trimmd to a dsird targt valu, it is ssntial to not that this trimming occurs at only on usr slctd input bias voltag. Dpnding on th slctd input bias voltag rlativ to th powr supply voltags, offst voltag trimming may affct on or both input stags. For th ALD2724E/ ALD2724, th switching point btwn th two stags occurs at approximatly 1.5V abov ngativ supply voltag. 7. Input Offst Voltag Drift is th avrag chang in Total Input Offst Voltag as a function of ambint tmpratur. This paramtr is sampl tstd. 8. Initial PSRR and initial CMRR spcifications ar providd as rfrnc information. Aftr programming, rror contribution to th offst voltag from PSRR and CMRR is st to zro undr th spcific powr supply and common mod conditions, and bcoms part of th Programmd Input Offst Voltag Error. 9. Avrag Long Trm Input Offst Voltag Stability is basd on input offst voltag shift through oprating lif tst at 125 C xtrapolatd to TA = 25 C, assuming activation nrgy of 1.V. This paramtr is sampl tstd. ADDITIONAL DESIGN NOTES: A. Th ALD2724E/ALD2724 is intrnally compnsatd for unity gain stability using a novl schm which producs a singl pol rol off in th gain charactristics whil providing mor than 7 dgrs of phas margin at unity gain frquncy. A unity gain buffr using th ALD2724E/ALD2724 will typically driv 4pF of xtrnal load capacitanc. B. Th ALD2724E/ALD2724 has complmntary p-channl and n-channl input diffrntial stags connctd in paralll to accomplish rail-to-rail input common mod voltag rang. Th switching point btwn th two diffrntial stags is 1.5V abov ngativ supply voltag. For applications such as invrting amplifirs or non-invrting amplifirs with a gain largr than 2.5 (5V opration), th common mod voltag dos not mak xcursions blow this switching point. Howvr, this switching dos tak plac if th oprational amplifir is connctd as a railto-rail unity gain buffr and th dsign must allow for input offst voltag variations. C. Th output stag consists of class AB complmntary output drivrs. Th oscillation rsistant fatur, combind with th railto-rail input and output fatur, maks th ALD2724E/ ALD2724 an ffctiv analog signal buffr for high sourc impdanc snsors, transducrs, and othr circuit ntworks. D. Th ALD2724E/ALD2724 has static discharg protction. Howvr, car must b xrcisd whn handling th dvic to avoid strong static filds that may dgrad a diod junction, causing incrasd input lakag currnts. Th usr is advisd to powr up th circuit bfor, or simultanously with, any input voltags applid and to limit input voltags not to xcd.3v of th powr supply voltag lvls. E. VExx ar high impdanc trminals, as th intrnal bias currnts ar st vry low to a fw microamprs to consrv powr. For som applications, ths trminals may nd to b shildd from xtrnal coupling sourcs. For xampl, digital signals running narby may caus unwantd offst voltag fluctuations. Car during th printd circuit board layout, to plac ground tracs around ths pins and to isolat thm from digital lins, will gnrally liminat such coupling ffcts. In addition, optional dcoupling capacitors of 1pF or gratr valu can b addd to VExx trminals. F. Th ALD2724E/ALD2724 is dsignd for us in low voltag, micropowr circuits. Th maximum oprating voltag during normal opration should rmain blow 1V at all tims. Car should b takn to insur that th application in which th dvic is usd dos not xprinc any positiv or ngativ transint voltags that will caus any of th trminal voltags to xcd this limit. G. All inputs or unusd pins xcpt VExx pins should b connctd to a supply voltag such as Ground so that thy do not bcom floating pins, sinc input impdanc at ths pins is vry high. If any of ths pins ar lft undfind, thy may caus unwantd oscillation or intrmittnt xcssiv currnt drain. As ths dvics ar built with CMOS tchnology, normal oprating and storag tmpratur limits, ESD and latchup handling prcautions prtaining to CMOS dvic handling should b obsrvd. ALD2724E/ALD2724 Advancd Linar Dvics 6 of 13
TYPICAL PERFORMANCE CHARACTERISTICS COMMON MODE INPUT VOLTAGE RANGE (V) ±7 ±6 ±5 ±4 ±3 COMMON MODE INPUT VOLTAGE RANGE AS A FUNCTION OF SUPPLY VOLTAGE T A = 25 C ±2 ±2 ±3 ±4 ±5 ±6 ±7 SUPPLY VOLTAGE (V) OPEN LOOP VOLTAGE GAIN (V/mV) OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF SUPPLY VOLTAGE AND TEMPERATURE 1 } -55 C 1 1 1 } +25 C } +125 C ±2 ±4 ±6 SUPPLY VOLTAGE (V) R L = 1KΩ R L = 5KΩ ±8 INPUT BIAS CURRENT (pa) 1 1 1 1 1. INPUT BIAS CURRENT AS A FUNCTION OF AMBIENT TEMPERATURE V S = ±5.V SUPPLY CURRENT (ma) 8 7 6 5 4 3 2 1 SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE INPUTS GROUNDED OUTPUT UNLOADED T A = -55 C -25 C +25 C +8 C +125 C.1-5 -25 25 5 75 1 125 ±1 ±2 ±3 ±4 ±5 ±6 ±7 AMBIENT TEMPERATURE ( C) SUPPLY VOLTAGE (V) CHANGE IN INPUT OFFSET VOLTAGE VOS (mv) ADJUSTMENT IN INPUT OFFSET VOLTAGE AS A FUNCTION OF CHANGE IN VE1 AND VE2 1 8 6 4 2-2 -4-6 -8-1 VE2 VE1 OPEN LOOP VOLTAGE GAIN (db) 12 1 8 6 4 2-2 OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF FREQUENCY V S = ±5.V T A = 25 C 45 9 135 18 PHASE SHIFT IN DEGREES.5 1. 1.5 2. 2.5 3. CHANGE IN VE1 AND VE2 (V) 1 1 1 1K 1K 1K 1M 1M FREQUENCY (Hz) ALD2724E/ALD2724 Advancd Linar Dvics 7 of 13
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd) OUTPUT VOLTAGE SWING (V) ±7 ±6 ±5 ±4 ±3 ±2 OUTPUT VOLTAGE SWING AS A FUNCTION OF SUPPLY VOLTAGE -55 C T A 125 C R L = 1KΩ R L = 1KΩ R L = 2KΩ 5V/div 5V/div LARGE - SIGNAL TRANSIENT RESPONSE V S = ±5.V T A = 25 C R L = 1KΩ C L = 5pF 2µs/div ±1 ±2 ±3 ±4 ±5 ±6 ±7 SUPPLY VOLTAGE (V) 1 OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF LOAD RESISTANCE SMALL - SIGNAL TRANSIENT RESPONSE OPEN LOOP VOLTAGE GAIN (V/mV) 1 1 V S = ±5.V T A = 25 C 1mV/div V S = ± 5.V T A = 25 C R L = 1.KΩ C L = 5pF 1 5mV/div 1µs/div 1K 1K 1K 1K LOAD RESISTANCE (Ω) 1 DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE BEFORE AND AFTER PERCENTAGE OF UNITS (%) 8 6 4 2 EXAMPLE B: V OST AFTER EPAD PROGRAMMING V OST TARGET = -75µV EXAMPLE A: V OST AFTER EPAD PROGRAMMING V OST TARGET =.µv V OST BEFORE EPAD PROGRAMMING -25-2 -15-1 -5 5 1 15 2 25 TOTAL INPUT OFFSET VOLTAGE (µv) ALD2724E/ALD2724 Advancd Linar Dvics 8 of 13
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd) EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN SUPPLY VOLTAGE (µv) 5 4 3 2 1 TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE EXAMPLE A: V OS EPAD PROGRAMMED AT V SUPPLY = +5V PSRR = 8 db EXAMPLE B: V OS EPAD PROGRAMMED AT V SUPPLY = +8V 1 2 3 4 5 6 7 8 9 1 SUPPLY VOLTAGE (V) EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE (µv) 5 4 3 2 1 THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE EXAMPLE B: V OS EPAD PROGRAMMED AT V IN = -4.3V EXAMPLE A: V OS EPAD PROGRAMMED AT V IN = V V SUPPLY = ±5V CMRR = 8dB EXAMPLE C: V OS EPAD PROGRAMMED AT V IN = +5V -5-4 -3-2 -1 1 2 3 4 5 COMMON MODE VOLTAGE (V) EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE (µv) 5 4 3 2 1 EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE FOR A COMMON MODE VOLTAGE RANGE OF.5V CMRR = 8dB COMMON MODE VOLTAGE RANGE OF.5V V OS EPAD PROGRAMMED AT COMMON MODE VOLTAGE OF.25V -.5 -.4 -.3 -.2 -.1..1.2.3.4.5 COMMON MODE VOLTAGE (V) ALD2724E/ALD2724 Advancd Linar Dvics 9 of 13
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd) APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING Exampls of applications whr accumulatd total input offst voltag from various contributing sourcs is minimizd undr diffrnt sts of usr-spcifid oprating conditions 25 25 TOTAL INPUT OFFSET VOLTAGE (µv) 2 15 1 5-5 -1-15 -2-25 V OS BUDGET AFTER + X V OS BUDGET BEFORE TOTAL INPUT OFFSET VOLTAGE (µv) 2 15 1 5-5 -1-15 -2-25 V OS BUDGET AFTER + X V OS BUDGET BEFORE EXAMPLE A EXAMPLE B 25 25 TOTAL INPUT OFFSET VOLTAGE (µv) 2 15 1 5-5 -1-15 -2-25 V OS BUDGET BEFORE + EXAMPLE C X V OS BUDGET AFTER TOTAL INPUT OFFSET VOLTAGE (µv) 2 15 1 5-5 -1-15 -2-25 V OS BUDGET AFTER + EXAMPLE D X V OS BUDGET BEFORE + X Dvic input V OS PSRR quivalnt V OS CMRR quivalnt V OS T A quivalnt V OS Nois quivalnt V OS Extrnal Error quivalnt V OS Total Input V OS aftr EPAD Programming ALD2724E/ALD2724 Advancd Linar Dvics 1 of 13
SOIC-14 PACKAGE DRAWING 14 Pin Plastic SOIC Packag Millimtrs Inchs E Dim A Min Max Min Max 1.35 1.75.53.69 A 1.1.25.4.1 S (45 ) b C.35.18.45.25.14.7.18.1 D-14 8.55 8.75.336.345 E 3.5 4.5.14.16 1.27 BSC.5 BSC D H 5.7 6.3.224.248 L.6.937.24.37 ø 8 8 A S.25.5.1.2 A 1 b S (45 ) H C L ø ALD2724E/ALD2724 Advancd Linar Dvics 11 of 13
PDIP-14 PACKAGE DRAWING 14 Pin Plastic DIP Packag Millimtrs Inchs E E1 Dim A A 1 Min Max Min Max 3.81 5.8.15.2.38 1.27.15.5 A 2 1.27 2.3.5.8 b.89 1.65.35.65 b 1.38.51.15.2 c.2.3.8.12 D-14 17.27 19.3.68.76 E 5.59 7.11.22.28 S D E 1 1 7.62 2.29 7.37 8.26 2.79 7.87.3.9.29.325.11.31 A 2 A L S-14 2.79 1.2 3.81 2.3.11.4.15.8 A 1 L ø 15 15 b b 1 c 1 ø ALD2724E/ALD2724 Advancd Linar Dvics 12 of 13
CERDIP-14 PACKAGE DRAWING 14 Pin CERDIP Packag Millimtrs Inchs E E 1 Dim A A 1 Min Max Min Max 3.55 5.8.14.2 1.27 2.16.5.85 b.97 1.65.38.65 b 1.36.58.14.23 C.2.38.8.15 D-14 -- 19.94 --.785 D E 5.59 7.87.22.31 E 1 7.73 8.26.29.325 s A 1 1 2.54 BSC 7.62 BSC.1 BSC.3 BSC A L 3.81 5.8.15.2 L b L 2 b 1 L 1 L 1 L 2 S 3.18.38 -- -- 1.78 2.49.125.15 -- --.7.98 Ø 15 15 C 1 ø ALD2724E/ALD2724 Advancd Linar Dvics 13 of 13