Single-Supply, Rail-to-Rail Low Power FET-Input Op Amp AD822

Single-Supply, Rail-to-Rail Low Power FET-Input Op Amp AD FEATURES True single-supply operation Output swings rail-to-rail Input voltage range extends below ground Single-supply capability from 3 V to 36 V Dual-supply capability from ±.5 V to ± V High load drive Capacitive load drive of 35 pf, G = Minimum output current of 5 ma Excellent ac performance for low power µa maximum quiescent current per amplifier Unity gain bandwidth:. MHz Slew rate of 3. V/ms Good dc performance µv maximum input offset voltage µv/ C typical offset voltage drift 5 pa maximum input bias current Low noise 3 nv/ Hz @ khz No phase inversion APPLICATIONS Battery-powered precision instrumentation Photodiode preamps Active filters -bit to -bit data acquisition systems Medical instrumentation Low power references and regulators FUNCTIONAL BLOCK DIAGRAM OUT IN IN V 3 AD 7 6 5 V OUT IN IN Figure. -Lead PDIP (N Suffix); -Lead MSOP (RM Suffix); and -Lead SOIC (R Suffix) GENERAL DESCRIPTION The AD is a dual precision, low power FET input op amp that can operate from a single supply of 3. V to 36 V or dual supplies of ±.5 V to ± V. It has true single-supply capability with an input voltage range extending below the negative rail, allowing the AD to accommodate input signals below ground in the single-supply mode. Output voltage swing extends to within mv of each rail, providing the maximum output dynamic range. INPUT VOLTAGE NOISE (nv/ Hz) 7- k k FREQUENCY (Hz) Figure. Input Voltage Noise vs. Frequency Offset voltage of µv maximum, offset voltage drift of µv/ C, input bias currents below 5 pa, and low input voltage noise provide dc precision with source impedances up to a GΩ.. MHz unity gain bandwidth, 93 db THD at khz, and 3 V/µs slew rate are provided with a low supply current of µa per amplifier. 7- (continued on Page 3) Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: 7.39.7 www.analog.com Fax: 7.6.33 5 Analog Devices, Inc. All rights reserved.

TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... Specifications... Absolute Maximum Ratings... Maximum Power Dissipation... ESD Caution... Typical Performance Characteristics... Input Characteristics... Output Characteristics... Applications... Single-Supply Voltage-to-Frequency Converter... Single-Supply Programmable Gain Instrumentation Amplifier... 3 V, Single-Supply Stereo Headphone Driver... Low Dropout Bipolar Bridge Driver... Outline Dimensions... Ordering Guide... 3 Application Notes... REVISION HISTORY /5 Rev. E to Rev. F Updated Format...Universal Changes to Outline Dimensions... Updated Ordering Guide... /3 Data sheet changed from Rev. D to Rev. E Edits to Specifications... Edits to Figure... 6 Updated Outline Dimensions... 7 / Data sheet changed from Rev. C to Rev. D Edits to Features... Edits to Ordering Guide... 6 Updated SOIC Package Outline... 7 / Data sheet changed from Rev. B to Rev. C All Figures Updated...Global Edits to Features... Updated All Package Outlines... 7 7/ Data sheet changed from Rev. A to Rev. B All Figures Updated...Global CERDIP References Removed..., 6, and Additions to Product Description... -Lead SOIC and -Lead MSOP Diagrams Added... Deletion of ADS Column... Edits to Absolute Maximum Ratings and Ordering Guide...6 Removed Metalization Photograph...6 Rev. F Page of

GENERAL DESCRIPTION (continued from Page ) The AD drives up to 35 pf of direct capacitive load as a follower and provides a minimum output current of 5 ma. This allows the amplifier to handle a wide range of load conditions. Its combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for the single-supply user. The AD is available in two performance grades. The A grade and B grade are rated over the industrial temperature range of C to 5 C. The AD is offered in three varieties of -lead packages: PDIP, MSOP, and SOIC. 5V V (GND) V OUT.............................. 9. V V µs %.............................. V Figure 3. Gain-of- Amplifier; VS = 5,, VIN =.5 V Sine Centered at.5 V, RL = Ω 7-3 Rev. F Page 3 of

SPECIFICATIONS VS =, 5 V @ TA = 5 C, VCM = V, VOUT =. V, unless otherwise noted. Table. AD A Grade AD B Grade Parameter Condition Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset.... mv Maximum Offset Overtemperature.5..5.9 mv Offset Drift µv/ C Input Bias Current VCM = V to V 5 pa at TMAX.5 5.5.5 na Input Offset Current pa at TMAX.5.5 na Open-Loop Gain VO =. V to V RL = kω 5 5 V/mV TMIN to TMAX V/mV RL = kω 5 5 V/mV TMIN to TMAX V/mV RL = kω 5 3 5 3 V/mV TMIN to TMAX V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise. Hz to Hz µv p-p f = Hz 5 5 nv/ Hz f = Hz nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise. Hz to Hz fa p-p f = khz.. fa/ Hz Harmonic Distortion RL = kω to.5 V f = khz VO =.5 V to.75 V 93 93 db DYNAMIC PERFORMANCE Unity Gain Frequency.. MHz Full Power Response VO p-p =.5 V khz Slew Rate 3 3 V/µs Settling Time to.% VO =. V to.5 V.. µs to.%.. µs MATCHING CHARACTERISTICS Initial Offset..5 mv Maximum Offset overtemperature.6.3 mv Offset Drift 3 3 µv/ C Input Bias Current pa Crosstalk @ f = khz RL = 5 kω 3 3 db f = khz 93 93 db INPUT CHARACTERISTICS Input Voltage Range.. V TMIN to TMAX.. V Common-Mode Rejection Ratio (CMRR) VCM = V to V 66 69 db TMIN to TMAX VCM = V to V 66 66 db Rev. F Page of

AD A Grade AD B Grade Parameter Condition Min Typ Max Min Typ Max Unit Input Impedance Differential 3.5 3.5 Ω pf Common Mode 3. 3. Ω pf OUTPUT CHARACTERISTICS Output Saturation Voltage VOL VEE ISINK = µa 5 7 5 7 mv TMIN to TMAX mv VCC VOH ISOURCE = µa mv TMIN to TMAX mv VOL VEE ISINK = ma 55 55 mv TMIN to TMAX mv VCC VOH ISOURCE = ma mv TMIN to TMAX 6 6 mv VOL VEE ISINK = 5 ma 3 5 3 5 mv TMIN to TMAX mv VCC VOH ISOURCE = 5 ma 5 5 mv TMIN to TMAX 9 9 mv Operating Output Current 5 5 ma TMIN to TMAX ma Capacitive Load Drive 35 35 pf POWER SUPPLY Quiescent Current TMIN to TMAX..6..6 ma Power Supply Rejection VS = 5 V to 5 V 66 7 db TMIN to TMAX 66 7 db This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (Vs V) to Vs. Common-mode effort voltage is typically less than 5 mv with the common-mode voltage set at V below the positive supply. VOL VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). VS = ±5 V @ TA = 5 C, VCM = V, VOUT = V, unless otherwise noted. Table. AD A Grade AD B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset.... mv Maximum Offset Overtemperature.5.5.5 mv Offset Drift µv/ C Input Bias Current VCM = 5 V to V 5 pa at TMAX.5 5.5.5 na Input Offset Current pa at TMAX.5.5 na Open-Loop Gain VO = V to V RL = kω V/mV TMIN to TMAX V/mV RL = kω 5 5 V/mV TMIN to TMAX V/mV RL = kω 3 3 V/mV TMIN to TMAX V/mV Rev. F Page 5 of

AD A Grade AD B Grade Parameter Conditions Min Typ Max Min Typ Max Unit NOISE/HARMONIC PERFORMANCE Input Voltage Noise. Hz to Hz µv p-p f = Hz 5 5 nv/ Hz f = Hz nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise. Hz to Hz fa p-p f = khz.. fa/ Hz Harmonic Distortion RL = kω f = khz VO = ±.5 V 93 93 db DYNAMIC PERFORMANCE Unity Gain Frequency.9.9 MHz Full Power Response VO p-p = 9 V 5 5 khz Slew Rate 3 3 V/µs Settling Time to.% VO = V to ±.5 V.. µs to.%.. µs MATCHING CHARACTERISTICS Initial Offset..5 mv Maximum Offset Overtemperature 3 mv Offset Drift 3 3 µv/ C Input Bias Current 5 pa Crosstalk @ f = khz RL = 5 kω 3 3 db f = khz 93 93 db INPUT CHARACTERISTICS Input Voltage Range 5. 5. V TMIN to TMAX 5. 5. V Common-Mode Rejection Ratio (CMRR) VCM = 5 V to V 66 69 db TMIN to TMAX VCM = 5 V to V 66 66 db Input Impedance Differential 3.5 3.5 Ω pf Common Mode 3. 3. Ω pf OUTPUT CHARACTERISTICS Output Saturation Voltage VOL VEE ISINK = µa 5 7 5 7 mv TMIN to TMAX mv VCC VOH ISOURCE = µa mv TMIN to TMAX mv VOL VEE ISINK = ma 55 55 mv TMIN to TMAX mv VCC VOH ISOURCE = ma mv TMIN to TMAX 6 6 mv VOL VEE ISINK = 5 ma 3 5 3 5 mv TMIN to TMAX mv VCC VOH ISOURCE = 5 ma 5 5 mv TMIN to TMAX 9 9 mv Operating Output Current 5 5 ma TMIN to TMAX ma Capacitive Load Drive 35 35 pf Rev. F Page 6 of

AD A Grade AD B Grade Parameter Conditions Min Typ Max Min Typ Max Unit POWER SUPPLY Quiescent Current TMIN to TMAX.3.6.3.6 ma Power Supply Rejection VS = 5 V to 5 V 66 7 db TMIN to TMAX 66 7 db This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (Vs V) to Vs. Common-mode effort voltage is typically less than 5 mv with the common-mode voltage set at V below the positive supply. VOL VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). VS = ±5 V @ TA = 5 C, VCM = V, VOUT = V, unless otherwise noted. Table 3. AD A Grade AD B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset..3.5 mv Maximum Offset Overtemperature.5 3.5.5 mv Offset Drift µv/ C Input Bias Current VCM = V 5 pa VCM = V pa at TMAX VCM = V.5 5.5.5 na Input Offset Current pa at TMAX.5.5 na Open-Loop Gain VO = V to V RL = kω 5 5 V/mV TMIN to TMAX 5 5 V/mV RL = kω 5 5 V/mV TMIN to TMAX V/mV RL = kω 3 5 3 5 V/mV TMIN to TMAX V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise. Hz to Hz µv p-p f = Hz 5 5 nv/ Hz f = Hz nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise. Hz to Hz fa p-p f = khz.. fa/ Hz Harmonic Distortion RL = kω f = khz VO = ± V 5 5 db DYNAMIC PERFORMANCE Unity Gain Frequency.9.9 MHz Full Power Response VO p-p = V 5 5 khz Slew Rate 3 3 V/µs Settling Time to.% VO = V to ± V.. µs to.%.5.5 µs Rev. F Page 7 of

AD A Grade AD B Grade Parameter Conditions Min Typ Max Min Typ Max Unit MATCHING CHARACTERISTICS Initial Offset 3 mv Maximum Offset Overtemperature.5 mv Offset Drift 3 3 µv/ C Input Bias Current 5 pa Crosstalk @ f = khz RL = 5 kω 3 3 db f = khz 93 93 db INPUT CHARACTERISTICS Input Voltage Range 5. 5. V TMIN to TMAX 5. 5. V Common-Mode Rejection Ratio (CMRR) VCM = 5 V to V 7 7 9 db TMIN to TMAX VCM = 5 V to V 7 7 db Input Impedance Differential 3.5 3.5 Ω pf Common Mode 3. 3. Ω pf OUTPUT CHARACTERISTICS Output Saturation Voltage VOL VEE ISINK = µa 5 7 5 7 mv TMIN to TMAX mv VCC VOH ISOURCE = µa mv TMIN to TMAX mv VOL VEE ISINK = ma 55 55 mv TMIN to TMAX mv VCC VOH ISOURCE = ma mv TMIN to TMAX 6 6 mv VOL VEE ISINK = 5 ma 3 5 3 5 mv TMIN to TMAX mv VCC VOH ISOURCE = 5 ma 5 5 mv TMIN to TMAX 9 9 mv Operating Output Current ma TMIN to TMAX 5 5 ma Capacitive Load Drive 35 35 pf POWER SUPPLY Quiescent Current TMIN to TMAX... ma Power Supply Rejection VS = 5 V to 5 V 7 7 db TMIN to TMAX 7 7 db This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (Vs V) to Vs. Common-mode effort voltage is typically less than 5 mv with the common-mode voltage set at V below the positive supply. VOL VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). VS =, 3 V @ TA = 5 C, VCM = V, VOUT =. V, unless otherwise noted. Table. Parameter Conditions Typ Unit DC PERFORMANCE Initial Offset. mv Maximum Offset Overtemperature.5 mv Offset Drift µv/ C Input Bias Current VCM = V to V pa at TMAX.5 na Input Offset Current pa at TMAX.5 na Rev. F Page of

Parameter Conditions Typ Unit Open-Loop Gain VO =. V to V RL = kω V/mV RL = kω 5 V/mV RL = kω 3 V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise μv p-p. Hz to Hz 5 nv/ Hz f = Hz nv/ Hz f = Hz 6 nv/ Hz f = khz 3 nv/ Hz f = khz Input Current Noise. Hz to Hz fa p-p f = khz. fa/ Hz Harmonic Distortion RL = kω to.5 V f = khz VO = ±.5 V 9 db DYNAMIC PERFORMANCE Unity Gain Frequency.5 MHz Full Power Response VO p-p =.5 V khz Slew Rate 3 V/µs Settling Time to.% VO =. V to.5 V µs to.%. µs MATCHING CHARACTERISTICS Offset Drift µv/ C Crosstalk @ f = khz RL = 5 kω 3 db f = khz 93 db INPUT CHARACTERISTICS Common-Mode Rejection Ratio (CMRR) VCM = V to V 7 db Input Impedance Differential 3.5 Ω pf Common Mode 3. Ω pf OUTPUT CHARACTERISTICS Output Saturation Voltage VOL VEE ISINK = µa 5 mv VCC VOH ISOURCE = µa mv VOL VEE ISINK = ma mv VCC VOH ISOURCE = ma mv VOL VEE ISINK = ma mv VCC VOH ISOURCE = ma 5 mv Capacitive Load Drive 35 pf POWER SUPPLY Quiescent Current. ma Power Supply Rejection VS = 3 V to 5 V db VOL VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. F Page 9 of

ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage Internal Power Dissipation PDIP (N) SOIC (R) Input Voltage Output Short Circuit Duration Differential Input Voltage Storage Temperature Range (N) Storage Temperature Range (R, RM) Operating Temperature Range AD A Grade and B Grade Lead Temperature Range (Soldering, 6 sec) -lead PDIP package: θja = 9 C/Ω. -lead SOIC package: θja = 6 C/Ω. -lead MSOP package: θja = 9 C/Ω. Rating ± V Observe Derating Curves Observe Derating Curves (VS. V) to ( V VS) Indefinite ±3 V 65 C to 5 C 65 C to 5 C C to 5 C 6 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD is limited by the associated rise in junction temperature. For plastic packages, the maximum safe junction temperature is 5 C. If these maximums are exceeded momentarily, proper circuit operation is restored as soon as the die temperature is reduced. Leaving the device in the overheated condition for an extended period can result in device burnout. To ensure proper operation, it is important to observe the derating curves shown in Figure 7. While the AD is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. With power supplies ± V (or less) at an ambient temperature of 5 C or less, if the output node is shorted to a supply rail, then the amplifier is not destroyed, even if this condition persists for an extended period. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F Page of

TYPICAL PERFORMANCE CHARACTERISTICS 7 5 6 V S = V, 5V NUMBER OF UNITS 5 3 INPUT BIAS CURRENT (pa) V S = ±5V V S = V, 5V AND ±5V % IN BIN.5. 6.3.....3..5 OFFSET VOLTAGE (mv) Figure. Typical Distribution of Offset Voltage (39 Units) 6 V S = ±5V V S = ±5V 6 6 OFFSET VOLTAGE DRIFT (µv/ C) Figure 5. Typical Distribution of Offset Voltage Drift ( Units) 5 5 7-7-5 5 5 3 3 5 COMMON-MODE VOLTAGE (V) Figure 7. Input Bias Current vs. Common-Mode Voltage; VS = 5 V, V, and VS = ±5 V INPUT BIAS CURRENT (pa) k. 6 6 COMMON-MODE VOLTAGE (V) Figure. Input Bias Current vs. Common-Mode Voltage; VS = ±5 V k k 7-7 7- NUMBER OF UNITS 35 3 5 5 5 3 5 6 7 9 INPUT BIAS CURRENT (pa) Figure 6. Typical Distribution of Input Bias Current (3 Units) 7-6 INPUT BIAS CURRENT (pa) k. 6 TEMPERATURE ( C) Figure 9. Input Bias Current vs. Temperature; VS = 5 V, VCM = 7-9 Rev. F Page of

M OPEN-LOOP GAIN (V/V) M k V S = V, 5V V S = ±5V V S = V, 3V INPUT VOLTAGE (µv) POS RAIL R L = kω POS RAIL R L = kω POS RAIL NEG RAIL NEG RAIL k k k k LOAD RESISTANCE (Ω) Figure. Open-Loop Gain vs. Load Resistance M 7- R L = kω NEG RAIL 6 3 OUTPUT VOLTAGE FROM SUPPLY RAILS (mv) Figure 3. Input Effort Voltage with Output Voltage Within 3 mv of Either Supply Rail for Various Resistive Loads; VS = ±5 V k 7-3 OPEN-LOOP GAIN (V/V) R L = kω V S = ±5V M V S = V, 5V R L = kω V S = ±5V V S = V, 5V k V S = ±5V R L = 6Ω V S = V, 5V k 6 6 TEMPERATURE ( C) Figure. Open-Loop Gain vs. Temperature 3 7- INPUT VOLTAGE NOISE (nv Hz) k k FREQUENCY (Hz) 5 Figure. Input Voltage Noise vs. Frequency R L = kω A CL = 7- INPUT VOLTAGE (V) R L = kω R L = kω THD (db) 6 7 V S = ±5V; V OUT = V p-p V S = V, 3V; V OUT =.5V p-p R L = 6Ω 3 6 6 OUTPUT VOLTAGE (V) Figure. Input Error Voltage vs. Output Voltage for Resistive Loads 7-9 V S = ±5V; V OUT = 9V p-p V S = V, 5V; V OUT =.5V p-p k k k FREQUENCY (Hz) Figure 5. Total Harmonic Distortion (THD) vs. Frequency 7-5 Rev. F Page of

9 OPEN-LOOP GAIN (db) 6 R L = kω C L = pf GAIN PHASE k k k M M FREQUENCY (Hz) Figure 6. Open-Loop Gain and Phase Margin vs. Frequency 6 PHASE MARGIN IN DEGREES 7-6 COMMON-MODE REJECTION (db) 7 V S = ±5V 6 5 V S = V, 3V V S = V, 5V 3 k k k M FREQUENCY (Hz) Figure 9. Common-Mode Rejection vs. Frequency M 7-9 OUTPUT IMPEDANCE (Ω) k. A CL = V S = ±5V. k k k M M FREQUENCY (Hz) 7-7 COMMON-MODE ERROR VOLTAGE (mv) 5 3 5 C NEGATIVE RAIL 5 C 55 C 55 C POSITIVE RAIL 5 C 3 COMMON-MODE VOLTAGE FROM SUPPLY RAILS (V) 7- OUTPUT SWING FROM TO ±VOLTS Figure 7. Output Impedance vs. Frequency 6 %.%.% ERROR.% % 6 3 5 SETTLING TIME (µs) Figure. Output Swing and Error vs. Settling Time 7- Figure. Absolute Common-Mode Error vs. Common-Mode Voltage from Supply Rails (VS VCM) OUTPUT SATURATION VOLTAGE (mv) V S V OH V OL V S... LOAD CURRENT (ma) Figure. Output Saturation Voltage vs. Load Current 7- Rev. F Page 3 of

OUTPUT SATURATION VOLTAGE (mv) I SOURCE = ma I SINK = ma I SOURCE =ma I SINK =ma I SOURCE =µa I SINK =µa 6 6 TEMPERATURE ( C) Figure. Output Saturation Voltage vs. Temperature 7- POWER SUPPLY REJECTION (db) 9 7 6 5 3 PSRR PSRR k k k M M FREQUENCY (Hz) Figure 5. Power Supply Rejection vs. Frequency 3 7-5 SHORT CIRCUIT CURRENT LIMIT (ma) 7 6 5 3 V S = V, 5V V S = ±5V V S = V, 3V V S = V, 5V V S = ±5V V S = V, 3V OUT 6 6 TEMPERATURE ( C) Figure 3. Short Circuit Current Limit vs. Temperature 7-3 OUTPUT VOLTAGE (V) 5 R L = kω V S = ±5V 5 V S = V, 5V 5 V S = V, 3V k k M M FREQUENCY (Hz) Figure 6. Large Signal Frequency Response 7-6 QUIESCENT CURRENT (µa) 6 6 T = 5 C T = 5 C T = 55 C 6 TOTAL SUPPLY VOLTAGE (V) 3 36 7- TOTAL POWER DISSIPATION (W)... -LEAD PDIP. -LEAD SOIC.6.... -LEAD MSOP.6.. 6 6 AMBIENT TEMPERATURE ( C) 7-7 Figure. Quiescent Current vs. Supply Voltage vs. Temperature Figure 7. Maximum Power Dissipation vs. Temperature for Packages Rev. F Page of

7 9 9 5V 5µs CROSSTALK (db) 3 3 k 3k k 3k k 3k M FREQUENCY (Hz) Figure. Crosstalk vs. Frequency 7- % Figure 3. Large Signal Response Unity Gain Follower; VS = ±5 V, RL = kω mv 5ns 7-3 V S.µF 9 V IN / AD.µF R L pf V OUT Figure 9. Unity Gain Follower 7-9 % 5V µs Figure 33. Small Signal Response Unity Gain Follower; VS =±5 V, RL = kω 7-33 9 V µs 9 % Figure 3. V p-p, 5 khz Sine Wave Input; Unity Gain Follower; RL = 6 Ω, VS = ± 5 V V p-p V IN 3 V s / AD.µF µf CROSS TALK = log V OUT V IN 5kΩ V OUT 7 5kΩ kω V s / AD 6 5 7-3.kΩ.µF µf 7-3 GND % Figure 3. VS = 5 V, V; Unity Gain Follower Response to V to V Step V S.µF V IN / AD R L pf Figure 35. Unity Gain Follower V OUT 7-35 7-3 Figure 3. Crosstalk Test Circuit Rev. F Page 5 of

V IN kω kω V S.µF V OUT mv µs 9 / AD R L pf 7-36 Figure 36. Gain-of-T Inverter GND % 9 V µs Figure 3. VS = 5 V, V; Unity Gain Follower Response to mv Step, Centered mv above Ground, RL = kω 7-3 GND % Figure 37. VS = 5 V, V; Unity Gain Follower Response to V to 5 V Step 7-37 Rev. F Page 6 of

mv µs V µs 9.............................. 9 GND % GND %.............................. Figure 39. VS = 5 V, V; Gain-of- Inverter Response to mv Step, Centered mv below Ground, RL = kω 7-39 V (a) V µs V V µs 9 Vs 9.............................. GND % GND %.............................. Figure. VS = 5 V, V; Gain-of- Inverter Response to.5 V Step, Centered.5 V below Ground, RL = kω 7- V (b) 5mV µs R P 5V 9 V IN V OUT GND % 7-7- Figure. (a) Response with RP = ; VIN from to VS (b) VIN = to VS mv VOUT = to VS RP = 9.9 kω Figure. VS = 3 V, V; Gain-of- Inverter, VIN =.5 V, 5 khz, Sine Wave Centered at.75 V, RL = 6 Ω Rev. F Page 7 of

APPLICATION NOTES INPUT CHARACTERISTICS In the AD, n-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input common-mode voltage extends from. V below VS to V less than VS. Driving the input voltage closer to the positive rail causes a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in Figure 3 and Figure 37) and increased common-mode voltage error as illustrated in Figure. INPUT VOLTAGE NOISE (µv) k k k WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR APPLICATION. RESISTOR JOHNSON NOISE khz Hz The AD does not exhibit phase reversal for input voltages up to and including VS. Figure shows the response of an AD voltage follower to a V to 5 V (VS) square wave input. The input and output are superimposed. The output tracks the input up to VS without phase reversal. The reduced bandwidth above a V input causes the rounding of the output waveform. For input voltages greater than VS, a resistor in series with the AD s noninverting input prevents phase reversal, at the expense of greater input voltage noise. This is illustrated in Figure. Since the input stage uses n-channel JFETs, input current during normal operation is negative; the current flows out from the input terminals. If the input voltage is driven more positive than VS. V, then the input current reverses direction as internal device junctions become forward biased. This is illustrated in Figure 7. A current limiting resistor should be used in series with the input of the AD if there is a possibility of the input voltage exceeding the positive supply by more than 3 mv, or if an input voltage is applied to the AD when ±VS =. The amplifier is damaged if left in that condition for more than seconds. A kω resistor allows the amplifier to withstand up to V of continuous overvoltage and increases the input voltage noise by a negligible amount. Input voltages less than VS are a completely different story. The amplifier can safely withstand input voltages V below the negative supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 V. In addition, the input stage typically maintains picoampere (pa) level input currents across that input voltage range. The AD is designed for 3 nv/ Hz wideband input voltage noise and maintains low noise performance to low frequencies (refer to Figure ). This noise performance, along with the AD s low input current and current noise, means that the AD contributes negligible noise for applications with source resistances greater than kω and signal bandwidths greater than khz. This is illustrated in Figure 3. AMPLIFIER-GENERATED NOISE. k k M M M G G SOURCE IMPEDANCE (Ω) Figure 3. Total Noise vs. Source Impedance OUTPUT CHARACTERISTICS The AD s unique bipolar rail-to-rail output stage swings within 5 mv of the negative supply and mv of the positive supply with no external resistive load. The AD s approximate output saturation resistance is Ω sourcing and Ω sinking. This can be used to estimate output saturation voltage when driving heavier current loads. For instance, when sourcing 5 ma, the saturation voltage to the positive supply rail is mv; when sinking 5 ma, the saturation voltage to the negative rail is mv. The amplifier s open-loop gain characteristic changes as a function of resistive load, as shown in Figure to Figure 3. For load resistances over kω, the AD s input error voltage is virtually unchanged until the output voltage is driven to mv of either supply. If the AD s output is overdriven so as to saturate either of the output devices, the amplifier recovers within μs of its input returning to the amplifier s linear operating region. Direct capacitive loads interact with the amplifier s effective output impedance to form an additional pole in the amplifier s feedback loop, which can cause excessive peaking on the pulse response or loss of stability. Worst case is when the amplifier is used as a unity gain follower. Figure shows the AD s pulse response as a unity gain follower driving 35 pf. This amount of overshoot indicates approximately of phase margin the system is stable, but nearing the edge. Configurations with less loop gain, and as a result less loop bandwidth, are much less sensitive to capacitance load effects. 7-3 Rev. F Page of

mv µs.............................. 9 Figure 6 shows a method for extending capacitance load drive capability for a unity gain follower. With these component values, the circuit drives 5 pf with a % overshoot. V S.µF %.............................. V IN / AD.µF Ω C L V OUT V S Figure. Small Signal Response of AD as Unity Gain Follower Driving 35 pf Figure 5 is a plot of capacitive load that results in a phase margin vs. noise gain for the AD. Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. 7- kω pf Figure 6. Extending Unity Gain Follower Capacitive Load Capability Beyond 35 pf 7-6 5 NOISE GAIN R F R 3 3 k 3k k 3k CAPACITIVE LOAD FOR PHASE MARGIN (pf) R F C L R Figure 5. Capacitive Load Tolerance vs. Noise Gain 7-5 Rev. F Page 9 of

APPLICATIONS SINGLE-SUPPLY VOLTAGE-TO-FREQUENCY CONVERTER The circuit shown in Figure 7 uses the AD to drive a low power timer that produces a stable pulse of width t. The positive going output pulse is integrated by R C and used as one input to the AD that is connected as a differential integrator. The other input (nonloading) is the unknown voltage, VIN. The AD output drives the timer trigger input, closing the overall feedback loop. C5.µF 3 V IN V U REF V 6 REF = 5V 5 R 99kΩ % R 99kΩ % C.µF % V TO.5V FULL SCALE R SCALE ** kω U CMOS 7HCO U3B 3.µF, % C / ADB U3A R3* 6kΩ C3.µF U CMOS 555 R V 6 THR 3 OUT TR 5 7 CV DIS GND NOTES. f OUT = V IN /(V REF t ), t =. R3 C6. = 5kHz F S AS SHOWN.. * = % METAL FILM <5ppm/ C TC. 3. ** = % T FILM <ppm/ C TC.. t = 33µF FOR f OUT = khz @ V IN =.V. Figure 7. Single-Supply Voltage-to-Frequency Converter OUT OUT C.µF Typical AD bias currents of pa allow MΩ range source impedances with negligible dc errors. Linearity errors on the order of.% full scale can be achieved with this circuit. This performance is obtained with a 5 V single supply that delivers less than ma to the entire circuit. SINGLE-SUPPLY PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER The AD can be configured as a single-supply instrumentation amplifier that is able to operate from single supplies down to 3 V or dual supplies up to ±5 V. Using only one AD rather than three separate op amps, this circuit is cost and power efficient. The AD FET inputs pa bias currents minimize offset errors caused by high unbalanced source impedances. 7-7 Table 6. In Amp Performance Parameters VS = 3 V, V VS = 65 V CMRR 7 db db Common-Mode Voltage Range. V to V 5. V to V 3 db BW, G = khz khz G = khz khz tsettling V Step (VS = V, 3 V) µs 5 V (VS = ± 5 V) 5 µs Noise @ f = khz, G = 7 nv/ Hz 7 nv/ Hz G =. µv/ Hz. µv/ Hz ISUPPLY (Total). ma.5 ma.............................. 9 %.............................. V Figure. Pulse Response of In Amp to a 5 mv p-p Input Signal; VS = 5 V, V; Gain = V REF V IN V IN R P kω R 9kΩ R 9kΩ R3 kω R kω R5 9kΩ 5µs R6 9kΩ G = G = G = G = R P kω V S / AD 3.µF 6 / AD 5 R6 (G = ) V OUT = (V IN V IN ) R R5 V REF R5 R6 (G = ) V OUT = (V IN V IN ) R 7 V REF 7- OHMTEK PART # 3 V OUT Figure 9. A Single-Supply Programmable Instrumentation Amplifier 7-9 An array of precision thin-film resistors sets the in amp gain to be either or. These resistors are laser trimmed to ratio match to.% and have a maximum differential TC of 5 ppm/ C. Rev. F Page of

3 V, SINGLE-SUPPLY STEREO HEADPHONE DRIVER The AD exhibits good current drive and THD N performance, even at 3 V single supplies. At khz, total harmonic distortion plus noise (THD N) equals 6 db (.79%) for a 3 mv p-p output signal. This is comparable to other single-supply op amps that consume more power and cannot run on 3 V power supplies. CHANNEL CHANNEL µf MYLAR 95.3kΩ µf MYLAR 3V 95.3kΩ 3 / 7.5kΩ AD.99kΩ kω kω.99kω 6 / 7.5kΩ AD 5.µF HEADPHONES 3Ω IMPEDANCE 7.µF 5µF 5µF Figure 5. 3 V Single-Supply Stereo Headphone Driver In Figure 5, each channel s input signal is coupled via a µf Mylar capacitor. Resistor dividers set the dc voltage at the noninverting inputs so that the output voltage is midway between the power supplies (.5 V). The gain is.5. Each half of the AD can then be used to drive a headphone channel. A 5 Hz high-pass filter is realized by the 5 µf capacitors and the headphones that can be modeled as 3 Ω load resistors to ground. This ensures that all signals in the audio frequency range ( Hz to khz) are delivered to the headphones. L R 7-5 LOW DROPOUT BIPOLAR BRIDGE DRIVER The AD can be used for driving a 35 Ω Wheatstone bridge. Figure 5 shows one-half of the AD being used to buffer the AD59, a.35 V low power reference. The output of.5 V can be used to drive an ADC converter front end. The other half of the AD is configured as a unity gain inverter and generates the other bridge input of.5 V. Resistor R and Resistor R provide a constant current for bridge excitation. The AD6 low power instrumentation amplifier is used to condition the differential output voltage of the bridge. The gain of the AD6 is programmed using an external resistor RG and determined by 9. kω G = kω % R G 9.9kΩ.35V 3 / AD59 kω % V S AD 5.kΩ % 35Ω kω % 6 / AD 5 R Ω 35Ω 35Ω 35Ω R G 7.5V R Ω TO A/D CONVERTER REFERENCE INPUT V S 3 V S 7 AD 5 V S V REF V S.µF GND.µF V S Figure 5. Low Dropout Bipolar Bridge Driver 6 5V µf µf 5V 7-5 Rev. F Page of

OUTLINE DIMENSIONS. (.6).365 (9.7).355 (9.) PIN. (5.33) MAX.5 (3.).3 (3.3).5 (.9). (.56). (.6). (.36). (.5) BSC.7 (.7).6 (.5).5 (.) 5. (7.).5 (6.35). (6.).5 (.3) MIN SEATING PLANE.5 (.3) MIN.6 (.5) MAX.5 (.3) GAUGE PLANE.35 (.6).3 (7.7).3 (7.6).3 (.9) MAX.95 (.95).3 (3.3).5 (.9). (.36). (.5). (.) COMPLIANT TO JEDEC STANDARDS MS--BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 5. -Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-) Dimensions shown in inches and (millimeters). (.57) 3. (.97).5 (.9). (.) COPLANARITY. 5. (.96). (.9) 5 SEATING PLANE.7 (.5) BSC 6. (.) 5. (.).75 (.6).35 (.53).5 (.).3 (.).5 (.9).7 (.67).5 (.96).5 (.99) 5.7 (.5). (.57) COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 53. -Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-) Dimensions shown in millimeters and (inches).95.5.75 3. 3...5. PIN 5.65 BSC.3. 3. 3.. COPLANARITY. 5.5.9.65. MAX SEATING PLANE.3. COMPLIANT TO JEDEC STANDARDS MO-7-AA Figure 5. -Lead Mini Small Outline Package [MSOP] (RM-) Dimensions shown in millimeters..6. Rev. F Page of

ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ADAN C to 5 C -Lead PDIP N- ADANZ C to 5 C -Lead PDIP N- ADAR C to 5 C -Lead SOIC R- ADAR-REEL C to 5 C -Lead SOIC R- ADAR-REEL7 C to 5 C -Lead SOIC R- ADARZ C to 5 C -Lead SOIC R- ADARZ-REEL C to 5 C -Lead SOIC R- ADARZ-REEL7 C to 5 C -Lead SOIC R- ADARM-R C to 5 C -Lead MSOP RM- BA ADARM-REEL C to 5 C -Lead MSOP RM- BA ADARMZ-R C to 5 C -Lead MSOP RM- #BA ADARMZ-REEL C to 5 C -Lead MSOP RM- #BA ADBR C to 5 C -Lead SOIC R- ADBR-REEL C to 5 C -Lead SOIC R- ADBR-REEL7 C to 5 C -Lead SOIC R- ADBRZ C to 5 C -Lead SOIC R- ADBRZ-REEL C to 5 C -Lead SOIC R- ADBRZ-REEL7 C to 5 C -Lead SOIC R- Z = Pb-free part, # denotes lead-free product may be top or bottom marked. SPICE model is available at www.analog.com. Rev. F Page 3 of

NOTES 5 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D7--/5(F) Rev. F Page of