CURRENT SENSG SGLE CHANNEL DRIVER Features Floating channel designed for bootstrap operation Fully operational to + V Tolerant to negative transient voltage dv/dt immune Application-specific gate drive range: Motor Drive: V to V (IRS7/IRS8) Automotive: 9 V to V (IRS7/IRS8) Undervoltage lockout. V, 5 V, and 5 V input logic compatible lead indicates shutdown has occured Output in phase with input (IRS7/IRS7) Output out of phase with input (IRS8/IRS8) RoHS compliant Description ical Connection Product Summary V OFFSET I O +/- V max. ma / ma V OUT V - V 9 V - V (IRS7/IR8) (IRS7/IR8) V CSth t on/off (typ.) Packages Data Sheet No. PD99 5 mv or.8 V 5 ns & 5 ns The IRS7/IRS8/IRS7/IRS8 are high voltage, high speed power MOSFET and IGBT drivers. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL outputs, down to. V. The protection circuity detects over-current in the driven power transistor and terminates the gate drive voltage. An open drain signal is provided to indicate that 8-Lead PDIP 8-Lead SOIC an over-current shutdown has occurred. The output driver features a high pulse current buffer stage designed for minimum cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side or low-side configuration which operates up to V. COM CS V S IRS7/IRS7 (Refer to Lead Assignments for correct pin configuration). These diagrams show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. COM CS V S IRS8/IRS8 www.irf.com
Absolute imum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min.. Units High-side floating supply voltage -. 5 V S High-side floating offset voltage - 5 +. V High-side floating output voltage V S -. +. Logic supply voltage -. 5 V V Logic input voltage -. +. V FLT output voltage -. +. V CS Current sense voltage V S -. +. dv s /dt Allowable offset supply voltage transient 5 V/ns P D Package power dissipation @ TA +5 C Rth JA Thermal resistance, junction to ambient 8-Lead DIP. 8-Lead SOIC.5 8-Lead DIP 5 8-Lead SOIC T J Junction temperature 5 T S Storage temperature -55 5 T L Lead temperature (soldering, seconds) W C/W C Recommended Operating Conditions The input/output logic timing diagram is shown in Fig.. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at 5 V differential. Symbol Definition Min.. Units High-side floating supply voltage (IRS7/IRS8) V S + V S + (IRS7/IRS8) V S + 9 V S + V S High-side floating offset voltage Note V High-side floating output voltage V S Logic supply voltage V V Logic input voltage V FLT output voltage V CS Current sense signal voltage V S V S + 5 T A Ambient temperature - 5 C Note : Logic operational for V S of -5 V to + V. Logic state held for V S of -5 V to -S. (Please refer to the Design Tip DT97- for more details). www.irf.com
Dynamic Electrical Characteristics IAS (, S ) = 5 V, C L = pf and T A = 5 C unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Fig.. Symbol Definition Min... Units Test Conditions t on Turn-on propagation delay 5 V S = V t off Turn-off propagation delay 5 V S = V t r Turn-on rise time 8 t f Turn-off fall time 5 ns t bl Start-up blanking time 55 75 95 t cs CS shutdown propagation delay 5 t flt CS to pull-up propagation delay 7 5 Static Electrical Characteristics IAS (, S ) = 5 V and T A = 5 C unless otherwise specified. The V, V TH, and I parameters are referenced to COM. The V O and I O parameters are referenced to V S. Symbol Definition Min... Units Test Conditions Logic input voltage (IRS7/IRS7) V IH Logic input voltage (IRS8/IRS8) V IL Logic input voltage (IRS7/IRS7) Logic input voltage (IRS8/IRS8).5 V CSTH+ CS input positive (IRS7/IRS8) 8 5 mv going threshold (IRS7/IRS8).5.8. V OH High level output voltage, IAS - V O.5. V OL Low level output voltage, V O.. I LK Offset supply leakage current 5 VB = VS = V I QBS Quiescent S supply current 8 V = V or 5 V I QCC Quiescent supply current I + Logic input bias current 7. 5 µa V = 5 V I - Logic input bias current 5. V = V I CS+ High CS bias current 5. V CS = V I CS- High CS bias current 5. V CS = V SUV+ S supply undervoltage (IRS7/IRS8) 8.8..8 positive going threshold (IRS7/IRS8). 7. 8. SUV- S supply undervoltage (IRS7/IRS8) 7.5 9.. negative going threshold (IRS7/IRS8)..8 7.7 I O+ Output high short circuit pulsed current 9 I O- Output low short circuit pulsed current.8 = V to V R on,flt - low on resistance 5 Ω V V V ma IO = ma V O = V, V = 5 V PW µs V O = 5 V, V = V PW µs www.irf.com
Functional Block Diagram IRS7/IRS7 UP SHIFTERS PULSE GEN HV LEVEL SHIFT UV DETECT PULSE FILTER PULSE GEN Q R - DOWN S + SHIFTER PULSE Q R FILTER COM S R R S Q DELAY BUFFER V S CS Functional Block Diagram IRS8/IRS8 PULSE GEN HV LEVEL SHIFT UV DETECT PULSE FILTER PULSE GEN - DOWN S + SHIFTER COM 5V Q R S UP SHIFTERS PULSE FILTER R R S Q Q R DELAY BUFFER V S CS www.irf.com
Lead Definitions Symbol COM V S CS Description Logic and gate drive supply Logic input for gate driver output (), in phase with (IRS7/IRS7) out of phase with (IRS8/IRS8) Indicates over-current shutdown has occurred, negative logic Logic ground High-side floating supply High-side gate drive output High-side floating supply return Current sense input to current sense comparator Lead Assignments 8 8 I N 7 I N 7 C S C S COM V S 5 COM V S 5 8 Lead PDIP 8 Lead SOIC IRS7/IRS7 IRS7S/IRS7S 8 8 I N 7 I N 7 C S C S COM V S 5 COM V S 5 8 Lead PDIP 8 Lead SOIC IRS8/IRS8 IRS8S/IRS8S www.irf.com 5
(IRS8/ IRS8) (IRS7/ IRS7) CS (IRS8/ IRS8) (IRS7/ t IRS7) on 5% 5% 5% 5% t r t off 9% 9% t f % % Figure. Switching Time Waveform Definition Figure. Input/Output Timing Diagram (IRS8/ IRS8) (IRS7/ IRS7) CS 5% 5% t bl 9% Figure. Start-Up Blanking Time Waveform Definitions CS V CSTH CS V CSTH t cs t flt 9% 9% Figure. CS Shutdown Waveform Definitions Figure 5. CS to Waveform Definitions www.irf.com
T ur n- On D elay T ime ( ns ) 5 5 5 T ur n- On D elay T ime ( ns ) 5 5 5-5 -5 5 5 75 5 8 Figure A. Turn-On Delay Time vs. Figure B. Turn-On Delay Time vs. Voltage Turn- Off Delay Time (ns) 5 5 5 Turn- Off Delay Time (ns) 5 5 5-5 -5 5 5 75 5 Figure 7A. Turn-Off Delay Time vs. 8 Figure 7B. Turn-Off Delay Time vs. Voltage www.irf.com 7
Turn- Off Fall Time (n s) T u r n - O n R i s e Time (ns) 8 8-5 -5 5 5 75 5 Figure 8A. Turn-On Rise Time vs. 9 8 7 5-5 -5 5 5 75 5 Turn- Off Fall Time (n s) T u r n - O n R i s e Time (ns) 8 8 8 Figure 8B. Turn-On Rise Time vs. Voltage 8 7 5 8 Figure 9A. Turn-Off Fall Time vs. Figure 9B. Turn-Off Fall Time vs. Voltage www.irf.com 8
S t a r t - U p B l a n k i n g T i m e ( n s ) 8 Min -5-5 5 5 75 5 Figure A. Start-Up Blanking Time vs. S t a r t - U p B l a n k i n g T i m e ( n s ) 8 Min 8 Figure B. Start-Up Blanking Time vs. Voltage CS S hutdown Prop. D elay (ns) 5 5 5 5 5 5-5 -5 5 5 75 5 Figure A. CS Shutdown Prop. Delay vs. CS S hutdown Prop. D elay (ns) 5 5 5 5 8 Figure B. CS Shutdown Prop. Delay vs. Voltage www.irf.com 9
CS to Pull-Up Prop. Delay (ns ) 8 7 5-5 -5 5 5 75 5 Figure A. CS to Pull-Up Prop. Delay vs. CS to Pull-Up Prop. Delay (ns ) 5 8 Figure B. CS to Pull-Up Prop. Delay vs. Voltage L o g i c " " ( " " f o r 8 ) V I H Threshold (V).5 Min.5.5-5 -5 5 5 75 5 L o g i c " " ( " " f o r 8 ) V I H Threshold (V).5 Min.5.5 8 Figure A. Logic "" ("" for 8) V IH Threshold vs. Figure B. Logic "" ("" for 8) V IH Threshold vs. Voltage www.irf.com
Logic "" ("" for 8) V IL Threshold (V).9.8.7..5.... -5-5 5 5 75 5 Logic "" ("" for 8) V IL Thre shold (V).9.8.7..5.... 8 Figure A. Logic "" ("" for 8) V IL Figure B. Logic "" ("" for 8) V IL Threshold vs. Threshold vs. Voltage CS Input Positive Going Voltage (V).5..5. Min.5..5-5 -5 5 5 75 5 Figure 5A. CS Input Positive Going Voltage vs. CS Input Positive Going Voltage (V).5..5. Min.5..5 8 Figure 5B. CS Input Positive Going Voltage vs. Voltage www.irf.com
H i g h L e v e l O u t p u t ( I O = m A ) ( V)..5..5..5-5 -5 5 5 75 5 High Level Output (I O = m A) (V).5..5..5 8 Figure A. High Level Output (I O = ma) vs. Figure B. High Level Output (I O = ma) vs. Voltage Low L evel Output (I O = m A ) ( V ).....8... -5-5 5 5 75 5 Figure 7A. Low Level Output (I = ma) O vs. Low Level Output (I O = m A) (V)...8... 8 Figure 7B. Low Level Output (I O = ma) vs. Voltage www.irf.com
O ff s e t Supply Leak a ge Cur r ent ( µa) 9 8 7 5-5 -5 5 5 75 5 Figure 8A. Offset Supply Leakage Current vs. S Supply Current (µa) 5 5 Figure 8B. High-Side Floating Well Offset Supply Leakage vs. Voltage 7 S Supply Current (µa) 5 S Supply Current (µa) 5-5 -5 5 5 75 5 Figure 9A. S Supply Current vs. 8 Figure 9B. S Supply Current vs. Voltage www.irf.com
8 Supp ly Current (µa ) 8 Supply Current (µa ) 8-5 -5 5 5 75 5 8 Figure A. Supply Current vs. Figure B. Supply Current vs. Voltage Logic "" Input Bias Current (µa) 8 8-5 -5 5 5 75 5 Figure A. Logic "" Input Bias Current vs. L o g i c " " I n p u t B i a s C u r r e n t ( µ A ) 8 8 Figure B. Logic "" Input Bias Current vs. Voltage www.irf.com
Logic "" Input Bias Current (µa) 5-5 -5 5 5 75 5 Figure A. Logic "" Input Bias Current vs. Logic "" Input Bias Current (µa) 5 8 Figure B. Logic "" Input Bias Current vs. Voltage Logic "" CS Bias Current (µa) 5 L o g i c " " C S B i a s C u r r e n t ( µ A ) 5-5 -5 5 5 75 5 8 Figure A. Logic "" CS Bias Current vs. Figure B. Logic "" CS Bias Current vs. Voltage www.irf.com 5
Logic "" CS Bias Current (µa) 5-5 -5 5 5 75 5 L o g i c " " C S B i a s C u r r e n t ( µ A ) 5 8 Figure A. Logic "" CS Bias Current vs. Figure B. Logic "" CS Bias Current vs. Voltage S UV Threshold (+) (V) 8 Min S UV T hreshold (+) (V) 8 Min -5-5 5 5 75 5 Figure 5A. S UV Threshold (+) vs. 8 Figure 5B. S UV Threshold (+) vs. Voltage www.irf.com
S UV Threshold (-) (V) 8 Min S UV T hreshold (-) (V) 8 Min -5-5 5 5 75 5 Figure A. S UV Threshold (-) vs. 8 Figure B. S UV Threshold (-) vs. Voltage Ou tput Source Cu rrent (A)..5..5..5..5 Min -5-5 5 5 75 5 Figure 7A. Output Source Current vs. Output Source Current (A).5.5..5..5..5. Min.5 8 Figure 7B. Output Source Current vs. Voltage www.irf.com 7
Ou tput Sink Curre nt (A).8.7..5.... Min -5-5 5 5 75 5 Figure 8A. Output Sink Current vs. Output Sink Current (A).9.8.7..5... Min. 8 Figure 8B. Output Sink Current vs. Voltage www.irf.com 8
Case outlines 8-Lead PDIP - - (MS-AB) A E X D 5 8 7 5 e B H.5 [.] A. [.55] X.7 [.5] FOOTPRT 8X.7 [.8] 8X.78 [.7] DIM CHES MILLIMETERS M MAX M MAX A A.5..88.98.5..75.5 b....5 c.75.98.9.5 D E.89.97.98.57.8.8 5.. e.5 BASIC.7 BASIC e.5 BASIC.5 BASIC H K L y.8.99...9.5 8 5.8.5...5.7 8 e A C y K x 5 8X b.5 [.] C A B NOTES: A. DIMENSIONG & TOLERANCG PER ASME Y.5M-99.. CONTROLLG DIMENSION: MILLIMETER. [.]. DIMENSIONS ARE SWN MILLIMETERS [CHES].. OUTLE CONFORMS TO JEDEC OUTLE MS-AA. 8-Lead SOIC 8X L 7 8X c. OUTLE CONFORMS TO JEDEC OUTLE MS-AA. 5 DIMENSION DOES NOT CLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED.5 [.]. DIMENSION DOES NOT CLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED.5 [.]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERG TO A SUBSTRATE. -7 - (MS-AA) www.irf.com 9
Tape & Reel 8-lead SOIC LOADED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLG DIMENSION MM E G CARRIER TAPE DIM ENSION FOR 8SOICN Metric Im perial Code Min Min A 7.9 8...8 B.9..5. C.7...8 D 5.5 5.55..8 E..5.8.55 F 5. 5...8 G.5 n/a.59 n/a H.5..59. F D E C B A G H REEL DIM ENSIONS FOR 8SOIC N Metric Im perial Code Min Min A 9..5.97. B.95.5.8.8 C.8..5.59 D.95.5.77.9 E 98...858.5 F n/a 8. n/a.7 G.5 7..57.7 H...88.5 www.irf.com
LEADFREE PART MARKG FORMATION Part number Date code IRxxxxxx S YWW? IR logo Pin Identifier? MARKG CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - digit SPN code) Assembly site code Per SCOP - ORDER FORMATION 8-Lead PDIP IRS7PbF 8-Lead PDIP IRS7PbF 8-Lead SOIC IRS7SPbF 8-Lead SOIC IRS7SPbF 8-Lead SOIC Tape & Reel IRS7STRPbF 8-Lead SOIC Tape & Reel IRS7STRPbF 8-Lead PDIP IRS8PbF 8-Lead PDIP IRS8PbF 8-Lead SOIC IRS8SPbF 8-Lead SOIC IRS8SPbF 8-Lead SOIC Tape & Reel IRS8STRPbF 8-Lead SOIC Tape & Reel IRS8STRPbF The SOIC-8 is MSL qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: Kansas St., El Segundo, California 95 Tel: () 5-75 Data and specifications subject to change without notice. /7/7 www.irf.com