256K-BIT STATIC RAM Wide Temperature Range Extremely Low Standby Current Access Time 100ns (2.7V) 55ns (4.5V) 32,768 Words 8-Bit Asynchronous DESCRIPTION The SRM2B256SLMX is a low voltage operating 32,768 words 8-bit asynchronous, static, random access memory fabricated using an advanced CMOS technology. Its very low standby power consumption makes it ideal for applications requiring non-volatile storage with back-up batteries, and 25 to 85 C operating temperature range makes it ideal for industrial use. The asynchronous and static nature of the memory requires no external clock or refresh circuit. 3-state output ports allow easy expansion of memory capacity. These features make the SRM2B256SLMX usable for a wide range of applications, from microprocessor systems to terminal devices. FEATURES Wide temperature range........... 25 to 85 C Extended supply voltage range...... 2.7 to 5.5V Fast access................. 100ns (3V ± 10%) 55ns (5V ± 10%) Extremely low standby current...... SL Version Completely static................. No clock required 3-state output Battery back-up operation Package....................... SRM2B256SLCX............... DIP2-28pin (plastic) SRM2B256SLMX.............. SOP2-28pin (plastic) SRM2B256SLTMX...........TSOP (I)-28pin (plastic) SRM2B256SLRMX........ TSOP (I)-28pin-R1 (plastic) 000-97-MEM- 57
BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 Address Buffer 9 6 X Decoder Y Decoder 512 64 Memory Cell Array 512 x 64 x 8 64 x 8 Column Gate Control Logic 8 OE WE OE, WE Control Logic I/O Buffer I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 58 000-97-MEM-
PIN CONFIGURATION (DIP/SOP2) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD WE A13 A8 A9 A11 OE A10 I/O8 I/O7 I/O6 I/O5 I/O4 SRM2B256SLMX/CX (TSOP) (TSOP-R1)(Reverse bending) OE A11 A9 A8 A13 WE V DD A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 SRM2B256SLTMX 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 I/O8 I/O7 I/O6 I/O5 I/O4 V SS I/O3 I/O2 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A12 A14 V DD WE A13 A8 A9 A11 OE 7 6 5 4 3 2 1 28 27 26 25 24 23 22 SRM2B256SLRMX 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A2 A1 A0 I/O1 I/O2 I/O3 V SS I/O4 I/O5 I/O6 I/O7 I/O8 A10 PIN DESCRIPTION A0 to A14 WE OE I/O1 to I/O8 VDD VSS Address input Write Enable Output Enable Chip Select Data I/O Power Supply (2.7V to 5.5V) Power Supply (0V) 000-97-MEM- 59
ABSOLUTE MAXIMUM RATINGS VSS = 0V Parameter Symbol Rating Unit Supply voltage VDD 0.5 to 7.0 V Input voltage VI 0.5* to 7.0 V Input/output voltage VI/O 0.5* to VDD + 0.3 V Power dissipation PD W Operating temperature TOPR 25 to 85 C Storage temperature TSTG 65 to 150 C Soldering temperature and TSOL 260 C, 10s (Lead only) * VI, VI/O (Min.) = 3.0V when pulse width is less or equal to 50ns DC RECOMMENDED OPERATING CONDITIONS VSS = 0V, Ta = 25 to 85 C Parameter Supply voltage Input voltage VDD = 3V ± 10% VDD = 5V ± 10% Symbol Unit Min. Typ. Max. Min. Typ. Max. VDD 2.7 3.3 4.5 5.5 V VSS 0 0 0 0 V VIH 2.2 VDD + 0.3 2.2 VDD + 0.3 V VIL 0.3* 0.4 0.3* V * VIL (Min.) = 3V when pulse width is less or equal to 50ns 60 000-97-MEM-
ELECTRICAL CHARACTERISTI DC Electrical Characteristics (VSS = 0V, Ta = 25 to 85 C) Parameter Symbol Conditions VDD = 3V VDD = 5V Min Typ*1 Max Min Typ*2 Max Input leakage ILI VI = 0 to VDD 1 1 1 1 µa Standby supply current IDDS = VIH 2 3.0 ma IDDS1 VDD 0.2V 0.3 25 0.5 50 µa Unit Average operating current IDDA IDDA1 VI = VIL, VIH II/O = 0mA, tcyc = Min VI = VIL, VIH II/O = 0mA, tcyc = 1µs 10 15 30 45 ma 5 10 ma Operating supply current IDDO VI = VIL, VIH ILO = 0mA 5 10 ma Output leakage High level output voltage Low level output voltage ILO = VIH or WE = VIL or OE = VIH, VI/O = 0 to VDD 1 1 1 1 µa VOH IOH = ma, 0.5mA*3 2.4 2.4 V VOL IOL = 2.1mA, ma*3 0.4 0.4 V *1 Typical values are measured at Ta = 25 C and VDD = 3.0V *2 Typical values are measured at Ta = 25 C and VDD = 5.0V *3 VDD = 3.0V Terminal Capacitance (f = 1MHz, Ta = 25 C) Parameter Symbol Conditions Min Typ Max Unit Address capacitance CADD VADD = 0V 8 pf Input capacitance CI VI = 0V 8 pf I/O capacitance CI/O VI/O = 0V 10 pf 000-97-MEM- 61
AC Electrical Characteristics Read Cycle VSS = 0V, Ta = 25 to 85 C SRM2B256SLMX55 SRM2B256SLMX70 SRM2B256SLMX10 Parameter Symbol Condi -tions VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V Unit Read cycle trc Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 100 55 120 70 180 100 ns Address access access OE access tacc 100 55 120 70 180 100 ns *1 ta 100 55 120 70 180 100 ns toe 60 30 70 35 90 45 ns output set tclz 15 10 15 10 15 10 ns output floating OE output set OE output floating Output hold tchz 35 20 40 25 50 35 ns *2 tolz 5 0 5 0 5 0 ns tohz 35 20 40 25 50 35 ns toh *1 15 10 15 10 15 10 ns 62 000-97-MEM-
Write Cycle VSS = 0V, Ta = 25 to 85 C SRM2B256SLMX55 SRM2B256SLMX70 SRM2B256SLMX10 Parameter Symbol Condi -tions VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V Unit Write cycle twc Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 100 55 120 70 180 100 ns Chip Select Address valid to end of write Address setup Write pulse width Address hold Input data set Input data hold Write to output floating Output active from end to write tcw 80 50 90 60 110 80 ns taw 80 50 90 60 110 80 ns tas 0 0 0 0 0 0 ns *1 twp 75 40 80 45 100 60 ns twr 0 0 0 0 0 0 ns tdw 40 25 45 30 60 40 ns tdh 0 0 0 0 0 0 ns twhz 35 20 40 25 50 35 ns *2 tow 5 5 5 5 5 5 ns *1. Test Conditions 1. Input pulse level: 0.6V to 2.4V (5V) /0.4V to 2.2V (3V) 2. tr = tr = 5ns 3. Input and output timing reference levels : 1.5V 4. Output load CL = 100pF I/O C L 1TTL C L = 100pF (Includes Jig Capacitance) *2. Test Conditions 1. Input pulse level: 0.6V to 2.4V (5V) /0.4V to 2.2V (3V) 2. tr = tr = 5ns 3. Input timing reference levels : 1.5V 4. Output timing reference levels: ± 200mV (the level displaced from stable output voltage level) 5. Output load CL = 5pF 1TTL I/O C L C L = 5pF (Includes Jig Capacitance) 000-97-MEM- 63
Timing Charts Read Cycle*1 t RC ADDRESS t ACC t A t OH t CLZ t CHZ OE Dout t OE t OLZ t CHZ Note: *1. During read cycle, WE must be H level. Write Cycle (1) ( Control)*2 t WC ADDRESS t AW t CW WE t AS t WP t WR Dout t CLZ t WHZ t DW t DH Din Note: *2. During write cycle that is controlled by, Output Buffer is in high impedance state, whether OE level is H or L. 64 000-97-MEM-
Write Cycle (2) (WE Control)*3 ADDRESS WE Dout Din t AS t WC t AW t WP t WHZ t DW t WR t DH t OW Note: *3. During write cycle that is controlled by WE, Output Buffer is in high impedance state if OE is H level. 000-97-MEM- 65
DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY (VSS = 0V, Ta = 25 to 85 C) Parameter Symbol Conditions Min Typ* Max Unit Data retention supply voltage VDDR 2.0 5.5 V Data retention current IDDR VDD = 3V VDD 0.2V 0.25 20 (2**) µa Chip select data hold tcdr 0 ns Operation recovery tr 5 ns * Typical values are measured at 25 C ** Typical values are measured at 40 C Data Retention Timing V DD Data hold mode 2.7V 2.7V V DDR 2.0V t CDR V IH V DD 0.2V t R V IH *Note: During standby mode in which the data is retentive, the supply voltage (VDD) can be in low voltage until VDD = VDDR. At this mode, data reading and writing are impossible. 66 000-97-MEM-
FUNCTIONS Truth Table OE WE A0 to A14 Data I/O Mode IDD H X X Hi-Z Standby IDDS, IDDS1 L X L Stable DIN Write IDDA, IDDA1 L L H Stable DOUT Read IDDA, IDDA1 L H H Stable Hi-Z Output disable IDDA, IDDA1 X: H or L : H, L, or Hi-Z Read Mode The data appear when the address is set while holding = L, OE = L and WE = H. When OE = H, DATA I/O terminals are in high impedance state, that makes circuit design and bus control easy. Write Mode There are the following 3 ways of writing data into memory: (1) Hold = L and WE = L, set address (2) Hold = L then set address and give L pulse to WE. (3) After setting addresses, give L pulse to both and WE. In case the above data on the DATA I/O terminals is latched up into the chip when or WE is in positive-going. Since DATA I/O terminals are high impedance when or OE = H, bus contention between data driver and memory outputs can be avoided. Standby Mode When is H, the chip is in the standby mode. In this mode, DATA I/O terminals are high impedance and all inputs of addresses, WE and data can be any H or L. When is over VDD 0.2V, the chip is in the data retention battery backup mode. In this case, there is a small current in the chip which flows through the high resistances of the memory cells. 000-97-MEM- 67
PACKAGE DIMENSIONS Plastic DIP-28 pin Unit: mm (inch) 28 37.4Max 36.7 ± 0.1 15 13.4 ± 0.1 1 14 1.5 0.6 ± 0.1 4.6 ± 0.1 15.24 0.25 ± 0.03 0.01 2.54 3.0Min 0.46 ± 0.1 15.24~16.64 Plastic TSOP (I)-28 pin Unit: mm (inch) 13.4 ± 0.1 11.8± 0.2 22 28 1 Index 21 8.0 ± 0.2 7 8 0.15 ± 0.05 1.2Max 0 ~ 10 0.5 ± 0.1 0.05 0.55 0.2 ± 0.1 68 000-97-MEM-
Plastic TSOP (I)-28 pin-r1 Unit: mm (inch) 13.4 ± 0.3 11.8± 0.2 7 28 1 Index 8 8.0 ± 0.2 22 21 0.15 ± 0.05 1.2Max 0 ~ 10 0.5 ± 0.1 0.05 0.55 0.2 ± 0.1 Plastic SOP2-28 pin Unit: mm (inch) 28 18.1 Max 17.8 ± 0.1 15 8.4 ± 0.1 11.8 ± 0.3 1 14 2.5 ± 0.15 0.15 ± 0.05 9.4 2.7 1.27 0.4 ± 0.1 0.2 000-97-MEM- 69
CHARACTERISTIC CURVES 1.3 1.2 1.1 0.9 Normalized I DDA Ta 5V 3V 0.9 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Normalized I DDA Frequency 5V 3V 1.3 1.2 1.1 0.9 Normalized I DDA V DD 5V 3V 0.7-50 -25 0 25 50 75 100 Ta ( C) 0.0 0 5 10 15 20 Ta ( C) 0.7 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 V DD (V) Ta = 25 C 100.0 10.0 0.1 Normalized I DDS1 Ta 5V 3V 0.0-50 -25 0 25 50 75 100 Ta ( C) Normalized I DDS1 V DD Normalized I OH V OH 1.6 2.5 1.4 1.2 0.6 0.4 2.0 1.5 0.5 5V 3V 0.2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 2.0 3.0 4.0 5.0 6.0 V DD (V) Ta = 25 C V OH (V) Ta = 25 C 3.0 2.5 2.0 1.5 0.5 Normalized I OL V OL 5V 3V 0.0 0.0 0.2 0.4 0.6 V DD (V) Ta = 25 C Normalized t ACC, t A V DD Normalized t ACC t A 2.4 1.3 2.2 5V 1.2 3V 2.0 1.8 1.1 1.6 1.4 1.2 0.9 0.6 0.7 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0-50 -25 0 25 50 75 100 V DD (V) Ta ( C) Ta = 25 C 70 000-97-MEM-