ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 010 Lecture 7: PLL Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University
Announcements Project Preliminary Report #1 due now Exam is still April 30 Reading Posted clocking papers Website additional links has PLL and jitter tutorials Majority of today s material from Fischette tutorial and M. Mansuri s PhD thesis (UCLA)
Agenda PLL noise transfer functions PLL circuits 3
Forward Clock I/O Circuits TX PLL TX Clock Distribution Replica TX Clock Driver Channel Forward Clock Amplifier RX Clock Distribution De-Skew Circuit DLL/PI Injection-Locked Oscillator 4
Embedded Clock I/O Circuits TX PLL TX Clock Distribution CDR Per-channel PLL-based Dual-loop w/ Global PLL & Local DLL/PI Local Phase-Rotator PLLs Global PLL requires RX clock distribution to individual channels 5
Input Noise Transfer Function [Mansuri] K o s Input Phase Noise: H n IN ( s) φ = φ out n IN = s K ( RCs + 1) N( ζω s + ω ) Loop = K Loop K Loop s + + N RCs + N n n n n ζω s + ω Voltage Noise on Input Clock Source: T n IN ( s) φ = v out n IN φ = φn out IN K s o = s s K + o K K Loop Loop N ( RCs + 1) K RCs + N Loop 6
VCO Noise Transfer Function [Mansuri] K VCO is different if the input is at the V cntrl input (K VCO ) or supply (K Vdd ) VCO Phase Noise: H n VCO φ φ out ( s) = = = n VCO s K + N Loop s RCs + K Loop N s + s ζωns + ωn Voltage Noise on VCO Inputs: T n VCO ( s) = φ v n out VCO φ = φn out VCO K s VCO = s + K N K Loop VCO s RCs + K Loop N 7
Clock Buffer Noise Transfer Function [Mansuri] K delay units = (s/v) Output Phase Noise: T n buf ( s) φ = v out n buf out buf H Voltage Noise on Buffer Inputs: φ = φn n buf Kdelayω s + 1 ωbuf VCO φ φ out ( s) = = = n buf Kdelayω = s + 1 ωbuf s VCO s K + N Loop K + N Loop s RCs + K s K RCs + N Loop N Loop s s + K K + N s ζω + ω ns n delay Loop ω VCO s K RCs + N Loop 8
Noise Transfer Functions Input phase noise (N=1) (low-pass) VCO input voltage noise (band-pass) Buffer phase or voltage noise (high-pass) [Mansuri] 9
Charge-Pump PLL Circuits Phase Detector Charge-Pump Loop Filter VCO Divider 10
Phase Detector Detects phase difference between feedback clock and reference clock The loop filter will filter the phase detector output, thus to characterize phase detector gain, extract average output voltage (or current for charge-pump PLLs) Can be analog or digital 11
Analog Multiplier Phase Detector A cosω t 1 1 1 1 cos[ ( ω1 + ω ) t + φ] + [( ω1 ω ) t φ] cos cos ( ω + φ) A t αa A α is mixer gain αa A If ω 1 =ω and filtering out high-frequency term y αa 1 A ( t) = cos φ Near φ lock region of π/: y( t) α A A 1 π φ K αa A 1 PD = [Razavi] 1
XOR Phase Detector Sensitive to clock duty cycle [Razavi] 13
XOR Phase Detector [Perrott] 14
Cycle Slipping If there is a frequency difference between the input reference and PLL feedback signals the phase detector can jump between regions of different gain PLL is no longer acting as a linear system [Perrott] 15
Cycle Slipping Cycle Slipping [Perrott] If frequency difference is too large the PLL may not lock 16
Phase Frequency Detector (PFD) Phase Frequency Detector allows for wide frequency locking range, potentially entire VCO tuning range 3-stage operation with UP and DOWN outputs Edge-triggered results in duty cycle insensitivity 17
PFD Transfer Characteristic UP=1 & DN=-1 [Perrott] Constant slope and polarity asymmetry about zero phase allows for wide frequency range operation 18
PFD Deadzone If phase error is small, then short output pulses are produced by PFD Cannot effectively propagate these pulses to switch charge pump Results in phase detector dead zone which causes low loop gain and increased jitter Solution is to add delay in PFD reset path to force a minimum UP and DOWN pulse length [Fischette] 19
PFD Operation Min. Pulse Width [Fischette] 0
Charge-Pump PLL Circuits Phase Detector Charge-Pump Loop Filter VCO Divider 1
Charge Pump VDD I UP Charging VCO Control Voltage DOWN I Discharging C 1 R C VSS Converts PFD output signals to charge Charge is proportional to PFD pulse widths PFD-CP Gain: 1 π I CP
Simple Charge Pump [Razavi] Issues Switch resistance can vary Vctrl due to body effect Charge injection from switches onto Vctrl Charge sharing between current source drain nodes and Vctrl 3
Charge Pump Mismatch PLL will lock with static phase error Extra ripple on Vctrl [Razavi] Results in frequency domain spurs at the reference clock frequency offset from the carrier 4
Charge Pump w/ Improved Matching [Young JSSC 199] Amplifier keeps current source Vds voltages constant resulting in reduced transient current mismatch 5
Charge Pump w/ Reversed Switches Swapping switches reduces charge injection MOS caps (Md1-4) provide extra charge injection cancellation Helper transistors Mx and My quickly turn-off current source Dummy brand helps to match PFD loading [Ingino JSSC 001] 6
Charge-Pump PLL Circuits Phase Detector Charge-Pump Loop Filter VCO Divider 7
Loop Filter VDD I Charging VCO Control Voltage I VSS Discharging C 1 R C F(s) Lowpass filter extracts average of phase detector error pulses 8
Loop Filter Transfer Function Neglecting secondary capacitor, C 9
Loop Filter Transfer Function With secondary capacitor, C 30
Why have C? Secondary capacitor smoothes control voltage ripple Can t make too big or loop will go unstable C < C 1 /10 for stability C > C 1 /50 for low jitter Control Voltage Ripple 31
Filter Capacitors To minimize area, we would like to use highest density caps Thin oxide MOS cap gate leakage can be an issue Similar to adding a non-linear parallel resistor to the capacitor Leakage is voltage and temperature dependent Will result in excess phase noise and spurs Metal caps or thick oxide caps are a better choice Trade-off is area Metal cap density can be < 1/10 thin oxide caps Filter cap frequency response can be relatively low, as PLL loop bandwidths are typically 1-50MHz 3
Charge-Pump PLL Circuits Phase Detector Charge-Pump Loop Filter VCO Divider 33
Voltage-Controlled Oscillator ω 0 1 K VCO 0 VDD/ VDD Time-domain phase relationship ( t) ( t) dt = K v ( t) θ out = ω out VCO c dt ω ( t) ω + ω ( t) = K v ( t) out = 0 out ω 0 + VCO Laplace Domain Model c 34
Voltage-Controlled Oscillators (VCO) Ring Oscillator Easy to integrate Wide tuning range (5x) Higher phase noise LC Oscillator Large area Narrow tuning range (0-30%) Lower phase noise 35
Barkhausen s Oscillation Criteria [Sanchez] n Closed-loop transfer function: H 1 H ( jω) ( jω) Sustained oscillation occurs if H ( jω) = 1 conditions: Gain = 1 at oscillation frequency ω 0 Total phase shift around loop is n360 at oscillation frequency ω 0 36
Ring Oscillator Example [Sanchez] 37
Ring Oscillator Example 4-stage oscillator A0 = sqrt() Phase shift = 45 Easier to make a larger-stage oscillator oscillate, as it requires less gain and phase shift per stage [Sanchez] 38
Next Time PLL wrap-up CDRs 39