Lecture 29-30 Perspectives Administrivia Final on Friday May 18 12:30-3:30 pm» Location: 251 Hearst Gym Topics all what was covered in class. Review Session Time and Location TBA Lab and hw scores to be posted on the web please check if correct or if something is missing Poster Session Phase III May 8, 3:30-6:30pm» Sign-up sheet posted HW8 posted; will not be graded. FEEDBACK ON COURSE EXTREMELY WELCOME! 1
Today s Design Methodologies Will Not Scale Much Further The Deep Sub-Micron (DSM) Effect ( 0.25µ) DSM Microscopic Problems Wiring Load Management Noise, Crosstalk Reliability, Manufacturability Complexity: LRC, ERC Accurate Power Prediction Accurate Delay Prediction etc. Everything Looks a Little Different? 1/DSM Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! The Productivity Gap Logic Transistors per Chip (K).10µ.35µ 2.5µ 10,000,000 1,000,000 100,000 10,000 1,000 100 10 1 1981 Logic Transistors/Chip Transistor/Staff Month 58%/Yr. compound Complexity growth rate 1983 1985 x x x 1987 1989 x x x x 1991 21%/Yr. compound Productivity growth rate 1993 100,000,000 10,000,000 1,000,000 100,000 10,000 1,000 1995 1997 1999 2001 2003 2005 2007 2009 100 10 Source: SEMATECH Productivity Trans./Staff - Month 2
Implementation Methodologies Digital Circuit Implementation Approaches Custom Semi-custom Cell-Based Array-Based Standard Cells Compiled Cells Macro Cells Pre-diffused Pre-wired (Gate Arrays) (FPGA) Custom Design Layout Editor Magic Layout Editor (UC Berkeley) 3
Cell-based Design (or standard cells) Feedthrough Cell Logic Cell Rows of Cells Functional Module (RAM, multiplier, ) Routing Channel Routing channel requirements are reduced by presence of more interconnect layers Standard Cell Example [Brodersen92] 4
Standard Cell - Example 3-input NAND cell (from Mississippi State Library) characterized for fanout of 4 and for three different technologies Gate Array Sea-of-gates polysilicon V DD rows of uncommitted cells GND metal possible contact Uncommited Cell In 1 In 2 In 3 In4 routing channel Committed Cell (4-input NOR) Out 5
Sea-of-gate Primitive Cells Oxide-isolation PMOS PMOS NMOS NMOS NMOS Using oxide-isolation Using gate-isolation Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6 µm CMOS) 6
Prewired Arrays Categories of prewired arrays (or fieldprogrammable devices): Fuse-based (program-once) Non-volatile EPROM based RAM based Programmable Logic Devices PLA PROM PAL 7
EPLD Block Diagram Primary inputs Macrocell Courtesy Altera Corp. Field-Programmable Gate Arrays Fuse-based I/O Buffers Program/Test/Diagnostics Vertical routes Standard-cell like floorplan I/O Buffers I/O Buffers Rows of logic modules Routing channels I/O Buffers 8
Interconnect Programmed interconnection Input/output pin Cell Antifuse Horizontal tracks Vertical tracks Programming interconnect using anti-fuses Field-Programmable Gate Arrays RAM-based CLB CLB Horizontal routing channel switching matrix Interconnect point CLB CLB Vertical routing channel 9
RAM-based FPGA Basic Cell (CLB) Combinational logic Storage elements R A B/Q1/Q2 C/Q1/Q2 D Any function of up to 4 variables F D in F G R D Q1 CE F A B/Q1/Q2 C/Q1/Q2 D Any function of up to 4 variables G F G R D Q2 CE G E Clock CE Courtesy of Xilinx RAM-based FPGA Xilinx XC4025 10
Addressing the Design Complexity Issue Architecture Reuse Reuse comes in generations Generation Reuse element Status 1 st Standard cells Well established 2 nd IP blocks Being introduced 3 rd Architecture Emerging 4 th IC Early research Source: Theo Claasen (Philips) DAC 00 Architecture ReUse Silicon System Platform» Flexible architecture for hardware and software» Specific (programmable) components» Network architecture» Software modules» Rules and guidelines for design of HW and SW Has been successful in PC s» Dominance of a few players who specify and control architecture Application-domain specific (difference in constraints)» Speed (compute power)» Dissipation» Costs» Real / non-real time data 11
Platform-Based Design Only the consumer gets freedom of choice; designers need freedom from choice (Orfali,, et al, 1996, p.522) A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer New platforms will be defined at the architecture-micro-architecture boundary They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations Key to such approaches is the representation of communication in the platform model Source:R.Newton Design at a crossroad System-on-a-Chip Multi- 500 k Gates FPGA Spectral RAM + 1 Gbit DRAM Imager Preprocessing 64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS Analog µc system +2 Gbit DRAM Recognition Embedded applications where cost, performance, and energy are the real issues! DSP and control intensive Mixed-mode Combines programmable and application-specific modules Software plays crucial role 12
EE 141 Summary Digital CMOS Design is Kicking and Healthy Some major challenges down the road caused by Deep Sub-micron» Super GHz design» Power consumption!!!!» Reliability making it work Some new circuit solutions are bound to emerge Who can afford design in the years to come? Some major design methodology change in the making! 13