Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits Low voltage op amps Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages 415-432 Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-2 INTRODUCTION Implications of Low-Voltage, Strong-Inversion Operation Reduced power supply means decreased dynamic range Nonlinearity will increase because the transistor is working close to V DS (sat) Large values of because the transistor is working close to V DS (sat) Increased drain-bulk and source-bulk capacitances because they are less reverse biased. Large values of currents and W/L ratios to get high transconductance Small values of currents and large values of W/L will give smallv DS (sat) Severely reduced input common mode range Switches will require charge pumps

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-3 What are the Limits of Power Supply? The limit comes when there is no signal range left when the dc drops are subtracted from. Minimum power supply (no signal swing range): (min.) = V T + 2V ON For differential amplifiers, the minimum power supply is: (min.) = 3V ON However, to have any input common mode range, the effective minimum power supply is, (min.) = V T + 2V ON V + + PB1 V T +V V ON ON + V + NB1 V ON V T +V ON 060802-01 + V ON + V ON + + V T +V ON + V T + V ON V NB1 V ON 060802-02 Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-4 Minimum Power Supply Limit Continued The previous consideration of the differential amplifier did not consider getting the signal out of the amplifier. This will add another V ON. + V ON + V M6 + V PB2 ON + + V ON V T +V ON + V T + V ON + V T V NB1 V ON V T +V ON M8 M9 060802-03 Therefore, (min.) = V T + 3V ON This could be reduced to 3V ON with the floating battery but its implementation probably requires more than 3V ON of power supply. Note the output signal swing is V T + V ON while the input common range is V ON.

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-5 LOW VOLTAGE INPUT STAGES Input Common Mode Voltage Range Minimum power supply (ICMR = 0): (min) = V SD3 (sat)-v T1 +V GS1 +V DS5 (sat) V = V SD3 (sat)+v DS1 (sat)+v DS5 (sat) SD3 (sat) Input common-mode range: V icm (upper) = - V SD3 (sat) + V T1 V icm (lower) = V DS5 (sat) + V GS1 -V T1 v icm V GS1 + VBias - If the threshold magnitudes are 0.7V, = 1.5V and the saturation voltages are 0.3V, then V icm (upper) = 1.5-0.3 + 0.7 = 1.9V and V icm (lower) = 0.3 + 1.0 = 1.3V giving an ICMR of 0.6V. V DS5 (sat) + VBias - Fig. 7.6-3 Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-6 Increasing ICMR using Parallel Input Stages Turn-on voltage for the n-channel input: V onn = V DSN5 (sat) + V GSN1 Turn-on voltage for the p-channel input: V onp = - V SDP5 (sat) - V SGP1 The sum of V onn and V onp equals the minimum power supply. Regions of operation: > V icm > V onp : (n-channel on and p-channel off) g m (eq) = g mn V onp V icm V onn : (n-channel on and p-channel on) g m (eq) = g mn + g mp V onn > V icm > 0 : (n-channel off and p-channel on) g m (eq) = g mp where g m (eq) is the equivalent input transconductance of the above input stage, g mn is the input transconductance for the n-channel input and g mp is the input transconductance for the p-channel input. g m (eff) g mn +g mp I Bias M6 V icm MN3 MN1 MP1 MP3 MP5 MN5 MP2 MN2 MP4 MN4 V icm Fig. 7.6-4 g mp n-channel off V onn n-channel on V onp n-channel on p-channel on p-channel on p-channel off 0 V SDP5 (sat)+v GSN1 -V SDP5 (sat)+v GSN1 g mn V icm Fig. 7.6-5

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-7 Removing the Nonlinearity in Transconductances as a Function of ICMR Increase the bias current in the differential amplifier that is on when the other I b differential amplifier is off. 3:1 Three regions of operation depending on the value of V icm : 1.) V icm < V onn : n-channel diff. amp. off and p-channel on with I p = 4I b : V B2 I nn V icm MB2 MN1 MP1 I p MP2 I n V icm MB1 MN2 I pp V B1 K P W P g m (eff) = L P 2 I b 2.) V onn < V icm < V onp : both on with I n = I p = I b : 1:3 I b Fig. 7.6-6 K N W N K P W P g m (eff) = L N I b + L P I b 3.) V icm > V onp : p-channel diff. amp. off and n-channel on with I n = 4I b : g m (eff) = K N W N L N 2 I b Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-8 How Does the Current Compensation Work? Set V B1 = V onn and V B2 = V onp. Result: v icm MN1 I n v icm MB1 MN2 I pp V onn I b If v icm >V onn then I n = I b and I pp =0 If v icm <V onn then I n = 0 and I pp =I b g m (eff) If v icm <V onp then I p = I b and I nn =0 If v icm >V onp then I p = 0 and I nn =I b V onp I nn v MP1 icm MB2 I b I p MP2 v icm Fig. 7.6-6A g mn =g mp 0 0 V icm V onn V onp VDD Fig. 7.6-7 The above techniques and many similar ones are good for power supply values down to about 1.5V. Below that, different techniques must be used or the technology must be modified (natural devices).

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-9 Natural Transistors Natural or native NMOS transistors normally have a threshold voltage around 0.1V before the threshold is increased by increasing the p concentration in the channel. If these transistors are characterized, then they provide a means of achieving low voltage operation. Minimum power supply (ICMR = 0): (min) = 3V ON Input common mode range: V icm (upper) = V ON + V T (natural) V icm (lower) = 2V ON + V T (natural) If V T (natural) V ON = 0.1V, then V icm (upper) = V icm (lower) = 3V ON = 0.3V Therefore, ICMR = - 3V ON = 0.3V (min) 1V Matching tends to be better (less doping and magnitude is smaller). Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-10 Bulk-Driven MOSFET A depletion device would permit large ICMR even with very small power supply voltages because V GS is zero or negative. When a MOSFET is driven from the bulk with the gate held constant, it acts like a depletion transistor. Cross-section of an n-channel v V V bulk-driven MOSFET: BS V DS GS DD Large signal equation: i D = K N W 2L V GS - V T0-2 F - v BS + 2 F 2 Small-signal transconductance: g mbs = (2K N W/L)I D 2 2 F - V BS ;; Bulk Drain Gate Source Substrate ;; p ;;; + n + Channel ;; n ; + ;; n+ Depletion Region p-well n substrate QP QV Fig. 7.6-8

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-11 Bulk-Driven MOSFET - Continued Transconductance characteristics: 2000 Bulk-source driven Saturation: V DS > V BS V P gives, V BS = V P + V ON i D = I DSS 1 - V BS 2 V P Comments: g m (bulk) > g m (gate) if V BS > 0 (forward biased ) Drain Current (μa) 1500 1000 500 I DSS Gate-source driven 0-3 -2-1 0 1 2 3 Gate-Source or Bulk-Source Voltage (Volts) Fig. 7.6-9 Noise of both configurations are the same (any differences comes from the gate versus bulk noise) Bulk-driven MOSFET tends to be more linear at lower currents than the gate-driven MOSFET Very useful for generation of I DSS floating current sources. Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-12 Bulk-Driven, n-channel Differential Amplifier What is the ICMR? V icm (min) = V SS + V DS5 (sat) + V BS1 = V SS + V DS5 (sat) - V P1 + V DS1 (sat) Note that V icm can be less than V SS if V P1 > V DS5 (sat) + V DS1 (sat) V icm (max) =? As V icm increases, the current through and is constant so the source increases. However, the gate voltage stays constant so that V GS1 decreases. Since the current must remain constant through and because of, the bulk-source v i1 v I i2 voltage becomes less negative causing V Bias TN1 + + + to decrease and maintain the currents V BS1 V GS V - - BS2 - through and constant. If V icm is increased sufficiently, the bulk-source voltage will become positive. However, M6 current does not start to flow until V BS is greater than 0.3 volts so the effective V icm (max) is V icm (max) - V SD3 (sat) - V DS1 (sat) + V BS1. V SS Fig. 7.6-10

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-13 Illustration of the ICMR of the Bulk-Driven, Differential Amplifier 250nA 200nA Bulk-Source Current 150nA 100nA 50nA 0 Comments: Effective ICMR is from V SS to -0.3V -50nA -0.50V -0.25V 0.00V 0.25V 0.50V Input Common-Mode Voltage Fig. 7.6-10A The transconductance of the input stage can vary as much as 100% over the ICMR which makes it very difficult to compensate Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-14 Reduction of V T through Forward Biasing the Bulk-Source The bulk can be used to reduce the threshold sufficiently to permit low voltage applications. The key is to control the amount of forward bias of the bulk-source. Current-Driven Bulk Technique : G S B G S B I E Gate n+;; p+ p+ D I BB Reduced Threshold MOSFET D I BB I CD Parasitic BJT Problem: Want to limit the BJT current to some value called, I max. Therefore, I max I BB = CS + CD + 1 I CS n-well Source Drain p- substrate Layout Fig. 7.6-19 T. Lehmann and M. Cassia, 1V Power Supply CMOS Cascode Amplifier, IEEE J. of Solid-State Circuits, Vol. 36, No. 7, 2001.

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-15 Current-Driven Bulk Technique Bias circuit for keeping the I max defined independent of BJT betas. Note: I D,C = I CD + I D I S,E = I D + I E + I R VBias1 The circuit feedback causes a bulk bias M8 + current I BB and hence a bias voltage V BIAS such that VBias VBias2 I I S,E = I D + I BB (1+ CS + CD ) + I R R - Use V Bias1 and V Bias2 to set I D,C 1.1I D, V SS Fig. 7.6-20 I S,E 1.3I D and I R 0.1I D which sets I BB at 0.1I D assuming we can neglect I CS with respect to I CD. For this circuit to work, the following conditions must be satisfied: V BE < V TN + I R R and V TP + V DS (sat) < V TN + I R R If V TP > V TN, then the level shifter I R R can be eliminated. M6 I S,E I D,C R I BB Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-16 LOW VOLTAGE GAIN STAGES Cascade Stages Simple cascade of inverters: V NB1 M6 V NB1 M8 -g m1 R 1 -g m2 R 2 -g m3 R 3 -g m4 R 4 The problem with this approach is the number of poles that occur (one per stage) if the amplifier is to be used in a closed loop application. 060803-01

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-17 Nested Miller Compensation Principle: Use Miller compensation to split the poles within a feedback loop. Compensating Results: v 1) C m1 pushes p 4 to higher in frequencies and p 3 down to lower frequencies 060812-01 2) C m2 pushes p 2 to higher frequencies and p 1 down to lower frequencies p 1 p 2 p3 -g m1 -gm2 -g p4 m3 -g m4 3) C m3 pushes p 3 to higher frequencies (feedback path) & pulls p 1 further to lower frequencies Equations: GB g m1 /C m3 p 2 g m2 /C m3 p 3 g m3 C m3 /(C m1 C m2 ) p 4 g m4 /C L The objective is to get all poles larger than GB: GB < p 2, p 3, p 4 C m2 C m3 C m1 R 1 R 2 R3 R L C L v out Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-18 Illustration of the Nested Miller Compensation Technique p 4 p 3 p 2 p 1 jω σ C m1 p 4 p 3 p 2 p 1 jω σ C m2 p 4 p 2 p 3 p 1 jω σ C m3 jω p 4 p 3 p 2 p 1 σ -GB 070508-01 This approach is complicated by the feedforward paths which create RHP zeros.

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-19 Elimination of the RHP Zeros The following are least three ways in which the RHP zeros can be eliminated. 1.) Nulling resistor. 2.) Feedback only buffer. 3.) Feedback only gain. z 1 = 060803-02 R z1 C c1 1 C c1 (1/g m1 R z1 ) C c1 V PN1 060803-03 Increases the minimum power supply by V ON. 060803-04 C c1 V PB2 V NB1 Increases the pole and increases the minimum power supply by V ON. Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-20 Use of LHP Zeros to Compensate Cascaded Amplifiers Principle: Feedforward around a noninverting stage creates a LHP zero or inverting feedforward around an inverting stage also creates a LHP zero. Example of Multipath, Nested Miller Compensation : V in +g m1 R1 060803-05 +g m4 +g m2 R 2,4 C C -g m3 R 3 V out C 3 V in V NB1 M6 M8 1 M9 0 V Ref1 2 4 C 3 Unfortunately, the analysis becomes quite complex - for the details refer to the reference below. C V Ref2 V out C 3 R. Hogervorst and J. H. Huijsing, Design of Low-Voltage, Low-Power Operational Amplifier Cells, Kluwer Academic Publishers, 1996, pp. 127-131.

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-21 Cascoding Possibilities that trade off output resistance and headroom: I D I D I D V GG I D R + out v out V T +2V on V GG R + out Sat. v out Sat. V T +2V on V GG R + out Sat. v out Act. V GG R + out Sat. v out Act. No Cascoding Normal Cascoding Reduced Headroom Cascoding Gate-Connected Cascode 051205-01 No Cascode Normal Cascode Reduced Headroom Cascode Gate-Connected Cascode v out 1 ß 1 V on1 1 + ß 2 1 + ß 1 ß 2 (2x-x 2 ) 2x + ß 1 ß 2 (2x-x 2 ) R out 1 2ß 2 2ß 2 (x-0.5x 2 ) 2ß 2 (x-0.5x 2 ) r ds 2 I D ß 1 (1-x) + I D x-0.5x 2 ß 1 (1-x) + I D x-0.5x 2 Note: v DS (active) = x V on1 = x (V GG V T ) x = 0.1 and ß 2 = 9ß 1 v out =1.145V on1 and R out =1.45r ds for reduced headroom cascode Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-22 Solutions to the Low Headroom Problem High Voltage Tolerant Circuits High voltage tolerant transistors in standard CMOS : (nom.) Upper gate switched to highest potential (nom.) Thick oxide transistor 050416-02 Thick oxide cascode Retractable cascode composite transistor (Transistor symbols with additional separation between the gate line and the channel line represent thick oxide transistors.) Anne-Johan Annema, et. Al., 5.5-V I/O in a 2.5-V 0.25μm CMOS Technology, IEEE J. of Solid-State Circuits, Vol. 36, No. 3, March 2001, pp. 528-538.

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-23 LOW VOLTAGE BIAS CIRCUITS A Low-Voltage Current Mirror with Wide Input and Output Swings The current mirror below requires a power supply of V T +3V ON and has a V in (min) = V ON and a V out (min) = 2V ON (less for the regulated cascode output mirror). I 1 -I B I B I B I 2 I 1 I B1 I B2 I B1 I 2 i in i out i in i out M6 or M6 I B2 Fig. 7.6-13A Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-24 Low-Voltage Current Mirrors using the Bulk-Driven MOSFET The biggest problem with current mirrors is the large minimum input voltage required for previously examined current mirrors. If the bulk-driven MOSFET is biased with a current that exceeds I DSS then it is enhancement and can be used as a current mirror. i in i out + + + V GS V BS - - - V GS Simple bulk-driven current mirror i in i out + + + V GS3 V BS3 - V - - GS4 + + + V GS1 V BS1 - - - V GS2 Cascodebulk-driven current mirror. Fig.7.6-11 0 0 0.2 0.4 0.6 0.8 1 Vout (V) Fig. 7.6-12 The cascode current mirror gives a minimum input voltage of less than 0.5V for currents less than 100μA Iout (A) 6 10-5 5 10-5 4 10-5 3 10-5 2 10-5 1 10-5 Cascode Current Mirror All W/L's = 200μm/4μm 2μm CMOS Iin=50μA Iin=40μA Iin=30μA Iin=20μA Iin=10μA

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-25 Bandgap Topologies Compatible with Low Voltage Power Supply I PTAT V Ref IV BE I NL I PTAT IV BE V Ref V PTAT V Ref I PTAT R2 V BE I NL R3 R1 Voltage-mode bandgap topology. Current-mode bandgap topology. Voltage-current mode bandgap topology Fig. 7.6-14 Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-26 Technique for Canceling the Bandgap Curvature 1:K 2 1:K 3 I 2 I NL K 3 I NL Current active off K 2 I VBE sat. on K 1 I PTAT I I VBE K 1 I NL PTAT Temperature Circuit to generate nonlinear correction term, I NL. Illustration of the various currents. Fig. 7.6-16 0 I NL =, K 1 I PTAT - K 2 I VBE, K 2 I VBE > K 1 I PTAT K 2 I VBE < K 1 I PTAT The combination of the above concept with the previous slide yielded a curvaturecorrected bandgap reference of 0.596V with a TC of 20ppm/C from -15C to 90C using a 1.1V power supply. In addition, the line regulation was 408 ppm/v for 1.2 10V and 2000 ppm/v for 1.1 10V. The quiescent current was 14μA. G.A. Rincon-Mora and P.E. Allen, A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Bandgap Reference, J. of Solid-State Circuits, vol. 33, no. 10, October 1998, pp. 1551-1554.

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-27 LOW VOLTAGE OP AMPS A Low Voltage Op Amp using Normal Technology (min) = 3V ON + V T (ICMR = V ON ): 1 + v IN V NB1 V PB2 v C OUT c M6 M8 M9 0 Performance: Gain g m 2 r ds 2 Miller compensated Output swing is -2V ON Max. CM input = Min. CM input = 2V ON + V T 060804-01 Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-28 A Low-Voltage, Wide ICMR Op Amp (min) = 4V ON + 2V T (ICMR = ): -V T -V DS (sat) 3:1 -V T -2V DS (sat) V T +2V DS (sat) + v OUT V T +V DS (sat) 1:3 Performance: 041231-15 Gain g m 2 r ds 2, self compensated, and output swing is -4V ON

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-29 An Alternate Low-Voltage, Wide ICMR Op Amp (min) = 4V ON + 2V T (ICMR = ): 3:1 V PB2 V PB2 + v OUT V NB2 V NB2 V NB1 1:3 060804-02 Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-30 A 1-Volt, Two-Stage Op Amp Uses a bulk-driven differential input amplifier. IBias =1V 6000/6 6000/6 3000/6 6000/6 M8 M9 0 1 v v in + in - 2000/2 C c =30pF R z =1kΩ Q5 Q6 400/2 400/2 400/2 2 v out C L Fig. 7.6-18

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-31 Performance of the 1-Volt, Two-Stage Op Amp Specification ( =0.5V, V SS =-0.5V) Measured Performance (C L = 22pF) DC open-loop gain 49dB (V icm mid range) Power supply current 300μA Unity-gainbandwidth (GB) 1.3MHz (V icm mid range) Phase margin 57 (V icm mid range) Input offset voltage ±3mV Input common mode voltage range -0.475V to 0.450V Output swing -0.475V to 0.491V Positive slew rate +0.7V/μsec Negative slew rate -1.6V/μsec THD, closed loop gain of -1V/V -60dB (0.75Vp-p, 1kHz sinewave) -59dB (0.75Vp-p, 10kHz sinewave) THD, closed loop gain of +1V/V -59dB (0.75Vp-p, 1kHz sinewave) -57dB (0.75Vp-p, 10kHz sinewave) Spectral noise voltage density 367nV/ Hz @ 1kHz 181nV/ Hz @ 10kHz, 81nV/ Hz @ 100kHz 444nV/ Hz @ 1MHz Positive Power Supply Rejection 61dB at 10kHz, 55dB at 100kHz, 22dB at 1MHz Negative Power Supply Rejection 45dB at 10kHz, 27dB at 100kHz, 5dB at 1MHz Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-32 A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique 1 2 VBiasP M6 C x + v in 3 7 M9 0 v out - M8 C L VBiasN 4 5 6 V SS Fig. 7.6-21 Transistors with forward-biased bulks are in a shaded box. For large common mode input changes, C x, is necessary to avoid slewing in the input stage. To get more voltage headroom at the output, the transistors of the cascode mirror have their bulks current driven.

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-33 A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique - Continued Experimental results: 0.5μm CMOS, 40μA total bias current (C x = 10pF) Supply Voltage 1.0V 0.8V 0.7V Common-mode input range 0.0V-0.65V 0.0V-0.4V 0.0V-0.3V High gain output range 0.35V-0.75V 0.25V-0.5V 0.2V-0.4V Output saturation limits 0.1V-0.9V 0.15V-0.65V 0.1V-0.6V DC gain 62dB-69dB 46dB-53dB 33dB-36dB Gain-Bandwidth 2.0MHz 0.8MHz 1.3MHz Slew-Rate (C L =20pF) 0.5V/μs 0.4V/μs 0.1V/μs Phase margin (C L =20pF) 57 54 48 The nominal value of bulk current is 10nA gives a 10% increase in differential pair quiescent current assuming a BJT of 100. Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-34 SUMMARY Integrated circuit power supplies are rapidly decreasing (today 2-3Volts) Classical analog circuit design techniques begin to deteriorate at 1.5-2 Volts Approaches for lower voltage circuits: - Use natural NMOS transistors (V T 0.1V) - Drive the bulk terminal - Forward bias the bulk - Use depeletion devices The dynamic range will be compressed if the noise is not also reduced Fortunately, the threshold reduction continues to allow the techniques of this section to be used in today s technology