Leading at the edge TECHNOLOGY AND MANUFACTURING DAY

Similar documents
Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells

Intel Demonstrates High-k + Metal Gate Transistor Breakthrough on 45 nm Microprocessors

Intel Xeon E3-1230V2 CPU Ivy Bridge Tri-Gate 22 nm Process

SoC Technology in the Era of 3-D Tri-Gate Transistors for Low Power, High Performance, and High Density Applications

EE 331 Devices and Circuits I. Lecture 1 March 31, 2014

Transistor Scaling in the Innovation Era. Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011

Enabling Breakthroughs In Technology

ECEN474/704: (Analog) VLSI Circuit Design Fall 2016

Texas Instruments BRF6350B Bluetooth Link Controller UMC 90 nm RF CMOS

Oki 2BM6143 Microcontroller Unit Extracted from Casio GW2500 Watch 0.25 µm CMOS Process

A Winning Combination

The future of lithography and its impact on design

A START-UP S PROSPECTIVE TO TECHNOLOGY CHOICE AND IC DEVELOPMENT IN DEEP SUBMICRON CMOS

Product Catalog. Semiconductor Intellectual Property & Technology Licensing Program

SP 22.3: A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver

Broadcom BCM43224KMLG Baseband/MAC/Radio All-in-One Die SMIC 65 nm Process

A Brief Introduction to Single Electron Transistors. December 18, 2011

Low Transistor Variability The Key to Energy Efficient ICs

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

More Moore: Does It Mean Mixed-Signal Integration or Dis-Integration?

CMOS Technology for Computer Architects

STMicroelectronics LIS3L02AE 3-Axis Accelerometer. MEMS Process Review

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Practical Information

Nikon NC81369R 24.2 Mp, 3.8 µm Pixel Size, APS-C Format CMOS Image Sensor from the Nikon D3200. Module 1: Overview Analysis

Sony IMX128AQP 24.3 Mp 5.9 µm Pixel Pitch CMOS Image Sensor from Nikon D600. Module 1: Overview Analysis

Static Power and the Importance of Realistic Junction Temperature Analysis

Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering

ISSCC 2003 / SESSION 1 / PLENARY / 1.1

CMOSIS CMV Mp, 5.5 µm Pixel Pitch High-Speed Pipelined Global Shutter CMOS Image Sensor with Correlated Double Sampling

The 20th Microelectronics Workshop Development status of SOI ASIC / FPGA

Reducing Transistor Variability For High Performance Low Power Chips

STANDARD CELL LIBRARIES FOR ALWAYS-ON POWER DOMAIN

FinFET-based Design for Robust Nanoscale SRAM

Nikon NC81369R 24.2 Mp, 3.8 µm Pixel Size, APS-C Format CMOS Image Sensor from the Nikon D3200. Module 4: Pixel Cross-Sectional Analysis

Semiconductor Devices

Volterra VT1115MF PWM Controller Chip

HOW TO CONTINUE COST SCALING. Hans Lebon

Microprocessor Design in the Nanoscale Era

450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D

! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! Standard Cells. ! CMOS Process Enhancements

Simple Power IC for the Switched Current Power Converter: Its Fabrication and Other Applications March 3, 2006 Edward Herbert Canton, CT 06019

Practical Information

Circuit Seed Overview

CIRCUITS. Raj Nair Donald Bennett PRENTICE HALL

Scalable and Synthesizable. Analog IPs

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS

Freescale MCIMX357DVM5B 90 nm Multimedia Application Processor

Sony IMX Mp, 1.2 µm Pixel Pitch Back Illuminated (Exmor R) CMOS Image Sensor from the Sony Cyber-shot HX300 Digital Compact Camera

Gallium Nitride (GaN) Technology & Product Development

Akustica AKU2000 MEMS Microphone. MEMS Process Review

Nikon NC81369R 24.2 Mp, 3.8 µm Pixel Size, APS-C Format CMOS Image Sensor from the Nikon D3200. Module 5: Substrate Dopant Analysis

Micron MT9T Megapixel, ¼ Optical Format, 1.75 µm Pixel Size System-on-Chip (SOC) CMOS Image Sensor

Sony IMX Mp, 4.8 µm Pixel Size APS-C (DX Format) CMOS Image Sensor from Nikon D7000. Module 5: Substrate Dopant Analysis

OmniVision OVM7692 (OV289AA Die Markings) VGA CameraCubeChip. Module 3: Planar Pixel Analysis

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

Vietnam General Manager Intel Corporation

45nm Foundry CMOS with Mask-Lite Reduced Mask Costs

Experiences and Benefits of 16nm and 10nm FinFET Development

DG-FINFET LOGIC DESIGN USING 32NM TECHNOLOGY

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm

Canon LC Mp, 4.3 µm Pixel Size, APS-C Format CMOS Image Sensor from the Canon EOS Rebel T4i (EOS 650D/EOS Kiss X6i)

Intel Technology Journal

Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore

ITRS: RF and Analog/Mixed- Signal Technologies for Wireless Communications. Nick Krajewski CMPE /16/2005

Limitations and Challenges to Meet Moore's Law

Low Power Design of Schmitt Trigger Based SRAM Cell Using NBTI Technique

EUV Supporting Moore s Law

40nm Node CMOS Platform UX8

Changing the Approach to High Mask Costs

An Introduction to High-Frequency Circuits and Systems

UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C FORM 6-K. ALCON INC. (Registrant Name)

Competitive in Mainstream Products

EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING

TriQuint SCM6M7010 WiMAX Dual-Band WiFi Front-End Module TriQuint TQPED 0.5 µm E-D phemt Process

Microchip PIC18F4320-I/ML Enhanced Flash Microcontroller Structural Analysis

Analysis and Simulation of a Low-Leakage 6T FinFET SRAM Cell Using MTCMOS Technique at 45 nm Technology

FUGITIVE EMISSIONS AND TYPE TESTING OF VALVES

Wire Bond Technology The Great Debate: Ball vs. Wedge

IBM POWER7 Server 46J6702 IBM 45 nm Dual Stress Liner SOI CMOS Process with edram

FinFET vs. FD-SOI Key Advantages & Disadvantages

OmniVision OVM7692 (OV289AA Die Markings) VGA CameraCubeChip. Module 1: Overview Analysis

Study of Pattern Area of Logic Circuit. with Tunneling Field-Effect Transistors

LSI Logic LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Controller 0.18 µm CMOS Process

Computer Aided Design of Electronics

Introducing 10-nm FinFET technology in Microwind

University of Minnesota, Minneapolis, MN 2. Intel Corporation, Hillsboro, OR 3. Los Alamos National Laboratory, Los Alamos, NM

Sony PMW-F55 CineAlta 4K PMW Series HD Super 35 mm Digital Motion Camera with Global Shutter CMOS Image Sensor. Module 3: Planar Pixel Analysis

Basic Functional Analysis. Sample Report Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:

Trends and Challenges in VLSI Technology Scaling Towards 100nm

FUNCTION ANALYSIS REPORT

Technology Overview. MM-Wave SiGe IC Design

Through-Silicon-Via Inductor: Is it Real or Just A Fantasy?

Simulation of GaAs phemt Ultra-Wideband Low Noise Amplifier using Cascaded, Balanced and Feedback Amplifier Techniques

It s Time for 300mm Prime

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

INSPECTION AND REVIEW PORTFOLIO FOR 3D FUTURE

Datorstödd Elektronikkonstruktion

Rockchip RK3188 Mobile Application Processor GF 28 nm SLP Gate First HKMG CMOS Process

Transcription:

Leading at the edge

22FFL technology MARK BOHR Intel Senior Fellow, Technology and Manufacturing Group Director, Process Architecture and Integration

Disclosures Intel Technology and Manufacturing Day 2017 occurs during Intel s Quiet Period, before Intel announces its 2017 first quarter financial and operating results. Therefore, presenters will not be addressing first quarter information during this year s program. Statements in this presentation that refer to forecasts, future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as anticipates, expects, intends, goals, plans, believes, seeks, estimates, continues, may, will, would, should, could, and variations of such words and similar expressions are intended to identify such forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Such statements are based on management s expectations as of March 28, 2017, and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in these forward-looking statements. Important factors that could cause actual results to differ materially from the company s expectations are set forth in Intel s earnings release dated January 26, 2017, which is included as an exhibit to Intel s Form 8-K furnished to the SEC on such date. Additional information regarding these and other factors that could affect Intel s results is included in Intel s SEC filings, including the company s most recent reports on Forms 10-K, 10-Q and 8-K reports may be obtained by visiting our Investor Relations website at www.intc.com or the SEC s website at www.sec.gov.

Intel s new 22FFL technology 22FFL is the world s first FinFET technology for low power IOT and mobile products Advanced FinFET transistors based on proven 22 nm and 14 nm features >100x leakage power reduction with new ultra-low leakage transistor option Simplified interconnects and design rules based on 22 nm technology New levels of design automation Fully RF design enabled Cost competitive with other industry 28/22 nm planar technologies Source: Amalgamation of analyst data and Intel analysis, based upon current expectations and available information.

22FFL dimensions 22 nm 22FFL 14 nm Transistor FinFET FinFET FinFET Fin Pitch 60 45 42 nm Gate Pitch 90 108 70 nm Metal Pitch 80 90 52 nm Logic Cell Ht 840 630 399 nm Trans. Density 15.3 18.8 37.5 MTr / mm 2 SRAM Cell.092.088.050 um 2 22FFL is based on proven 22 nm and 14 nm features Source: Intel.

22FFL devices High performance transistors Ultra low leakage transistors Analog transistors High voltage I/O transistors High voltage power transistors Good device matching Low 1/F noise Deep N-well isolation Precision resistor MIM capacitor High resistance substrate High-Q inductors 22FFL offers a wide range of devices for digital and analog/rf design Source: Intel.

FinFET Performance and leakage Advantage 2.0 10 1.8 1 Transistor Gate Delay (normalized) 1.6 1.4 1.2 1.0 0.8 37% Faster 22 nm Tri-Gate 32 nm Planar 18% Faster 0.6 0.5 0.6 0.7 0.8 0.9 1.0 1.1 Operating Voltage (V) Channel Current (normalized) 0.1 0.01 0.001 0.0001 Planar Reduced Tri-Gate 1E-05 0.0 0.2 0.4 0.6 0.8 1.0 Gate Voltage (V) FinFETs provide a significant performance and leakage advantage over any planar transistor Source: Intel. Intel 22 nm Tri-Gate announcement, April 2011

22FFl high performance transistors 100 0.85V 10 Total 22FFL 14 nm++ 1 22GP Lower Higher Performance 22FFL provides high performance transistors with drive currents similar to 14nm++ Source: Intel. 0.1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Drive Current

22FFL Low leakage transistors 100 0.85V 10 1 22GP 22FFL 14 nm++ Total 0.1 0.01 0.001 22FFL Low (LL) >100x Lower Higher Performance 22FFL provides the lowest leakage transistors for any mainstream technology Source: Intel. 0.0001 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Drive Current

22FFL transistor Options 100 0.85V 10 22FFL Total 1 0.1 transistors for high performance circuits 0.01 0.001 22FFL Low (LL) LL transistors for always-on alwaysconnected circuits Lower Higher Performance High performance and low leakage transistors co-exist on the same die Source: Intel. 0.0001 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Drive Current

Intel Custom Foundry s robust Ecosystem Design Service Design Tools & Flows Intel Custom Foundry Soft IP Foundation IP Advanced IP Other names and brands may be claimed as the property of others. 22FFL is fully supported by a robust design ecosystem

22FFL is an exciting new technology that provides a compelling combination of performance, power, density and ease-of-design for low power IOT and mobile products * Intel estimate based on current expectations and available information. 22FFL technology High transistor drive currents similar to Intel 14 nm Low leakage transistors with >100x lower total leakage than 22GP Die area scaling better than industry 28/22 nm technologies Wide range of advanced analog/rf devices Extensive use of single patterning for affordable ease-of-design Mature die yield with use of proven 22/14 nm features Cost competitive with other 28/22 nm planar technologies Industry standard PDK0.5 available now, PDK1.0 in Q2 17* Production readiness in Q4 2017*

Leading at the edge