International Journal of Electronics Engineering Research. ISSN 0975-6450 Volume 9, Number 9 (2017) pp. 1389-1395 Research India Publications http://www.ripublication.com DESIGN AND ANALYSIS OF PHASE FREQUENCY DETECTOR USING D FLIP-FLOP FOR PLL APPLICATION S.N. Shukla 1, K.K.Verma 2, Sanjay Kumar Jaiswal 3 and Suraj Chaurasiya 4 1,2,3,4 Department Physics and Electronics, Dr. Ram Manohar Lohia Avadh University, Faizabad, India. Abstract Novel design of 50T Phase frequency detector (PFD) using D Flip Flop is proposed and qualitatively compared with 52T NAND gate based phase frequency detector. Proposed 50T Phase frequency detector (PFD) design consumes significantly low power ~18% than other class of PDF. W/L of NMOS in the proposed design is kept 540/180 nm whereas for PMOS it is 1620/180 nm. Delay and power analysis of the PFD s under discussion are done at different Vdd. Proposed 50T Phase frequency detector (PFD) using D Flip Flop design may be advantageously used in phase locked loop (PLL). Keywords: PFD, low power, dynamic power, PLL, VLSI. 1. INTRODUCTION The scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of Digital circuits. Low power consumption and smaller area are some of the most important criteria for the fabrication of chip. Phase frequency detector (PFD) is used as basic component for designing phase locked loop. Phase Locked Loops (PLL) has a negative feedback control system circuit. There is an increasing demand for a high frequency operation and low jitter PLL.A common architecture for clock generation uses a phase frequency detector (PFD) for simultaneous phase and frequency acquisition.
1390 S.N. Shukla, K.K.Verma, Sanjay Kumar Jaiswal and Suraj Chaurasiya 2. DESIGN DESCRIPTION Present investigation deals with a qualitative comparison of two different logic designs of CMOS PFD s that are sequentially depicted in fig.1and fig.2. accommodates schematic of proposed design whereas others are used in the discussion as reference schematics. Investigators of fig.1 [ref.1] initially developed respective designs of PFD with 380nm and 180nm CMOS technology. However, to provide a fair comparison environment all the logic designs under discussion are simulated herein with 180nm CMOS technology. 52T NAND based phase frequency detector The schematic of 52T NAND Based PFD [ref.1] is shown in fig.1. This 52T NAND Based PFD design accommodates 52 CMOS transistors which suffer from dead zone, blind zone, limited frequency range. It has slow PLL locking time and frequency. Output waveform and power of 52T NAND Based PFD is shown in fig.2 and 3 respectively. It has two outputs UP and DOWN. If the reference signal and feedback signal frequency are different then UP and DOWN signal are leading and lagging. Fig.1. Schematic of 52T NAND based phase frequency detector circuit Fig. 2. Output waveform of 52 T NAND Based PFD
Design and Analysis Of Phase Frequency Detector Using D Flip-Flop 1391 Fig.3. Output power of 52 T NAND Based PFD 50T phase frequency detector using DFF 50T Phase Frequency Detector using D Flip Flop is shown in fig.4. It is consists of two edge-triggered D flip flops which are identical to each other. 50T PFD using DFF has two inputs A and B with enable signal E. when E input at logic 1 then only the PFD output comes otherwise both outputs QA and QB are low. Output and power waveform of 50T phase frequency detector using D Flip Flop is shown in fig.6 and7 respectively. Fig.4. Schematic diagram of Phase frequency detector
1392 S.N. Shukla, K.K.Verma, Sanjay Kumar Jaiswal and Suraj Chaurasiya D flip flop are used for the design of PFD which is shown in fig.5. It is consist of 3-input NAND gate and 2-input NOR based structure. It has three inputs D, CP and rst and two outputs Q and Q _bar. Fig.5. Schematic of edge triggered D flip flop Fig.6. Output waveforms of phase frequency detector using D flip flop
Design and Analysis Of Phase Frequency Detector Using D Flip-Flop 1393 Fig.7. Output power of 50T Phase Frequency Detector using DFF 3. RESULTS AND DISCUSSION Simulation results related to the delay and power consumption of the circuits under discussion are represented in Table 1 and Table 2 Table 1: Delay analysis and Transistor count for various designs PDF s Delay (ns) at different Vdd 1.8 V 2V 3V 5V 52 T PFD 9.5683 9.5683 9.5683 9.5683 50 T PFD 1.9158 1.9158 1.9158 1.9588 Table 2: Power analysis for various designs PDF s Power (mw) at different Vdd 1.8 V 2V 3V 5V 52 T PFD 0.7525 0.7527 0.7539 0.7547 50 T PFD 0.7125 0.7132 0.7139 0.7149 Table 2 refers that power consumption for reference PFD circuit of fig.1 is 0.7547 mw whereas it is observed 0.7149 mw for proposed PFD of fig.4. This shows that reducing the transistors from the reference design of fig.1 records 18% reduction in
1394 S.N. Shukla, K.K.Verma, Sanjay Kumar Jaiswal and Suraj Chaurasiya power consumption for proposed PFD of fig.4. Thus the purposed PFD design consumes least power than other designs of reference a PFD at similar 180nm CMOS technology platform. This sussegests that the purposed PFD designs may be adequately useful for the PLL. 4. CONCLUSION In this paper, the main goal is to improve the performance of Phase Frequency Detector such as delay for generating output and to reduce the overall power dissipated in the circuit with less number of transistors. All circuits designed with 0.18μm CMOS technology on tanner tool and compared delay, power with 52T and 50T PFD. Due to less number of transistors, low power, and small delay 50T using D Flip Flop Phase Frequency Detector is quite useful for PLL applications. REFERENCES [1] Abishek Mann, Amit Karalkar, Lili He, Morris Jones, The Design of A Low- Power Low-Noise Phase Lock Loop IEEE international Synopsys, qulity electronic design, 2010, pp.,528-531 [2] HWANG-CHERNG CHOW and NAN-LIANG YEH A New Phase-Locked Loop with High Speed PhaseFrequency Detector and Enhanced Lock-in, Proceedings of the 10th WSEAS International Conference on CIRCUITS, Vouliagmeni, Athens, Greece, July 10-12, 2006 (pp96-101). [3] N. Kumar Babu, P. Sasibala, Fast Low Power Frequency Synthesis Applications By Using A Dcvsl Delay Cell, International Journal of Electrical and Electronics Engineering (IJEEE), ISSN (PRINT): 2231 5284, Volume-3, Issue-2, 2013. [4] Kan M. Chu and David L. Pulfrey, A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic, IEEE Journal of Solid-State Circuits, Vol. Sc-22, No. 4, August 1987. [5] D. T. Comer, Introduction to Mixed Signal VLSI. New York: Array Publishing Co., 1994. [6] D. J. Allstot, G. Liang, and H. C. Yang, Current-mode logic techniques for cmos mixed-mode asics, Proceedings of the 1991 IEEE Integrated Circuits Conference, vol. 49, no. 8, pp. 25.2/1 25.2/4, May 1991. [7] P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and design of analog integrated circuits, 4 th ed. New York: John Wiley & Sons, 2000. [8] Wen-Chi Wu,C,h ih-chien Huung, Chih-Hsiung Chang', Nui-Heng Tseng,
Design and Analysis Of Phase Frequency Detector Using D Flip-Flop 1395 Low power CMOS PLL for clock generator, IEEE International synopsis on circuits and systems,2003,vol-1, pp.i- 633-I-636. [9] Won-Hyo Lee; Jun-dong Cho; Sung-Dae Lee, A high speed and low power phase-frequency detector and charge-pump, Design Automation Conference, 1999. Proceedings of the ASPDAC 99. Asia and South Pacific, vol., no., pp.269,272 vol.1, 18-21 Jan 1999. [10] K. Arshak, O. Abubaker, and E. Jafer, Design and Simulation Difference Types CMOS Phase Frequency Detector for High Speed and Low Jitter PLL, proceedings of 5th IEEE International Caracas Conference on Devices, Circuits, and Systems, ominican Republic, Vol. 1, Nov.3-5, pp.188-191, 2004.
1396 S.N. Shukla, K.K.Verma, Sanjay Kumar Jaiswal and Suraj Chaurasiya