May OBSOLETE PRODUCT NO RECOMMENDED REPLACEMENT Call Central Applications -800-44-7747 or email: centapp@harris.com TV Chroma Processor [ /Title (CA3 6) /Subject (TV Chrom a Processor) /Autho r () /Keywords (Harris Semiconductor, TV chroma processor, subcarrier regeneration, ntsc, acc, overload detector, keyed chroma output, color processor, industrial Features Phase Locked Subcarrier Regeneration Utilizes Sample-and-Hold Techniques Automatic Chrominance Control ()/Killer Detector Employs Sample-and-Hold Techniques Supplementary with an Overload Detector to Prevent Oversaturation of this Picture Tube Sinusoidal Subcarrier Output Keyed Chroma Output Emitter Follower Buffered Outputs for Low Output Impedance Linear DC Saturation Control Applications TV/CATV Receiver Circuits NTSC Color Decoder/Processor Computer Graphics Subcarrier Regenerator Timing Reference for Frame Grabbers DSP Clock Timing Reference Source Pinouts IN AFPC + AFPC - RF BYPASS GROUND VCO OUT VCO IN CARRIER OUT 3 4 5 6 7 8 (PDIP) TOP VIEW 6 5 4 3 0 GAIN CONT. OUT ZENER REF OVERLOAD DET. V+ + - HORIZ. KEY IN Description The Harris is a monolithic silicon integrated circuit designed for TV chroma processing and is ideally suited for NTSC color graphic applications that require subcarrier regeneration of the color burst signal. Part Number Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. E -40 to 85 6 Ld PDIP E6.3 M -40 to 85 0 Ld SOIC M0.3 IN AFPC + NC AFPC - RF BYPASS GROUND VCO OUT VCO IN NC NC 3 4 5 6 7 8 0 (SOIC) TOP VIEW 0 8 7 6 5 4 3 GAIN CONT. OUT NC ZENER REF OVERLOAD DET. V+ + - HORIZ. KEY IN CARRIER OUT CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation 8-33 File Number 860.5
Absolute Maximum Ratings DC Supply Voltage (V+ to GND) (Note )................. 3.V DC Current: Into V+ Pin...................................... 38mA Into Zener Reference Pin........................... 0mA DC Voltage (Horizontal Key In) Negative Rating................................... -5V Positive Rating..................................... 3V Operating Conditions Temperature Range......................... -40 o C to 85 o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) PDIP Package............................. SOIC Package............................. 85 Maximum Junction Temperature (Plastic Packages)....... 50 o C Maximum Storage Temperature Range......... -65 o C to 50 o C Maximum Lead Temperature (Soldering 0s)............. 300 o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. This rating does not apply when using the internal zener reference in conjunction with an external pass transistor.. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications T A = 5 o C, Chroma Gain Control at maximum position for all tests except as noted. Electrical specifications referenced to test circuit. PARAMETER TERMINAL, MEASUREMENT AND SYMBOL SWITCH POS. S S V INPUT TP MIN TYP MAX UNITS DC ELECTRICAL SPECIFICATIONS Voltage Regulator V 0 0... V Supply Current I 0 6 5 38 ma SWITCHING ELECTRICAL SPECIFICATIONS (Note 3) Pull-In Range (Note 4) V 8 (Note 6) 0.5V P-P ±50 - - Hz Oscillator Output V 8 0 0.6.0 - V P-P % Chroma Output V 5 0.5V P-P.4.7 - V P-P Overload Detector V 5 0.5V P-P 0.4-0.7 V P-P Minimum Chroma Output (Note 5) V 5 0.5V P-P - - 0 mv P-P 00% Chroma Output V 5 V P-P 70 40 % of % 0% Chroma Output V 5 0.V P-P 40-05 Reading Kill Level V TP Vary 5-60 mv P-P NOTES: 3. Except for pull-in range testing, tune oscillator trimmer capacitor for free running frequency of 3.57545MHz ±0Hz. 4. Set Switch to Position, detune oscillator ±50Hz, set Switch to Position, and check for oscillator pull-in. 5. Set Chroma Gain Control to minimum position (CCW). 8-34
Test Circuit +4V 0kΩ 70Ω V REG N0 0.05µF CW 0kΩ CCW GAIN CONTROL 47kΩ µf 3.kΩ S I 0.0µF 0.0µF µf 6 5 4 3 0 kω OSCILLOSCOPE.45kΩ TP S INPUT SIGNAL 3 4 5 6 7 8 kω 0.µF 50Ω VARIABLE ATTENUATOR 680Ω 0pF NPO XTAL 3.57545MHz 0pF N750 TEST SIGNAL GENERATOR 33pF N750 BURST SYNC. SUB- CARRIER KEY PULSE PULSE GENERATOR COUNTER.5µs 63.5µs Pin numbers refer to the PDIP package. (A) BURST 3.57545MHz V (A) Chroma input signal 4µs 0.46V (B) Key pulse input signal (B) 5µs CENTERED ON BURST.0V PEAK (MIN) 8-35
Block Diagram TV PROCESSOR RF BYPASS AFPC.0µF kω 680Ω 4 3 6 CRYSTAL 0pF 0pF 7 33pF INPUT.45kΩ TO TERM. INPUT CW GAIN CONTROL 0 6 kω 50kΩ µf CCW.kΩ KILLER GND 5 FIRST AFPC DET. -π/4 φ SHIFTER +π/4 φ SHIFTER DET. SIGNAL SLE SLE INTERN. REF. ATTENU- ATOR CONTROL SIGNAL SLE SLE DC CONTR. BALANCED φ SHIFTER OVERLOAD DETECTOR SECOND BALANCE- UNBALANCE TRANSLATOR VCO LIMIT COUPLING NETWORK KILLER DELAY CARRIER 8 +.V ZENER REF. KEYER 3 70Ω N0 (NOTE 6) 0.05 µf 0.0 µf (NOTE 6) 5 4 3.kΩ kω SUPPLY VOLTAGE +4V 0kΩ 0V 5µs WIDTH HORIZONTAL KEY INPUT DELAY 0 µf NOTES: 6. Optional design features. 7. Pinout numbers refer to the PDIP package. 8-36
Schematic Diagram 4 RF BYPASS FIRST LIFIER Q 7 AFPC DETECTOR R 3 4K Q 53 SINGLE SLE A B C D R 300 R R 4 300 R 5 R.3K Q Q Q 5 Q 5 0 C 3 5pF R 4. R 5 R 7 Q 54 Q Q R 0 E INPUT R 60. Q R 6 500 R 3 50 Q 3 Q R 8. R 7 500 Q 50 R 0.6K R 500 D Q 7 Q 5 Q 4 R Q6 Q 8 C 0pF R 6 R R 8 Q 3 F G SECOND LIFIER R 43. DETECTOR R 54 4K SIGNAL SLE R 57 H I J K Q 80 Q 68 Q 7 5 Q 65 Q 66 Q 3 Q 4 R 78 Q 35 Q 6 Q 33 Q 3 Q70 Q 36 Q 34 Q 3 R 5 L M N O P GAIN CONTROL 6 3 OVERLOAD DETECTOR R 7 300 Q 67 R 4 8K Q Q 5 R 4 R 40 330 D 3 R 77 750 R 44 Q 0 Q 7 KILLER.. R 46 Q R 48 Q 8 R 47 R 45 0 R 4 R 5 R 50 Q 30 R 5 ZENER REFERENCE D Z Z 3 Q 47 R 53 R 55 3. Q R S OVERLOAD DETECTOR T NOTE: Pin numbers refer to the PDIP Package. Resistance values are in ohms. GROUND 5 (SUBSTRATE) 4 ZENER REFERENCE 8-37
Schematic Diagram (Continued) AFPC XTAL 3 6 7 CARRIER 8 A B C D E Q 55 BALANCED PHASE SHIFTER Q 64 R Q 57 Q 58 R 4 SLE Q 5 Q 7 Q 8 Q 6 R 6 LIMITER LIFIER R 7 3K Q Q 6 R 8 30 R 30 430 R 30 R 3 4K Q 6 R 36 3K F Q 56 Q 4 Q 5 C pf R 5 R 35 4. Q 60 Q 0 R 33 Q 8 R 34 Q 63 Q 4 R 37. R 38. G H I J K R R 3 8. BALANCE - UNBALANCE TRANSLATOR R 6 Q R 73 63 R 64 R 7 4.K Q Q 43 76 D 6 Q 7 Q R 3 750 R 36. OSCILLATOR SLE R 3 500 D POWER SUPPLY +V CC L M N O P Q 3 Q 40 Q 4 R 56 3. Q 37 Q 44 Q 45 Q 46 R 7 0 R 6.8K Q 75 R 70.4K KEYER Q R 6.4K Q 38 Q 74 R 65 R 68. R 67. Z Q 77 R 73. R 74 Q 48 R S T R 54 R 66 Q 4 D 5 D 4 R 75. VOLTAGE REFERENCES HORIZONTAL KEYING INPUT 8-38
Application Information Circuit Description (Pin numbers refer to the DIP package.) The following paragraphs briefly describe the circuit operation of the (shown in the Block Diagram and Schematic Diagram). A detailed description of the operation of various portions of the is given in AN647, Application of the Chroma-Processing lc Using Sample-and-Hold Techniques. The chroma input is applied to Terminal through the desired band-shaping network. A,450Ω resistor should be placed in series with Terminal to minimize oscillator pickup in the first chroma amplifier. This amplifier supplies signals to the second chroma amplifier and to the and AFPC detectors. The first chroma amplifier is gain-controlled by the amplifier. A horizontal keying pulse is applied to Terminal. This pulse must be present to ensure proper operation of the oscillator circuit. The subcarrier burst is sampled during the keying interval in the AFPC detector. The error voltage, produced at Terminal and proportional to the burst phase, is compared to the quiescent bias voltage at Terminal 3 by the sample-and-hold circuitry. This compared voltage controls the phase- shifting network in the phase-locked loop. The operation of the AFPC loop is independent of any external adjustments or voltages except for an initial capacitor adjustment to set the free-running frequency. The regenerated oscillator signal at Terminal 8 is applied internally to the AFPC and detectors through +45 and -45-degree phase-shifter networks to establish the proper phase relationship for these detectors. The detector, which also samples the burst during the keying interval, produces a correction voltage proportional to the burst amplitude. The correction voltage is compared to the quiescent bias level using sample-and-hold circuitry similar to that used in the AFPC portion of the circuit. The compared voltage is applied internally to the amplifier and killer amplifier. Because the amplifier gains and killer threshold are determined by the ratios of the internal resistors, these functions are independent of external voltages or controls. The attenuated chroma signal is fed to the second chroma amplifier, where the burst is removed by keyer action. The killer amplifier, the chroma gain control, and the overload detector control the action of the second chroma amplifier, whose gain is proportional to the dc voltage at Terminal 6. The overload detector (Terminal 3) receives a sample of the chroma output (Terminal 5) and detects the peak of the signal. The detected voltage is stored in an external capacitor connected to Terminal 6. This stored voltage on Terminal 6 affects the gain of the second chroma in the same manner as the chroma gain control. General Considerations The block diagram shown is typical of the type of circuit used in the practical application of the. Several items are critical for proper operation of the circuit.. A series resistor of approximately,450ω (or high source impedance) must be used at the chroma input, Terminal. This high impedance minimizes pickup of unbalanced currents, particularly of the subcarrier oscillator signal.. When the overload detector is used, a large resistor (nominally 47,000Ω) must be placed in series with Terminal 6 to set the required RC time constant. The same RC network series serves to set the killer time constant. 3. The setting of the free-running oscillator frequency requires the presence of the keying pulse. The free-running frequency will be erroneous if Terminal is DC shorted during the setting operation because of the DC offset voltage introduced to the AFPC detector. 4. Care must be taken in PC board designs to provide reasonable isolation between the oscillator portion of the circuit (Terminals 6, 7, and 8) and the chroma input (Terminal ). Overload Detector The overload detector accomplishes two purposes:. It prevents oversaturation due to low burst-to-chroma ratios.. It prevents overload conditions due to noise. Both of these conditions are discussed in more detail in AN647. The extent to which the overload detector is used depends upon the individual receiver design goals. If greater than 0.5V P-P output is desired, the chroma output at Terminal 5 can be tapped to yield any desired degree of overload detector action. Chroma Gain Control The chroma gain control operates by varying the base bias on current source transistor Q 5. To ensure proper temperature tracking of the chroma gain control, it is essential that the control be operated from a supply source derived from the reference voltage at Terminal. Because the control operates from a current source, chroma gain is much more predictable and far less temperature sensitive than controls that steer current by means of a differential amplifier. The typical chroma gain characteristic for the is shown in Figure. (% OF MAX. VALUE) 80 60 40 0 T A = 5 o C, INPUT = 0.5V P-P 0 0 40 60 80 0 VOLTAGE AT TERMINAL 6 (% OF V ) FIGURE. GAIN CONTROL Subcarrier Regenerator Oscillator The oscillator filter consists of a 3.57545MHz crystal, a 680Ω resistor, and a 0pF capacitor connected in series across Terminals 6 and 7. A 33pF capacitor, shunt connected from Terminal 7 to ground, rolls off higher order harmonics, thereby preventing oscillation at the crystal third-harmonic frequency. A 40 8-3
curve of the typical static phase error as a function of the freerunning oscillator frequency is shown in Figure. It should be noted that the slope of the curve determines the DC gain of the phase-locked loop, i.e., 40Hz per degree. STATIC PHASE ERROR (DEGREES) 6 4 0 - -4 T A = 5 o C LITUDE (% OF 5 o C VALUE) 40 30 0 0 0 INPUT = 0.5V P-P, 3.58MHz CW SIGNAL LITUDE PHASE 80-50 -5 0 5 50 75 TEMPERATURE ( o C) -5 FIGURE 4. LITUDE AND PHASE VARIATIONS OF vs TEMPERATURE 5 0 5 0-5 -0 PHASE (DEGREE OF DEVIATION FROM 5 o C VALUE) -300-00 - 0 00 300 OSCILLATOR FREE-RUNNING FREQUENCY (DEVIATION IN Hz FROM 3.57545MHz) 400 FIGURE. STATIC PHASE ERROR Thermal Considerations The circuit of the is thermally compensated to achieve the optimal operating characteristics over the normal operating temperature range of TV receivers. Figures 3 and 4 show the oscillator and chroma-output amplitudes and phases as a function of temperature (Terminals 8 and 5), respectively. Both the oscillator and chroma-output amplitudes and phases are measured relative to the chroma-input phase. The performance of the oscillator free-running frequency as a function of temperature is shown in Figure 5. All the temperature plots are characteristic of the test circuit with the indicated component types and values given. OSCILLATOR LITUDE (% OF 5 o C VALUE) 0 INPUT = 0.5V P-P, 3.58MHz CW SIGNAL 0 80 70 PHASE LITUDE 60-50 -5 0 5 50 75 TEMPERATURE ( o C) 0-5 -0 OSCILLATOR PHASE (DEGREE OF DEVIATION FROM 5 o C VALUE) OSCILLATOR FREE-RUNNING FREQUENCY (DEVIATION IN Hz FROM 3.57545 MHz) 50 0-50 - INPUT = 0V P-P -50-50 -5 0 5 50 75 TEMPERATURE ( o C) FIGURE 5. VARIATION OF OSCILLATOR FREE RUNNING FREQUENCY vs TEMPERATURE 5 FIGURE 3. LITUDE AND PHASE VARIATIONS OF OSCILLATOR vs TEMPERATURE 8-40
+V µf kω 680Ω XTAL 5pF-5pF 33pF 8pF L µh 68pF L 7µH INPUT TYP. 0.5V P-P 56 pf 500Ω.4kΩ V CC 4 3 AFPC DET/FILT. 0pF 6 7 VCO SUBCARRIER FSC 3.57545MHz SUBCARRIER (CW) 8 COMPOSITE VIDEO/ INPUT FIRST / BURST-GATE SWITCH ND 5.V ZENER REF DET/FILT. O.L. DET KILLER AND GAIN CONT. BURST KEYER 4 5 0 3 6 µf kω >V PEAK 0V NOTE: For Subcarrier Regenerator, the second chroma amp is not used; Pins 3,4, and 5 are not connected and pin 6 is grounded. BURST KEY PULSE 4µs (TYP), CENTERED ON BURST FIGURE 6. TYPICAL APPLICATION OF THE AS A SUBCARRIER REGENERATOR 8-4