Intel Xeon E3-1230V2 Package Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com
Package Analysis Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc. 2012 all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. PKG-1204-801 23241JMJM Revision 1.0 Published: May, 2012
Package Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Package Summary 1.7 Brief Comparison to 32 nm Core i5 660 Series Package 2 Device Identification 2.1 Package and Die 3 Package and Die Cross-Sectional Analysis 3.1 Analysis Overview 3.2 Package Structure 3.3 Package Lid (IHS) 3.4 Package Substrate Metal Layers and Vias 3.5 Flip-Chip Studs and Solder Bumps 4 Materials Analysis 4.1 SEM-EDS Analysis of Package Materials 5 References 6 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Identification 2.1.1 Package Top View 2.1.2 Package Bottom View 2.1.3 Package Side View 2.1.4 Package with IHS Removed 2.1.5 Package X-Ray Overview 2.1.6 Package X-Ray Area Near Die 2.1.7 Die Markings 2.1.8 Die Photograph 3 Package and Die Cross-Sectional Analysis 3.2.1 Package Cross-Sectional Overview 3.2.2 PS Edge 3.2.3 Package Edge SEM 3.2.4 Die Edge Cross Section 3.2.5 Die Edge Cross Section SEM 3.2.6 Discrete Components on Bottom of PS SEM 3.2.7 Discrete Components on Bottom of PS Optical 3.3.1 Center of IHS with Die and PS 3.3.2 Package IHS Left-Hand Edge SEM 3.3.3 Die With IHS 3.3.4 TIM Cross Section 3.3.5 TIM Cross Section SEM 3.4.1 Organic PS General Structure Optical 3.4.2 Plan View of Solder Bump Array and Metal 8 FLI 3.4.3 Plan View of Typical Metal 8 FLI Layout 3.4.4 Plan View of Minimum Dimension Metal 8 FLI Layout 3.4.5 Detail of Minimum Dimension Metal 8 FLI Layout 3.4.6 Through Hole Via Overview Optical 3.4.7 Through Hole Via Details Optical 3.4.8 Through Hole Via Detail SEM Cross Section 3.4.9 Top of Through Hole Via, Metals 5 to 8, and Blind Via 5s 3.4.10 Metals 5 to 8 SEM 3.4.11 Metals 5 to 8 with Spacing of Metals 5 and 6 3.4.12 Metals 6 to 8 3.4.13 Metals 6 and 8, Stacked Vias SEM 3.4.14 Metals 1 to 4 Optical 3.4.15 Metals 1 to 4 SEM 3.4.16 Staggered Via 1 to Via 3 and Through Hole Via 3.5.1 Overview of Flip-Chip Studs Tilt-View SEM 3.5.2 Minimum Pitch Flip-Chip Studs Layout A 3.5.3 Minimum Pitch Flip-Chip Studs Layout B 3.5.4 Flip-Chip Studs Tilt-View SEM
Overview 1-2 3.5.5 Flip-Chip Stud and Solder Bump 3.5.6 Stud and Solder Bump SEM 3.5.7 Stud UBM SEM 3.5.8 Details of Solder, Upper UBM, and Lower UBM SEM 3.5.9 Overview of Flip-Chip Pillars and Studs Tilt-View SEM 3.5.10 Detail of Pillars, Layout A Tilt-View SEM 4 Materials Analysis 4.1.1 IHS Lid Body 4.1.2 IHS Lid Top Plating 4.1.3 IHS Lid Bottom Plating 4.1.4 Lid Attach 4.1.5 TIM 4.1.6 Die Attach and Die Corner Underfill 4.1.7 Die RDL 4.1.8 Die Coat 4.1.9 Flip-Chip Stud 4.1.10 Flip-Chip Stud UBM 4.1.11 Solder Bump Body 4.1.12 Solder Bump UBM 4.1.13 Solder Bump Land 4.1.14 Metal 8 FLI Body 4.1.15 Die Underfill 4.1.16 Flip-Chip Solder Mask 4.1.17 Upper Buildup Layer 4.1.18 PS Core 4.1.19 Through Hole Via Fill 4.1.20 Lower Buildup Layer Top Portion 4.1.21 Lower Buildup Layer Bottom Portion 4.1.22 Discrete Component Solder 4.1.23 LGA Solder Mask 4.1.24 LGA Plating 1.2 List of Tables 1 Overview 1.4.1 Companion Reports Intel E3-1230V2 22 nm Tri-Gate CPU 1.5.1 Device Summary 1.6.1 Package Summary 1.6.2 Observed PS Metal Layer Critical Dimensions 1.6.3 Package Vertical Dimensions and Materials (Top to Bottom) 1.7.1 Comparison to 32 nm Intel Core i5 660 Package
22 nm Tri-gate Microprocessor About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at 1-613-829-0414. Chipworks 3685 Richmond Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T 1-613-829-0414 F 1-613-829-0515 Web site: www.chipworks.com Email: info@chipworks.com Please send any feedback to feedback@chipworks.com