IM, IM ovember 99 General urpose Timers Features Exact Equivalent in Most ases for SE/E/ or TL/ Low Supply urrent - IM................................ 0µA - IM............................... 0µA Extremely Low Input urrents............... 0pA High Speed Operation...................... MHz Guaranteed Supply Voltage ange....... V to V Temperature Stability............ 0.00%/ o at o ormal eset Function - o rowbarring of Supply During Output Transition an be Used with Higher Impedance Timing Elements than egular / for Longer Time onstants Timing from Microseconds through Hours Operates in Both Astable and Monostable Modes Adjustable Duty ycle High Output Source/Sink Driver can Drive TTL/MOS Outputs have Very Low Offsets, HI and LO Applications recision Timing ulse Generation Sequential Timing Time Delay Generation ulse Width Modulation ulse osition Modulation Missing ulse Detector Description The IM and IM are MOS timers providing significantly improved performance over the standard SE/E/ and timers, while at the same time being direct replacements for those devices in most applications. Improved parameters include low supply current, wide operating supply voltage range, low THESHOLD, and currents, no crowbarring of the supply current during output transitions, higher frequency performance and no requirement to decouple OTOL for stable operation. Specifically, the IM and IM are stable controllers capable of producing accurate time delays or frequencies. The IM is a dual IM, with the two timers operating independently of each other, sharing only V+ and GD. In the one shot mode, the pulse width of each circuit is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled by two external resistors and one capacitor. Unlike the regular bipolar / devices, the OTOL terminal need not be decoupled with a capacitor. The circuits are triggered and reset on falling (negative) waveforms, and the output inverter can source or sink currents large enough to drive TTL loads, or provide minimal offsets to drive MOS loads. Ordering Information AT UMBE (BAD) IMBA (BA) IMIBA (IBA) TEM. AGE ( o ) AKAGE KG. O. 0 to 0 Ld SOI M. - to Ld SOI M. IMIA - to Ld DI E. IMITV - to in Metal an T. IMMTV (ote) - to in Metal an T. IMID - to Ld DI E. IMMJD (ote) - to Ld EDI F. OTE: Add /B to part number if B processing is desired. inouts IM (DI, SOI) TO VIEW IM (METAL A) TO VIEW IM (DI, EDI) TO VIEW GD THESHOLD OTOL GD AD ASE THESHOLD OTOL THESH- OLD OTOL THESHOLD OTOL 0 9 GD AUTIO: These devices are sensitive to electrostatic discharge; follow proper I Handling rocedures. --ITESIL or -- opyright Intersil orporation 999-0 File umber.
IM, IM Absolute Maximum atings Supply Voltage..................................... +V Input Voltage Trigger, ontrol Voltage, Threshold, eset (ote )......................V+ +0.V to GD -0.V Output urrent.................................... 00mA Operating onditions Temperature ange IM................................. 0 o to 0 o IMI, IMI....................... - o to o IMM, IMM.................... - o to o Thermal Information Thermal esistance (Typical, ote ) θ JA ( o /W) θ J ( o /W) EDI ackage................ 0 Metal an ackage............... 0 Lead DI ackage............ /A Lead DI ackage............. 0 /A SOI ackage................... 0 /A Maximum Junction Temperature (Hermetic ackage)........ o Maximum Junction Temperature (lastic ackage)........ 0 o Maximum Storage Temperature ange......... - o to 0 o Maximum Lead Temperature (Soldering 0s)............ 00 o (SOI - Lead Tips Only) AUTIO: Stresses above those listed in Absolute Maximum atings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. OTES:. Due to the S structure inherent in the MOS process used to fabricate these devices, connecting any terminal to a voltage greater than V+ +0.V or less than V- -0.V may cause destructive latchup. For this reason it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple supply systems, the supply of the IM/ must be turned on first.. θ JA is measured with the component mounted on an evaluation board in free air. Electrical Specifications Applies to IM and IM, Unless Otherwise Specified T A = o (OTE ) - o TO o AAMETE SYMBOL TEST ODITIOS MI TY MAX MI TY MAX UITS Static Supply urrent I DD IM = V - 0 00 - - 00 µa = V - 0 00 - - 00 µa IM = V - 0 00 - - 00 µa = V - 0 00 - - 00 µa Monostable Timing Accuracy A = 0K, = 0.µF, = V - - - - - % - - - - µs Drift with Temperature (ote ) = V - - - - 0 - ppm/ o = 0V - - - - 00 - ppm/ o = V - - - - 0 - ppm/ o Drift with Supply (ote ) = V to V - 0. - - 0. - %/V Astable Timing Accuracy A = B = 0K, = 0.µF, = V - - - - - % - - - - µs Drift with Temperature (ote ) = V - - - - 0 - ppm/ o = 0V - - - - 00 - ppm/ o = V - - - - 0 - ppm/ o Drift with Supply (ote ) = V to V - 0. - - 0. - %/V Threshold Voltage V TH = V - % Trigger Voltage V TIG = V - % Trigger urrent I TIG = V - - 0 - - 0 na Threshold urrent I TH = V - - 0 - - 0 na ontrol Voltage V V = V - % eset Voltage V ST = V to V 0. -.0 0. -. V eset urrent I ST = V - - 0 - - 0 na -
IM, IM Electrical Specifications Applies to IM and IM, Unless Otherwise Specified T A = o (OTE ) - o TO o AAMETE SYMBOL TEST ODITIOS MI TY MAX MI TY MAX UITS Discharge Leakage I DIS = V - - 0 - - 0 na Output Voltage V OL = V, I SIK = 0mA - 0..0 - -. V = V, I SIK =.ma - 0. 0. - - 0. V V OH = V, I SOUE = 0.mA.. -. - - V = V, I SOUE = 0.mA.0. -. - - V Discharge Output Voltage V DIS = V, I SIK = ma - 0. 0. - - 0. V = V, I SIK = ma - - - - - 0. V Supply Voltage (ote ) Functional Operation.0 -.0.0 -.0 V Output ise Time (ote ) t L = 0M, L = 0pF, = V - - - - - ns Output Fall Time (ote ) t F L = 0M, L = 0pF, = V - - - - - ns Oscillator Frequency (ote ) f MAX = V, A = 0Ω, B = 0Ω, = 00pF - - - - - MHz OTES:. These parameters are based upon characterization data and are not tested.. Applies only to military temperature range product (M suffix). Functional Diagram THESHOLD OTOL OMAATO A + - FLI-FLO DIVES + - n OMAATO B GD OTE: This functional diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs. = 00kΩ, ±0% (Typ) TUTH TABLE THESHOLD SWITH Don t are Don t are Low Low On > / (V+) > / (V+) High Low On < / (V+) > / (V+) High Stable Stable Don t are < / (V+) High High Off OTE: will dominate all other inputs: will dominate over THESHOLD. -
IM, IM Schematic Diagram THESHOLD OTOL GD = 00kΩ ±0% (TY) Application Information General The IM/ devices are, in most instances, direct replacements for the E/SE / devices. However, it is possible to effect economies in the external component count using the IM/. Because the bipolar / devices produce large crowbar currents in the output driver, it is necessary to decouple the power supply lines with a good capacitor close to the device. The / devices produce no such transients. See Figure. The IM/ produces supply current spikes of only ma - ma instead of 00mA - 00mA and supply decoupling is normally not necessary. Also, in most instances, the OTOL decoupling capacitors are not required since the input impedance of the MOS comparators on chip are very high. Thus, for many applications capacitors can be saved using an IM, and capacitors with an IM. SULY UET (ma) 00 00 00 00 00 0 0 T A = o 00 SE/E IM/ 00 00 00 TIME (ns) FIGUE. SULY UET TASIET OMAED WITH A STADAD BIOLA DUIG A TASITIO -
IM, IM ower Supply onsiderations Although the supply current consumed by the IM/ devices is very low, the total system supply current can be high unless the timing components are high impedance. Therefore, use high values for and low values for in Figures and. Output Drive apability The output driver consists of a MOS inverter capable of driving most logic families including MOS and TTL. As such, if driving MOS, the output swing at all supply voltages will equal the supply voltage. At a supply voltage of.v or more the IM/ will drive at least standard TTL loads. Astable Operation The circuit can be connected to trigger itself and free run as a multivibrator, see Figure A. The output swings from rail to rail, and is a true 0% duty cycle square wave. (Trip points and output swings are symmetrical). Less than a % frequency variation is observed, over a voltage range of +V to +V. Monostable Operation In this mode of operation, the timer functions as a one-shot, see Figure. Initially the external capacitor () is held discharged by a transistor inside the timer. Upon application of a negative pulse to pin, the internal flip-flop is set which releases the short circuit across the external capacitor and drives the high. The voltage across the capacitor now increases exponentially with a time constant t = A. When the voltage across the capacitor equals / V+, the comparator resets the flip-flop, which in turn discharges the capacitor rapidly and also drives the to its low state. must return to a high state before the can return to a low state. t = -ln ( / ) A =. A IM A THESHOLD OTOL f = -----------------. The timer can also be connected as shown in Figure B. In this circuit, the frequency is: V OTIOAL AAITO FIGUE. MOOSTABLE OEATIO f =. ( A + B ) The duty cycle is controlled by the values of A and B, by the equation: GD D = ( A + B ) ( A + B ) THESHOLD FIGUE A. ASTABLE OEATIO A OTOL 0K ALTE- ATE OTIOAL AAITO ontrol Voltage The OTOL terminal permits the two trip voltages for the THESHOLD and internal comparators to be controlled. This provides the possibility of oscillation frequency modulation in the astable mode or even inhibition of oscillation, depending on the applied voltage. In the monostable mode, delay times can be changed by varying the applied voltage to the OTOL pin. The terminal is designed to have essentially the same trip voltage as the standard bipolar /, i.e., 0.V to 0.V. At all supply voltages it represents an extremely high input impedance. The mode of operation of the function is, however, much improved over the standard bipolar / in that it controls only the internal flip-flop, which in turn controls simultaneously the state of the and pins. This avoids the multiple threshold problems sometimes encountered with slow falling edges in the bipolar devices. B OTIOAL AAITO FIGUE B. ALTEATE ASTABLE OFIGUATIO -