DSHEE ISL37 Precision Single Digitally ontrolled Potentiometer (XDP ) Low Noise, Low Power, I Bus, 8 aps FN69 Rev. pril 5, he digitally controlled potentiometer is implemented with a combination of resistor elements and MOS switches. he position of the wiper is controlled by the user through the I bus interface. he potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. he contents of the WR control the position of the wiper. t power up, the device recalls the contents of the DP s IVR to the WR. he highly precise ISL37 features a low end-to-end temperature coefficient of _Ref ±ppm/ and precise resistance selection. It maintains less than ±% typical variance from the ideal resistance at each wiper position providing 99% accuracy of selected resistance value. his highly accurate DP eliminates the need for complex algorithms to guarantee precision. he ISL37 allows the user to dial in an accurate resistance and the EEPROM memory stores the set value for life, or until changed by the user. n external.5% or better reference resistor must be attached to the ISL37. he ISL37 will mirror both the precise resistance and temperature coefficient of the external resistor. he DP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Pinout SL SD 3 ISL37 ( LD DFN) OP VIEW 9 8 V RH RW Features Precision Digitally ontrolled Potentiometer - 99% ypical ccuracy Of Resistance Over Operational onditions - Zero-ompensated Wiper Resistance Integrated Digitally ontrolled Potentiometer - 8-ap Positions - I Serial Interface - Pin Selectable Slave ddress - k 5k and k otal Resistance - Monotonic Over-emperature - Non-Volatile EEPROM Storage of Wiper Position - to V erminal Voltage Single.7V to 5.5V Supply High Reliability - 5 Years Retention @ +55-5 Years Retention @ +5 -,, ycles Endurance 3mmx3mm hin DFN Package.75mm Max hickness,.65mm Pitch Pb-Free (RoHS ompliant) pplications Setting Precise urrent Values for D Margining and Backlight ontrol Replaces omplex ompensation ircuitry hat Stores Values in Look-up ables Needed for Precise Resistor Setting Setting Precise Resistance Values for est and Measurement ircuits djust Specific Resistances in nalog ircuits Precise alibration and Fine une-up REF_ 4 7 RL REF_B 5 6 GND FN69 Rev. Page of 5 pril 5,
Ordering Information PR NUMBER (Notes,, 3) Block Diagram PR MRING RESISNE OPION (k ) EMP. RNGE ( ) PGE (Pb-free) PG. DWG. # ISL37FRZ 37-4 to +5 Ld DFN L.3x3B ISL37UFRZ 37U 5-4 to +5 Ld DFN L.3x3B ISL37WFRZ 37W -4 to +5 Ld DFN L.3x3B NOES:. dd - suffix for tape and reel. Please refer to B347 for details on reel specifications.. hese Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J SD-. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL37. For more information on MSL please see techbrief B363. V SL RH R REF SD REF_ POWER-UP, INERFE, EEPROM ND ONROL LOGI RW RL k.5% External Resistor for W option, or 5k.5% for U and options respectively REF_B GND Pinout ISL37 ( LD DFN) OP VIEW Pin Descriptions DFN PIN # SYMBOL DESRIPION SL Open drain I interface clock input SL SD REF_ REF_B 3 4 5 9 8 7 6 V RH RW RL GND SD Open drain Serial data I/O for the I interface 3 Device address input for the I interface 4 REF_ erminal for an external reference resistor 5 REF_B erminal B for an external reference resistor 6 GND Device ground pin 7 RL Low terminal of DP 8 RW Wiper terminal of DP 9 RH High terminal of DP V Power supply pin EPD* Exposed Die Pad internally connected to GND *PB thermal land for QFN/DFN EPD should be connected to GND plane or left floating. For more information refer to http://www.intersil.com/data/tb/b389.pdf FN69 Rev. Page of 5 pril 5,
bsolute Maximum Ratings Voltage at any Digital Interface Pin with respect to GND...................... -.3V to V +.3V V...................................... -.3V to +6.V Voltage at any DP Pin with respect to GND..........V to V I W (s).......................................... ±6m Latchup (Note 6).................. lass II, Level B at +5 ESD Human Body Model.................................5kV Machine Model....................................5V hermal Information hermal Resistance (ypical, Notes 4, 5) J ( /W) J ( /W) Lead DFN................. 44 3 Storage emperature........................-65 to +5 Maximum Junction emperature (Plastic Package)........ +5 Pb-Free Reflow Profile.........................see link below http://www.intersil.com/pbfree/pb-freereflow.asp Recommended Operating onditions emperature Range (Extended Industrial)........-4 to +5 V.........................................7V to 5.5V V RH -V RL................................ V to V -.3V V RW -V RL................................3V to V -.3V Power Rating......................................5mW Wiper urrent....................................±3.m UION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOES: 4. J is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See ech Brief B379. 5. For J, the case temp location is the center of the exposed metal pad on the package underside. 6. Jedec lass II pulse conditions and failure criterion used. Level B exceptions is using a minimum negative pulse of -.8V on the pin. nalog Specifications Over recommended operating conditions unless otherwise stated. SYMBOL PRMEER ES ONDIIONS MIN (Note ) YP (Note 7) MX (Note ) UNI R OL RH to RL Resistance W option k U option 5 k option k RH to RL Resistance olerance U and options -3 ± +3 % W option -4 ± +4 % End-to-End emperature oefficient ll options, match external reference r ref ± ppm/ V RH DP High erminal Voltage V RH to GND V RL + V -.3 V V RL DP Low erminal Voltage V RL to GND V - V V R W Wiper Resistance Precision On, RH - floating, V RL = V, force I W current to wiper, I W = (V - V RL )/R OL Precision Off, RH - floating, V RL = V, force I W current to wiper, I W = (V - V RL )/R OL 7 R REF External Reference Resistor for W option,.5% k for U option,.5% 5 k for option,.5% 5 k I LkgDP Leakage on DP Pins Voltage at pin from GND to V..5 µ VOLGE DIVIDER MODE (V @ RL; V -.3V @ RH; measured at RW, unloaded) INL (Note ) Integral Non-linearity W, U or option V RL +.3V < V RW < V -.3V -.5 ±..5 LSB (Note 8) DNL (Note ) Differential Non-linearity W, U or option V RL +.3V < V RW < V -.3V -.5 ±..5 LSB (Note 8) FN69 Rev. Page 3 of 5 pril 5,
nalog Specifications Over recommended operating conditions unless otherwise stated. (ontinued) SYMBOL PRMEER ES ONDIIONS MIN (Note ) YP (Note 7) MX (Note ) UNI ZSerror (Note 9) Zero-scale Error W, U or option V RL < V RW < V RL +.3V.5 LSB (Note 8) FSerror (Note ) Full-scale Error W, U or option - -.5 LSB V -.3V < V RW < V (Note 8) V (Notes 3, 9) Ratiometric emperature oefficient Match to external Rref, DP register set between 5 hex and 7F hex ref ± ppm/ f cutoff -3dB ut Off Frequency Wiper at midpoint (4hex) W option (k) khz Wiper at midpoint (4hex) U option (5k) khz RESISOR MODE (Measurements between RW and RL with RH not connected) Wiper at midpoint (4hex) option (k) khz RINL (Note 7) Integral Non-linearity W, U or option urrent forced to the wiper I W = (V - V RL )/R OL (Note ) -3 ± 3 MI (Note 4) RDNL (Note 6) Differential Non-linearity W, U or option urrent forced to the wiper I W = (V - V RL )/R OL (Note ) -3 ± 3 MI (Note 4) Roffset (Note 5) Offset W, U or option, wiper is out of recommended operation conditions MI (Note 4) R (Notes 8, 9) Resistance emperature oefficient Match to external Rref, DP register set between 5 hex and 7F hex, all options ref ± ppm/ Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PRMEER ES ONDIIONS I V Supply urrent (volatile write/read) V = +5.5V, f SL = 4kHz; SD = Open; (for I, active, read and write states) V = +.7V, f SL = 4kHz; SD = Open; (for I, active, read and write states), k MIN (Note ) YP (Note 7) MX (Note ) UNI.6. m.35.9 m I V Supply urrent (non-volatile write/read) V = +5.5V, f SL = 4kHz; SD = Open; (for I, active, read and write states).75.5 m V = +.7V, f SL = 4kHz; SD = Open; (for I, active, read and write states)..8 m I SB V urrent (Standby) V = +5.5V @ +5, I interface in standby state V = +.7V @ +5, I interface in standby state, k I SD V urrent (Shutdown) V = +5.5V @ +5, I interface in standby state.5. m.3.75 m.5.5 µ I LkgDig t DP t ShdnRec Leakage urrent, at Pins REF_, REF_B,, SD, and SL DP Wiper Response ime DP Recall ime from Shutdown Mode Voltage at pin from GND to V -.5.5 µ SL falling edge of last bit of DP data byte to wiper new position SL falling edge of last bit of R data byte to wiper stored position and RH connection 5 µs 5 µs Vpor Power-on Recall Voltage Minimum V at which memory recall occurs.6 V V Ramp V Ramp Rate. 5 V/ms FN69 Rev. Page 4 of 5 pril 5,
Operating Specifications Over the recommended operating conditions unless otherwise specified. (ontinued) SYMBOL PRMEER ES ONDIIONS MIN (Note ) YP (Note 7) MX (Note ) UNI t D Power-up Delay V above Vpor, to DP Initial Value Register recall completed, and I Interface in standby state ms EEPROM SPEIFIION EEPROM Endurance,, ycles EEPROM Retention emperature +55 5 Years emperature +5 5 Years t W (Note ) Non-volatile Write ycle ime ms SERIL INERFE SPES V IL V IH Hysteresis V OL pin,, SD, and SL Input Buffer LOW Voltage,, SD, and SL Input Buffer HIGH Voltage.7*V.3*V SD and SL Input Buffer Hysteresis.5*V V SD Output Buffer LOW Voltage, Sinking 4m,, SD, and SL Pin apacitance.4 V V V pf f SL SL Frequency 4 khz t sp Pulse Width Suppression ime at SD and SL Inputs ny pulse narrower than the max spec is suppressed 5 ns t SL Falling Edge to SD Output Data Valid SL falling edge crossing 3% of V, until SD exits the 3% to 7% of V window 9 ns t BUF ime the Bus must be Free Before the Start of a New ransmission SD crossing 7% of V during a SOP condition, to SD crossing 7% of V during the following SR condition 3 ns t LOW lock LOW ime Measured at the 3% of V crossing 3 ns t HIGH lock HIGH ime Measured at the 7% of V crossing 6 ns t SU:S SR ondition Setup ime SL rising edge to SD falling edge; both crossing 7% of V 6 ns t HD:S SR ondition Hold ime From SD falling edge crossing 3% of V to SL falling edge crossing 7% of V 6 ns t SU:D Input Data Setup ime From SD exiting the 3% to 7% of V window, to SL rising edge crossing 3% of V t HD:D Input Data Hold ime From SL falling edge crossing 7% of V to SD entering the 3% to 7% of V window ns ns t SU:SO SOP ondition Setup ime From SL rising edge crossing 7% of V, to SD rising edge crossing 3% of V 6 ns t HD:SO SOP ondition Hold ime for Read, or Volatile Only Write From SD rising edge to SL falling edge; 3 ns both crossing 7% of V t DH Output Data Hold ime From SL falling edge crossing 3% of V, until SD enters the 3% to 7% of V window ns FN69 Rev. Page 5 of 5 pril 5,
Operating Specifications Over the recommended operating conditions unless otherwise specified. (ontinued) SYMBOL PRMEER ES ONDIIONS t R t F b Rpu SD and SL Rise ime From 3% to 7% of V +.*b SD and SL Fall ime From 7% to 3% of V +.*b 5 ns 5 ns apacitive Loading of SD or SL otal on-chip and off-chip 4 pf SD and SL Bus Pull-up Resistor Off-chip Maximum is determined by t R and t F For b = 4pF, max is about k ~.5k For b = 4pF, max is about 5k ~ k MIN (Note ) YP (Note 7) MX (Note ) k t SU: Setup ime Before SR condition 6 ns t HD: Hold ime fter SOP condition 6 ns NOES: 7. ypical values are for = +5 and 3.3V supply voltage. 8. LSB: [V(R W ) 7 V(R W ) ]/7. V(R W ) 7 and V(R W ) are V(R W ) for the DP register set to 7F hex and hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 9. ZS ERROR = V(RW) /LSB.. FS error = [V(RW) 7 V ]/LSB.. DNL = [V(RW) i V(RW) i- ]/LSB-, for i = to 7, where i is the DP register setting.. INL = [V(RW) i i LSB V(RW) ]/LSB for i = to 7 Max V RW 3. i Min V RW i for i = 5 to 7 decimal, = -4 to +5. Max( ) is the maximum value of the wiper V --------------------------------------------------------------------------------------------- = ---------------- 6 Max V RW i + Min V RW i + 65 voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 4. MI = RW 7 RW /7. MI is a minimum increment. RW 7 and RW are the measured resistances for the DP register set to 7F hex and hex respectively. 5. R OFFSE = RW /MI, when measuring between RW and RL. 6. R DNL = (RW i RW i- )/MI -, for i = to 7. 7. R INL = [RW i (MI i) RW ]/MI, for i = to 7. 8. Max Ri Min Ri 6 for i = 5 to 7, = -4 to +5. Max( ) is the maximum value of the resistance and Min ( ) is R = --------------------------------------------------------------- ---------------- Max Ri + Min Ri the minimum value of the resistance over the temperature range. + 65 9. Limits should be considered typical and are not production tested.. In rheostat mode, if a current is injected into the RW terminal, the magnitude of the current should be such that the developed potential difference between RW and RL terminals is at least 3mV, even at the minimum wiper setting. his ensures that the recommended operating condition of V(RW) V(RL) +.3V is satisfied and the part operates in its most accurate resistance. Minimum and Maximum wiper setting can be calculated as follow, MIN code = (.3V*7)/(Iw*Rtotal), Max code = [(V -.3V)*7]/(I W *R OL ).. t W is the time from a valid SOP condition at the end of a Write sequence of I serial interface, to the end of the self-timed internal non-volatile write cycle.. Parameters with MIN and/or MX limits are % tested at +5, unless otherwise specified. emperature limits established by characterization and are not production tested. UNI SD vs SL iming t F t HIGH t LOW t R t sp SL t SU:D t SU:S t HD:S t HD:D t SU:SO SD (INPU IMING) t t DH t BUF SD (OUPU IMING) FN69 Rev. Page 6 of 5 pril 5,
Pin iming SR SOP SL L SD t SU: t HD: ypical Performance urves = +5 = +5 RESISNE ERROR (%) - RESISNE ERROR (%) - - 5 5 45 65 85 5 5 FIGURE. RESISNE ERROR vs P POSIION [I(RW) = V /R OL ] FOR k () - 5 5 45 65 85 5 5 FIGURE. RESISNE ERROR vs P POSIION [I(RW) = V /R OL ] FOR k (W) = +5 = +5 R INL (MI) R INL (MI) - - - 4 6 8 FIGURE 3. INL vs P POSIION IN RHEOS MODE FOR k () - 4 6 8 FIGURE 4. INL vs P POSIION IN RHEOS MODE FOR k (W) FN69 Rev. Page 7 of 5 pril 5,
ypical Performance urves (ontinued) = +5 3 = +5 R DNL (MI) R DNL (MI) - - 4 6 8 FIGURE 5. DNL vs P POSIION IN RHEOS MODE FOR k () - 4 6 8 FIGURE 6. DNL vs P POSIION IN RHEOS MODE FOR k (W).6. R OL ERROR (%)..8.4. R OL ERROR (%).5. -.5 -.4-4 - 4 6 8 EMPERURE (º) FIGURE 7. R OL ERROR vs EMPERURE FOR k () -. -4-4 6 8 EMPERURE (º) FIGURE 8. R OL ERROR vs EMPERURE FOR k (W).3 = +5.3 = +5.5.5 INL (LSB) INL (LSB) -.5 -.5 -.3 4 6 8 FIGURE 9. INL vs P POSIION IN VOLGE DIVIDER MODE FOR k () -.3 4 6 8 FIGURE. INL vs P POSIION IN VOLGE DIVIDER MODE FOR k (W) FN69 Rev. Page 8 of 5 pril 5,
ypical Performance urves (ontinued). = +5. = +5.5.5 DNL (LSB) -.5 DNL (LSB) -.5 -. 4 6 8 FIGURE. DNL vs P POSIION IN VOLGE DIVIDER MODE FOR k () -. 4 6 8 FIGURE. DNL vs P POSIION IN VOLGE DIVIDER MODE FOR k (W).8.4.6.3 ZS ERROR (LSB).4. ZS ERROR (LSB).. -4-4 6 8 EMPERURE (º) FIGURE 3. ZS ERROR vs EMPERURE FOR k () -4-4 6 8 EMPERURE (º) FIGURE 4. ZS ERROR vs EMPERURE FOR k (W) FS ERROR (LSB) -.3 -.6 -.9 -. -4-4 6 8 EMPERURE (º) FIGURE 5. FS ERROR vs EMPERURE FOR k () FS ERROR (LSB) -.3 -.6 -.9 -. -4-4 6 8 EMPERURE (º) FIGURE 6. FS ERROR vs EMPERURE FOR k (W) FN69 Rev. Page 9 of 5 pril 5,
ypical Performance urves (ontinued) 4 4 3 3 r (ppm/ º) v (ppm/º) 5 35 55 75 95 5 FIGURE 7. FOR RHEOS MODE (k/5k/k) IN ppm [R REF ppm/ ] 5 35 55 75 95 5 FIGURE 8. FOR VOLGE DIVIDER MODE (k/5k/k) IN ppm [R REF ppm/ ] 8 ISB (u) 6 4 WIPER RESISNE ( ) 8 6 4 = +5 = +5 = -4-4 4 8 EMPERURE ( ) FIGURE 9. SNDBY I vs EMPERURE 4 6 8 FIGURE. WIPER RESISNE vs P POSIION WHEN PREISION IS OFF Pin Description Potentiometers Pins RH ND RL he high (RH) and low (RL) terminals of the ISL37 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and the voltage potential on the terminals. With WR set to 7 decimal, the wiper will be closest to RH. With the WR set to, the wiper is closest to RL. he voltage potential on the RH terminal must be higher than voltage potential on RL terminal. RW RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. he position of the wiper within the array is determined by the WR register. REF_, REF_B REF_ and REF_B are pins to connect an external resistor. If application is required to connect RL terminal to GND, then the REF_B pin should also be connected to GND. Warning! Do not connect REF_ to GND under any circumstances. hat may damage the ISL37. Bus Interface Pins SERIL D INPU/OUPU (SD) he SD is a bidirectional serial data input/output pin for I interface. It receives device address, operation code, wiper address and data from an I external master device at the rising edge of the serial clock SL, and it shifts out data after each falling edge of the serial clock. SD requires an external pull-up resistor, since it is an open drain input/output. SERIL LO (SL) his input is the serial clock of the I serial interface. DEVIE DDRESS () he address input is used to set the bit of the 7-bit I interface slave address, see able 4. match in the slave address serial data stream must match with the ddress input pins in order to initiate communication with the ISL37. FN69 Rev. Page of 5 pril 5,
maximum of two ISL37 devices may occupy the I serial bus with addresses 5h and 54h. Principles of Operation he ISL37 is an integrated circuit incorporating one DP with its associated registers, non-volatile memory and an I serial interface providing direct communication between a host and the potentiometer and memory. he resistor array is comprised of individual resistors connected in series. t either end of the array and between each resistor, is an electronic switch that transfers the potential at that point to the wiper. he electronic switches on the device operate in a make before break mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is restored, the contents of the IVR is recalled and loaded into the WR to set the wiper to the initial value. DP Description he DP is implemented with a combination of resistor elements and MOS switches. he physical ends of each DP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). he RW pin of the DP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. he position of the wiper terminal within the DP is controlled by a 7-bit volatile Wiper Register (WR). When the WR of a DP contains all zeroes (WR<6:>: h), its wiper terminal (RW) is closest to its Low terminal (RL). When the WR register of a DP contains all ones (WR<6:>: 7Fh), its wiper terminal (RW) is closest to its High terminal (RH). s the value of the WR increases from all zeroes () to all ones (7 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. While the ISL37 is being powered up, the WR is reset to 4h (64 decimal), which locates RW roughly at the center between RL and RH. fter the power supply voltage becomes large enough for reliable non-volatile memory reading, the WR will be reload with the value stored in a non-volatile Initial Value Register (IVR). he WR and IVR can be read or written to directly using the I serial interface as described in the following sections. Memory Description he ISL37 contains one non-volatile 8-bit Initial Value Register (IVR), one 8-bit non-volatile Mode Select Register (MSR), and two volatile 8-bit registers: Wiper Register (WR) and ccess ontrol Register (R). Memory map of ISL37 is in able. he nonvolatile register (IVR) at address, contains initial wiper position and the volatile register (WR) contains current wiper position. BLE. MEMORY MP DDRESS (hex) NON-VOLILE VOLILE N R Mode Select Register N IVR WR he non-volatile IVR and volatile WR registers are accessible with the same address. he ISL37 is pre-programed with 4h in the IVR. he ccess ontrol Register (R) at address contains information and control bits described below in able. he VOL bit (R<7>) determines whether the access is to wiper registers WR or initial value registers IVR. BLE. ESS ONROL REGISER (R) VOL SHDN WIP (MSB) If VOL bit is, the non-volatile IVR register is accessible. If VOL bit is, only the volatile WR is accessible. Note, value is written to IVR register also is written to the WR. he default value of this bit is. he SHDN bit (R<6>) disables or enables Shutdown mode. When this bit is, DP is in Shutdown mode. Default value of SHDN bit is. he WIP bit (R<5>) is read only bit. It indicates that non-volatile write operation is in progress. It is impossible to write to the WR or R while WIP bit is. he Mode Select Bit in Mode Select Register (MSR<7>) at address allows selection of Rheostat or Voltage Divider Mode, see able 3. Mode Select (MSB) BLE 3. MODE SELE REGISER (MSR) Precision Off When this bit is, DP is in two-terminal Rheostat Mode. In Rheostat Mode, the RH pin should be left unconnected and DP can be used as variable resistor between RW and RL pins. When this bit is, DP is in three-terminal Voltage Divider Mode. In Voltage Divider Mode, signal is applied between RH and RL terminals. otal resistance between RH and RL terminals is precisely matched to external reference resistor. Refer to reference resistor value in nalog Specifications able on page 3. Default value of Mode Select Bit is. (LSB) x x x x x x (LSB) he Precision Off bit (MSR<6>) allows the user to turn off the matching mechanism and use the device as a regular, non- FN69 Rev. Page of 5 pril 5,
precision DP by setting this bit to. Default value of the Precision Off bit is, i.e. matching to external resistor is ON. Note, if the external resistor between REF_/REF_B is not populated, the DP will work as a normal DP without giving 99% precision and with ~4% higher value of the resistance. It is highly recommended to use the bit option (MSR<6>) to turn OFF the precision mode first and then removing the external resistor. ll other bits MSR<5:> are reserved and cannot be written. ny value read from these bits should be ignored. I Serial Interface he ISL37 supports an I bi-directional bus oriented protocol. he protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. he device controlling the transfer is a master and the device being controlled is the slave. he master always initiates data transfers and provides the clock for both transmit and receive operations. herefore, the ISL37 operates as a slave device in all applications. ll communication over the I interface is conducted by sending the MSB of each byte of data first. Protocol onventions Data states on the SD line must change only during SL LOW periods. SD state changes during SL HIGH are reserved for indicating SR and SOP conditions (see Figure ). On power-up of the ISL37, the SD pin is in the input mode. ll I interface operations must be terminated by a SOP condition, which is a LOW to HIGH transition of SD while SL is HIGH (see Figure ). SOP condition at the end of a read operation, or at the end of a write operation, places the device in its standby mode. n, cknowledge, is a software convention used to indicate a successful data transfer. he transmitting device, either master or slave, releases the SD bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SD line LOW to acknowledge the reception of the eight bits of data (see Figure ). he ISL37 responds with an after recognition of a SR condition followed by a valid Identification Byte, and once again after successful receipt of an ddress Byte. he ISL37 also responds with an after receiving a Data Byte of a write operation. he master must respond with an after receiving a Data Byte of a read operation valid Identification Byte contains as the five MSBs, and the following bit matching the logic value present at pin. he LSB is the Read/Write bit. Its value is for a Read operation, and for a Write operation (See able 4). BLE 4. IDENIFIION BYE FORM R/W (MSB) Logic value at pin (LSB) ll I interface operations must begin with a SR condition, which is a HIGH to LOW transition of SD while SL is HIGH. he ISL37 continuously monitors the SD and SL lines for the SR condition and does not respond to any command until this condition is met (see Figure ). SR condition is ignored during the power-up of the device. SL SD SR D D D SOP SBLE HNGE SBLE FIGURE. VLID D HNGES, SR, ND SOP ONDIIONS FN69 Rev. Page of 5 pril 5,
SL FROM MSER 8 9 SD OUPU FROM RNSMIER HIGH IMPEDNE SD OUPU FROM REEIVER HIGH IMPEDNE SR FIGURE. NOWLEDGE RESPONSE FROM REEIVER WRIE SIGNLS FROM HE MSER S R IDENIFIION BYE DDRESS BYE D BYE S O P SIGNL SD SIGNLS FROM HE SLVE FIGURE 3. BYE WRIE SEQUENE SIGNLS FROM HE MSER S R IDENIFIION BYE WIH R/W= DDRESS BYE S R IDENIFIION BYE WIH R/W= S O P SIGNL SD SIGNLS FROM HE SLVE FIRS RED D BYE LS RED D BYE FIGURE 4. RED SEQUENE Write Operation Write operation requires a SR condition, followed by a valid Identification Byte, a valid ddress Byte, a Data Byte, and a SOP condition. fter each of the three bytes, the ISL37 responds with an. t this time, the device enters its standby state (see Figure 3). he non-volatile write cycle starts after a SOP condition is determined and requires up to ms delay for the next non-volatile write. Read Operation Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 4). he master initiates the operation issuing the following sequence: a SR, the Identification byte with the R/W bit set to, an ddress Byte, a second SR, and a second Identification byte with the R/W bit set to. fter each of the three bytes, the ISL37 responds with an. hen the ISL37 transmits Data Bytes as long as the master responds with an during the SL cycle following the eighth bit of each byte. he master terminates the read operation (issuing a and SOP condition) following the last bit of the last Data Byte (see Figure 4). In order to read back the non-volatile IVR, it is recommended that the application reads the R first to verify the WIP bit is. If the WIP bit (R[5]) is not, the host should repeat its reading sequence again. FN69 Rev. Page 3 of 5 pril 5,
Rheostat Mode onfiguration When DP is used as a two-terminal variable resistor, the RH terminal should be left unconnected and MSR<7> is. Resistance between RW and RL terminal can be calculated by Equation : Rtotal Ri = ----------------- i (EQ. ) 7 Where i is a decimal code from to 7. Note, that resistance accuracy will decrease at the lowest and the highest taps, where voltage drops <.3V. In other words, a minimum and maximum decimal code at which the DP resistance not exceed 3% precision is as shown in Equations and 3: imin imax.3 7 = ----------------------------------------- (EQ. ) Iwiper Rtotal Vcc.3 7 = --------------------------------------------- (EQ. 3) Iwiper Rtotal Where Iwiper is a current going through the wiper terminal. Voltage Divider Mode onfiguration In Voltage Divider Mode, voltage or signal is applied between RH and RL terminals and MSR<7> is. potential at RH terminal must be higher than at RL terminal at any time. otal resistance between RH and RL terminal is fixed and matched to external reference resistor. Voltage on the wiper terminal RW can be calculated by Equation 4: Vrw i Vrh Vrl = ----------------------- i (EQ. 4) 7 Where i is a decimal code from to 7. Note, that the wiper voltage accuracy will decrease at the lowest and the highest taps, where it is less than.3v from ground or from V respectively. pplications Information In order to get better accuracy in applications where RL pin is connected to GND, it is highly recommended that REF_B pin is also connected to GND. he coupling capacitors of µf and.µf should be placed close to V pin. Revision History DE REVISION HNGE 4/6/ FN69. Page description of Pin references able 3 changed to able 4. Page 5, thd:d parameter test condition,"from SL rising edge..." changed to "From SL falling edge..." dded MSL note to ordering information. Replaced POD to recent version with following changes:. Removed mention of "b" from Note 4 since "b" does not exist on the drawing.. dded Note 6 callout to lead width on "Bottom View". 3. orrected the word "indentifier" in Note 6 to read "identifier". 5/6/9 FN69. Initial Release of Datasheet. Issued FN69 making it a Rev. opyright Intersil mericas LL 9-. ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see www.intersil.com FN69 Rev. Page 4 of 5 pril 5,
Package Outline Drawing L.3x3B LED HIN DUL FL PGE (DFN) WIH E-PD Rev, 3/ 3. B 6 PIN # INDEX RE 6 PIN INDEX RE 3..38 +./ -.5.5 6 4.5 +.5/ -.7 OP VIEW (4X).5.64 +./ -.5 BOOM VIEW x.4 +/-. PGE OULINE (x.4) (x.) SEE DEIL "X" (X.5)..38.75.5 SIDE VIEW SEING PLNE.8 (8x.5).64 YPIL REOMMENDED LND PERN. REF 5.5 DEIL "X" NOES:.. 3. 4. 5. 6. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to MSE Y4.5m-994. Unless otherwise specified, tolerance : Decimal ±.5 Dimension applies to the metallized terminal and is measured between.8mm and.3mm from the terminal tip. iebar shown (if present) is a non-functional feature. he configuration of the pin # identifier is optional, but must be located within the zone indicated. he pin # identifier may be either a mold or mark feature. FN69 Rev. Page 5 of 5 pril 5,