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421 DESIGN OF BRAUN S MULTIPLIER USING HAN CARLSON AND LADNER FISCHER ADDERS CHETHAN BR 1, NATARAJ KR 2 Dept of ECE, SJBIT, Bangalore, INDIA 1 chethan.br44@gmail.com, 2 nataraj.sjbit@gmail.com ABSTRACT Multiplication is one of the basic and essential building blocks in Digital Signal Processing DSP) applications including Fast Fourier Transform FFT), Digital Filters etc. Multiplication in such high performance application requires a parallel array multiplier to perform multiplication in parallel fashion to achieve high execution speed and meet the performance demands. A typically used structure to implement such array multiplier is Braun design. Braun multiplier is simple parallel array multiplier. In this paper, a new design for Braun Multiplier have been proposed and proposed multiplier design uses a parallel prefix adders like Han- Carlson and Ladner-Fischer adder to replace Ripple carry adder at the final stage. The architecture of Braun multiplier is modified in this paper to reduce the delay resulting from the ripple carry adder and to obtain faster multiplication results of two binary numbers. Keywords: - Braun s Multiplier, Ripple carry adder, Carry save adder, Parallel prefix adders, Han-Carlson adder, Ladner Fischer adder, Bypassing techniques. 1. INTRODUCTION Digital Multiplication is fundamental and extensively used operation in arithmetic unit and signal processing operation. Multipliers are key components of many high performance systems such as FIR filters, microprocessors, image processors, Digital signal processors etc. In low power VLSI applications, it is desirable that the multiplier should consume less power or less area in the design or achieve high execution speed or combination of all these in a single multiplier [1]. The system s performance is usually determined by the performance of the multiplier because the multiplier used in the design generally contributes significant amount of delay and consumes most of the area in the design. Hence, optimizing the speed and area of the multiplier is a major design issue. In order to achieve high speed of execution and meet the performance demands in DSP applications, parallel array multipliers are widely used. One such widely used parallel array multiplier is the Braun s Multiplier [1][2]. The Braun s Multiplier is generally called as the carry Save Array Multiplier. 1.1 Carry Save Adder Carry save adder is a digital adder which computes the sum of three or more n-bit binary numbers. Carry save adder utilizes the same structure as full adder. It produces two outputs. The output of carry save adder consists of: One sequence of partial sum bits One sequence of carry bits. Figure 1: Carry Save Adder Figure 2: Ripple Carry adder All the columns in carry save adder can be perform addition operation in parallel without relying on the result of the previous column and produces two outputs sum and carry. The sum bit and carry bit are then be recombined in a normal addition to produce the correct result. 1.2 Ripple Carry Adder A simple ripple carry adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed by cascading the full adders in series fashion. The carry output from one full adder stage is connected to the carry input of the next full adder stage in the chain. Fig 2 structure of 4-bit ripple carry adder. The major drawback of ripple carry adder is that the total propagation delay of carry from input stage to output stage, which is directly proportional to the total number of stages in the Ripple Carry Adder. 2. BRAUN MULTIPLIER Braun Multiplier is a simple parallel multiplier generally called as carry save multiplier. This parallel multiplier is used to perform the unsigned bit multiplication. The Braun multiplier structure consists of the array of array

422 of AND gates and full adders. To implement the n*n multiplier nn-1) full adders and n 2 AND gate are required[1]. The architecture of 4 bit multiplier is illustrated in fig 3. Figure 3: Braun s Multiplier The delay introduced by the Braun s multiplier depends on the delay of the full adders and also on the delay of the final adder in the last stage which is a ripple carry adder. The dynamic power dissipation of the multiplier resulting from the switching activities can be reduced via bypassing techniques like Row bypassing, column bypassing and Row & Column bypassing techniques [2]. In Row Bypassing multiplier, if the multiplier bit bi is zero, then the addition operations in the i-th row can be bypassed, thus providing directly i-1)-th row outputs directly to the i+1)-th row [4]. Thus, the switching activities in the i-th row reduced and hence the power dissipation. The 4 bit Braun Multiplier with Row Bypassing technique is illustrated in Fig 4. Figure 4: Row Bypassing Braun s Multiplier In a Column bypassing Braun multiplier, the addition operation is disabled in the column if the corresponding multiplicand bit aj is zero [3] [6]. The 4*4 column bypassing based Braun multiplier is illustrated in fig 5. A low power multiplier with Row and Column bypassing can be obtained by simplification of full adders. Here the half adders are replaced by the incremental adders or A + 1 adders and the full adders are replaced by A + B + 1 adders [5]. This is as shown in fig 6. Figure 5: Column Bypassing Braun s Multiplier Figure 6: RC Bypassing Braun s Multiplier

423 3. PROPOSED WORK The delay of the Braun multiplier depends on the full adders and also on the final adder present in the last stage. In conventional design of Braun multiplier, ripple carry adder is used at the last stage. The delay introduced by the multiplier can be reduced by replacing the ripple carry adder with parallel prefix adders like Han-Carlson and Ladner-Fischer adders. The proposed 4*4 multiplier s block diagram is shown in fig 7 where we have used parallel prefix adders like Han-Carlson adder and Ladner Fischer adder at the 4 th stage of Braun multiplier. Figure 7: Block diagram of proposed Braun Multiplier 3.1 Han Carlson Adder Han Carlson is a parallel prefix form of carry look-ahead adder. The Han Carlson adder tree is a family of network between kogge stone adder and Brent Kung adder. To compute the first stages of parallel prefix, this structure used Brent Kung stage followed by kogge stone adder design and terminated by another Brent Kung stage for the terminal stage of the prefix computations [8]. The construction 4 bit and 8bit Han Carlson adder is shown in fig 8, fig 9. B3 A3 B2 A2 B1 A1 B0 A0 P3,G3) P2,G2) P1,G1) P0,G0) Cp3,Cg3) Cp1,Cg1) Cp0,Cg0) P0,G0) Figure 8: 4 bit Han Carlson adder Figure 9: 8 bit Han Carlson adder 3.2 Ladner Fischer Adder Ladner Fisher adder is a parallel prefix form of carry Look-ahead adder. Usually these adders are represented in the parallel prefix graph consisting of carry operator nodes. The Ladner Fischer adder tree is a family of network between Sklansky and Brent Kung adder. Ladner Fischer parallel prefix adder is considered as the fastest adder with focus on design time and commonly used adder structure for high performance in industries [7]. The structure of 4 bit and 8 bit Ladner-Fischer adder sis shown in fig10 and fig 11. B3 A3 B2 A2 B1 A1 B0 A0 P3,G3) P2,G2) P1,G1) P0,G0) Cp3,Cg3) Cp1,Cg1) Cp0,Cg0) P0,G0) Figure 10: 4 bit Ladner Fischer adder Figure 11: 8 bit Ladner Fischer adder

424 4. SIMULATION RESULTS AND COMPARISON The Braun s multiplier using various Bypassing techniques is designed using Verilog HDL in Xilinx 13.2. The performance of proposed Braun s multiplier is analysed and compared against the conventional Braun s multiplier design. The simulated waveforms for 4*4 Braun s multiplier with ripple carry adder, Han Carlson and Ladner Fischer adder at the final stage shown below. 4.1 Ripple Carry Adder at the final stage Figure 12 : Standard Braun Multiplier Figure 13: Row Bypassing Braun Multiplier Figure 14: Column Bypassing Braun multiplier 4.2 Han Carlson Adder at the final stage Figure 15: Row and Column Bypassing Braun multiplier Figure 16: Standard Braun Multiplier Figure 17: Row Bypassing Braun Multiplier Figure 18: Column Bypassing Braun multiplier Figure 19: Row and column bypassing Braun Multiplier

425 4.3 Ladner Fischer Adder at the final stage Figure 20: Standard Braun Multiplier Figure 21: Row Bypassing Braun Multiplier Figure 22: Column Bypassing Braun multiplier Figure 23: Row and Column Bypassing Braun multiplier Table: 1. Comparison of Maximum Combinational Path delay in Nano seconds ns) for different Braun s multipliers for Spartan-3E Han Carlson adder at last Ladner Fischer adder at RCA at the final stage Design stage last stage 4*4 8*8 16*16 4*4 8*8 16*16 4*4 8*8 16*16 Braun s Multiplier 12.566 21.773 39.438 12.370 19.856 34.558 12.745 20.039 34.558 Row Bypassing 12.709 22.836 48.142 13.489 20.178 41.772 12.537 19.603 48.515 Column Bypassing 11.418 20.549 39.438 11.214 19.333 34.998 12.343 18.612 34.558 Row and column Bypassing 10.615 21.132 39.643 10.466 19.025 33.910 11.731 18.226 33.537 The comparison between conventional Braun Multiplier and proposed Barun Multiplier interms of delay is illustrated in fig24, fig25, fig 26. Figure 24: Total delay for 4*4 Braun multiplier

426 Figure 25: Total delay for 8*8 Braun Multiplier Figure 26: Total delay for 16*16 Braun Multiplier CONCLUSION Braun s Multiplier for various bypassing techniques is designed using parallel prefix adders like Han Carlson and Ladner Fischer adders. The multiplier is designed for 2 inputs A and B each of width 4, 8 and 16 bits. The simulated results in terms of combinational path delay are shown in Table 1. Form the above table it is evident that, the implementation of Braun multiplier using parallel prefix adder at the final stage for higher bit multiplication reduces delay compared conventional Braun multiplier design where ripple carry adder is used. REFERENCES [1] Anitha R, Alekhya Nelapati, Lincy Jesima W, Bagyaveereswaran, Comparative Study of High performance Braun s Multiplier using FPGAs, IOSR Journal of Electronics and Communication Engineering IOSRJECE),Volume 1, Issue 4, pg no:33-37 May-June 2012). [2] Jun-ni Ohban, Vasily G. Moshnyaga, and Koji Inoue, Multiplier Energy Reduction through Bypassing of Partial Products, IEEE, pg no 13-17, 2002. [3] Ming-Chen Wen, Sying-Jyan Wang, and Yen-Nan Lin, Low Power Parallel Multiplier with Column Bypassing IEEE, pg no1638-1641,2005. [4] Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu and Chia-Jen Sheu Low Power Multipliers Using Enhenced Row Bypassing Schemes IEEE,pg no 136-141, 2007. [5] M.-C. Wen, S.-J, Wang and Y.-N. Lin, Low-power parallel multiplier with column bypassing, Electronics Letters, Vol. 41 No. 10, 2005 [6] Jin-Tai Yan and Zhi-Wei Chen, Low-Power Multiplier Design with Row and Column Bypassing, IEEE, pg no 227-230, 2009 [7] Pakkiraiah Chakali, Madhu Kumar Patnala, Design of High Speed Ladner-Fischer Based Carry Select Adder International Journal of Soft Computing and Engineering IJSCE), Volume-3, pg no 173-176, 2013. [8] Sreenivaas Muthyala Sudhakar,Kumar Chidambaram and Earl E. Swartzlander Jr. Hybrid Han-Carlson Adder IEEE, pg no 818-821, 2012..