MITSUBISHI SEMICONDUCTOR <pplicati Specific Specific Intelligent Power Power Module> TYPE TYPE INTEGRTED FUNCTIONS ND FETURES 3-Phase IGBT inverter bridge cfigured by the latest 3rd. generati IGBT and diode technologies. Circuit for dynamic braking of motor regenerative energy. Inverter output current capability Io (Note ) : Type Name % load 4.8 (rms) 5% over load 7.2 (rms), min (Note ) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the above loading cases is defined as : Iop = Io 2 INTEGRTED DRIE, PROTECTION ND SYSTEM CONTROL FUNCTIONS: For P-Side IGBTs : Drive circuit, High-speed photo-couplers, Short circuit protecti (SC), Bootstrap circuit supply scheme (Single drive power supply ) and Under-voltage protecti (U). For N-Side IGBTs : Drive circuit, Short-circuit protecti (SC), Ctrol supply Under voltage and Over voltage protecti (O/U), System Over temperature protecti (OT), Fault output signaling circuit (Fo), and Current-Limit warning signal output (CL). For Brake circuit IGBT : Drive circuit. Warning and Fault signaling : FO : Short circuit protecti for lower-leg IGBTs and Input interlocking against spurious arm shoot-through. FO2 : N-side ctrol supply abnormality locking (O/U) FO3 : System over-temperature protecti (OT). CL : Warning for inverter current overload cditi For system feedback ctrol : nalogue signal feedback reproducing actual inverter output phase current (3φ). Input Interface : 5 CMOS/TTL compatible, Schmitt trigger input, and rm-shoot-through interlock protecti. PPLICTION coustic noise-less.5kw/c4 Class 3 Phase inverter and other motor ctrol applicatis. PCKGE OUTLINES 2.45 ±.3 (.35).5 2 ±.3 (7.75).2 8.5 ± 7.5 ±.5 6 ±.3 56 ±.8 76.5 ± 23 2.5 83.5 ±.5 92.5 ± 3 32 33 34 35 36 4-R4.6 ±.3 5.8 ±.8 5 4-φ4.6.5 78.75 2.4 ± 8.5 3 27 ± Terminals ssignment: CBU+ 2 CBU 3 CB+ 4 CB 5 CBW+ 6 CBW 7 GND 8 DL 9 DH CL FO 2 FO2 3 FO3 4 CU 5 C 6 CW 7 UP 8 P 9 WP 2 UN 2 N 22 WN 23 Br 3 P 32 B 33 N 34 U 35 36 W LBEL (Fig. ) Jan. 2
INTERNL FUNCTIONS BLOCK DIGRM pplicati Specific Intelligent Power Module CBU CBU+ CB CB+ CBW CBW+ Protecti Input Circuit Circuit Drive Circuit Brake resistor cnecti, Inrush preventi circuit, etc. C 4 class line input R S T P B Photo Coupler U W M Z C N T S C 4 class line output Z : Surge absorber. C : C filter (Ceramic cdenser 2.2~6.5nF) [Note : dditially an appropriate Line-to line surge absorber circuit may become necessary depending the applicati envirment]. Current sensing circuit Input signal cditiing Drive Circuit Fo Logic Protecti circuit Ctrol supply fault sense CU C CW UP P WP UN N WN Br CL,FO,FO2,FO3 GND DL DH nalogue signal output correspding to PWM input Fault output each phase current (5 line) Note ) (5 line) Note 2) (5 line) Note 3) Note ) To prevent chances of signal oscillati, a series resistor (kω) coupling at each output is recommended. Note 2) By virtue of integrating a photo-coupler inside the module, direct coupling to CPU, without any extemal opto or transformer isolati is possible. Note 3) ll outputs are open collector type. Each signal line should be pulled up to plus side of the 5 power supply with approximately 5.kΩ resistance. Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the SIPM against catastrophic high surge voltage. For extra precauti, a small film snubber capacitor (.~.22µF, high voltage type) is recommended to be mounted close to these P and N DC power input pins. (Fig. 2) MXIMUM RTINGS (Tj = 25) INERTER PRT (Including Brake Part) Cditi CC CC(surge) P or N P(S) or N(S) ±Ic(±Icp) Ic(Icp) IF(IFP) Supply voltage Supply voltage (surge) Each output IGBT collector-emitter static voltage Each output IGBT collector-emitter surge voltage Each output IGBT collector current Brake IGBT collector current Brake diode anode current pplied between P-N pplied between P-N, Surge-value pplied between P-U,, W, Br or U,, W, Br-N pplied between P-U,, W, Br or U,, W, Br-N TC = 25 Note : ( ) means IC peak value 9 2 2 ±5 (±3) 5 () 5 () CONTROL PRT Cditi pplied between DH-GND, CBU+-CBU, DH, DB Supply voltage 2 CB+-CB, CBW+-CBW DL CIN FO IFO CL ICL ICO Supply voltage Input signal voltage Fault output supply voltage Fault output current Current-limit warning output voltage CL output current nalogue-current-signal output current pplied between DL-GND pplied between UP P WP UN N WN Br-GND pplied between FO FO2 FO3-GND Sink current of FO FO2 FO3 pplied between CL-GND Sink current of CL Sink current of CU C CW 7.5 ~ DL+.5.5 ~ 7 5.5 ~ 7 5 ± Jan. 2
TOTL SYSTEM Cditi Tj Tstg TC ISO Note 2) : Juncti temperature Storage temperature Module case operating temperature Isolati voltage Mounting torque (Note 2) (Fig. 3) 6 Hz sinusoidal C for minute, between all terminals and base plate. Mounting screw: M3.5 2 ~ +25 4 ~ +25 2 ~ + 25.78 ~.27 The item defines the maximum juncti temperature for the power elements (IGBT/Diode) of the SIPM to ensure safe operati. However, these power elements can endure instantaneous juncti temperature as high as 5. To make use of this additial temperature allowance, a detailed study of the exact applicati cditis is required and, accordingly, necessary informati is to be provided before use. rms N m CSE TEMPERTURE MESUREMENT POINT (3mm from the base surface) TC (Fig. 3) THERML RESISTNCE Rth(jc)Q Rth(jc)F Rth(jc)QB Rth(jc)FB Rth(c-f) Juncti to case Thermal Resistance Ctact Thermal Resistance Cditi Inverter IGBT (/6) Inverter FWDi (/6) Brake IGBT Brake FWDi Case to fin, thermal grease applied ( Module) Min. Typ. Max..9 5.3 3. 7.3.4 ELECTRICL CHRCTERISTICS (Tj = 25, DH = 5, DB = 5, DL = 5 unless otherwise noted) CE(sat) EC FBr t tc() toff tc(off) trr IDH IDL th() th(off) Ri CE(sat)Br Collector-emitter saturati voltage FWDi forward voltage Brake IGBT Collector-emitter saturati voltage Brake diode forward voltage Switching times FWD reverse recovery time Short circuit endurance (Output, rm, and Load, Short Circuit Modes) Switching SO DH Circuit Current DL Circuit Current Input threshold voltage Input off threshold voltage Input pull-up resistor Cditi DL = 5, DH = DB = 5 Input = ON, Tj = 25, Ic = 5 Tj = 25, Ic = 5, Input = OFF DL = 5, DH = 5 Input = ON, Tj = 25, Ic = 5 Tj = 25, IF = 5, Input = OFF /2 Bridge inductive, Input = ON CC = 6, Ic = 5, Tj = 25 DL = 5, DH = 5, DB = 5 Note : t, toff include delay time of the internal ctrol circuit. CC 8, Input = ON (One-Shot) Tj = 25 start 3.5 DH = DB = 6.5 CC 8, Tj 25, Ic < IOL(CL) operati level, Input = ON, 3.5 DH = DB = 6.5 DL = 5, DH = 5, CIN = 5 DL = 5, DH = 5, CIN = 5 Integrated between input terminal-dh Min..3 Typ..2.5 2.2.9.2 No FO output.8.4 2.5 3. 5 Max. 3.6 3.5 3.6 3.5 2..4 4..6 5 5 2. 4. No destructi FO output by protecti operati No destructi No protecting operati kω Jan. 2
ELECTRICL CHRCTERISTICS (Tj = 25, DH = 5, DB = 5, DL = 5 unless otherwise noted) Cditi Min. Typ. fpwm PWM input frequency TC, Tj 25 2 txx llowable input -pulse width DH = 5, DL = 5, TC = 2 ~ + Note 3) 2 tdead llowable input signal dead time Relates to correspding inputs (Except brake part) for blocking arm shoot-through TC = 2 ~ + 4. tint Input inter-lock sensing Relates to correspding inputs (Except brake part) CO C+(2%) C (2%) CO C+ C C(2%) rch td(read) ICL(H) ICL(L) ±IOL SC OT OTr UDB UDBr UDH UDHr ODH ODHr tdv IFO(H) IFO(L) nalogue signal linearity with output current Offset change area vs temperature nalogue signal output voltage limit nalogue signal overall linear variati nalogue signal data hold accuracy nalogue signal reading time Signal output current of CL operati Over tenperature protecti Supply circuit under and over voltage protecti Fault output current Idle ctive CL warning operati level Short circuit current trip level Filter time Idle ctive Ic = DH = 5 Ic = IOP(2%) DL = 5 Ic = IOP(2%) TC = 2 ~ DH = 5, DL = 5, TC = 2 ~ DL = 5, DH = 5, TC = 2 ~ (Note 4) Tj = 25 (Fig. 7), (Note 5) (Note 3) : (a) llowable minimum input -pulse width : This item applies to P-side circuit ly. (b) llowable maximum input -pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit. (Note4) : CL output : The "current limit warning (CL) operati circuit outputs warning signal whenever the arm current exceeds this limit. The circuit is reset automatically by the next input signal and thus, it operates a pulse-by-pulse scheme. (Note5) : The short circuit protecti works instantaneously when a high short circuit current flows through an internal IGBT rising up momentarily. The protecti functi is, thus meant primarily to protect the SIPM against short circuit distracti. Therefore, this functi is not recommended to be used for any system load current regulati or any over load ctrol as this might, cause a failure due to excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropriately used for such current regulati or over load ctrol operati. In other words, the PWM signals to the SIPM should be shut down, in principle, and not to be restarted before the juncti temperature would recover to normal, as so as a fault is feed back from its FO pin of the SIPM indicating a short circuit situati. (Fig.4) Ic > IOP(2%), DH = 5, DL = 5 (Fig. 4) CO-C±(2%) Correspd to max. 5 data hold period ly, Ic = IOP(2%) (Fig. 5) fter input signal trigger point (Fig. 8) Open collector put DL = 5, DH = 5 TC = 2 ~ + Tj 25 Open collector output.87.77 2.97 4. 5 2.9 2.7..5.5.55 8. 6.5 65 2.27.7 3.37 5. 3 5.6 38. 9..5 2. 2.5 9.2 7.5 Max. 5 5 2.57.47 3.67.7 5 9.68 55. 2 2. 2.5 2.75 3.25 2.5 8.65 khz ns m % µ µ RECOMMENDED CONDITIONS CC DH, DB Supply voltage Ctrol supply voltage DL Ctrol supply voltage DH, DB, Supply voltage ripple DL CIN() Input ON voltage CIN(off) Input OFF voltage fpwm PWM Input frequency tdead rm shoot-through blocking time Cditi pplied between P-N pplied between DH-GND, CBU+-CBU, CB+-CB, CBW+-CBW pplied between DL-GND Using applicati circuit Using applicati circuit Min. 3.5 4.8 4.8 2 4. Typ. Max. 6 8 5. 6.5 5. 5.2 +.3 5 / khz Jan. 2
Fig. 4 OUTPUT CURRENT NLOGUE SIGNLING LINERITY Fig. 5 OUTPUT CURRENT NLOGUE SIGNLING DT HOLD DEFINITION 5 C 4 min max C (2%) DH=5 DL=5 TC= 2~ C C 5 C() 3 2 4 3 2 nalogue output signal data hold range C C+(2%) C+ 2 3 4 rch= CH(5) CH(55)-CH(5) CH(5) CH(55) Note ; Ringing happens around the point where the signal output voltage changes state from analogue to data hold due to test circuit arrangement and instrumentatial trouble. Therefore, the rate of change is measured at a 5 delayed point. Real load current peak value.(%)(ic=io 2) Fig. 6 INPUT INTERLOCK OPERTION TIMING CHRT Input signal CIN(p) of each phase upper arm Input signal CIN(n) of each phase lower arm Gate signal o(p) of each phase upper arm (SIPM internal) Gate signal o(n) of each phase upper arm (SIPM internal) Error output FO Note : Input interlock protecti circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simultaneously in LOW level. By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and FO signal is outputted. fter an input interlock operati the circuit is latched. The FO is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later. Fig. 7 TIMING CHRT ND SHORT CIRCUIT PROTECTION OPERTION Input signal CIN of each phase upper arm Short circuit sensing signal S Gate signal o of each phase upper arm(sipm internal) SC delay time Error output FO Note : Short circuit protecti operati. The protecti operates with FO flag and reset a pulse-by-pulse scheme. The protecti by gate shutdown is given ly to the IGBT that senses an overload (excluding the IGBT for the Brake ). Jan. 2
Fig. 8 INERTER OUTPUT NLOGUE CURRENT SENSING ND SIGNLING TIMING CHRT. CIN (hold) off off N-side IGBT Current N-side FWDi Current IC (S) +ICL ICL C CL Ref off t(hold) Delay time td(read) Fig. 9 STRT-UP SEQUENCE Normally at start-up, Fo and CL output signals will be pulled-up High to DL voltage (OFF level); however, FO output may fall to Low (ON) level at the instant of the first ON input pulse to an N-Side IGBT. This can happen particularly when the boot-strap capacitor is of large size. FO resetting sequence (together with the boot-strap charging sequence) is explained in the following graph DC-Bus voltage Ctrol voltage supply Boot-strap voltage N-Side input signal PN DH, DL DB CIN(N) PWM starts a) b) Fig. RECOMMENDED I/O INTERFCE CIRCUIT DL(5) SIPM 5.kΩ R UP,P,WP,UN,N,WN,Br R CPU FO,FO2,FO3,CL kω CU,C,CW.nF.nF GND(Logic) P-Side input signal CIN(P) Brake input signal FO output signal CIN(Br) FOI a) Boot-strap charging scheme : pply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 2 number of pulses = ~ 5 depending the boot-strap capacitor size) b) FO resetting sequence: pply ON signals to the following input pins : Br Un/n/Wn Up/p/Wp in that order. Jan. 2