Testing Dely Fults in Asynchronous Hnshke Circuits Feng Shi Electricl Engineering Dept. Yle University New Hven, Connecticut feng.shi@yle.eu Yiorgos Mkris Electricl Engineering Dept. Yle Univerisity New Hven, Connecticut yiorgos.mkris@yle.eu ABSTRACT As clss of synchronous circuits, hnshke circuits re esigne to tolerte vrition of gte elys. However, certin timing constrints, such s the unle t ssumption, re exploite in the single-ril implementtion of these circuits in orer to simplify them. Therefore, ny ely fult in the circuit my cuse one of two prolems, nmely performnce egrtion or logic errors. To ress the chllenges incurre y the utonomous ehvior of hnshke circuits uring t-spee test, we propose test methos for oth types of ely fults se on DFT strtegy which gretly simplifies the complexity of test genertion. The efficiency of the propose methoology is emonstrte through experimentl results on severl hnshke circuits. Ctegories n Suject Descriptors B.7.3 [Integrte Circuits]: Reliility n Testing Generl Terms Algorithms, Reliility, Verifiction Keywors Asynchronous Circuits, Hnshke Circuits, Dely Fults, Test Genertion. INTRODUCTION The vntges of synchronous circuits over their synchronous counterprts re emonstrte not only y cemic reserch ut lso y commercil proucts, such s the newly-relese synchronous ARM996HS TM processor []. Asynchronous circuits hve the potentil for higher performnce, lower power consumption n esign reusility. At the sme time, they voi key emerging chllenge of tritionl synchronous esign, nmely high-frequency clock istriution. As chip complexity increses, clock skew effects re significntly mplifie, mking the prolem intrctle. Consequently, interest in synchronous circuits hs resurfce n severl commercil proucts hve lrey een esigne. Despite the recent strek of progress, the evelopment of CAD solutions for the esign n test of synchronous circuits is fr from Permission to mke igitl or hr copies of ll or prt of this work for personl or clssroom use is grnte without fee provie tht copies re not me or istriute for profit or commercil vntge n tht copies er this notice n the full cittion on the first pge. To copy otherwise, to repulish, to post on servers or to reistriute to lists, requires prior specific permission n/or fee. ICCAD 6, Novemer 5 9, 26, Sn Jose, CA Copyright 26 ACM -59593-389-/6/...$5.. eing sufficient. Among these issues, we focus on the prolem of testing synchronous circuits. Due to the utonomous ehvior of synchronous circuits, mnufcturing efects my emonstrte themselves in ifferent wy thn in synchronous circuits n, thus, require ifferent test methoology. Consierle reserch [2, 4, 8,,, 3] hs een one on test genertion n esign for testility (DFT) methos for stuck-t fults in vrious clsses of synchronous circuits. However, not much reserch [3, 5, 7, 2] hs een conucte on testing ely fults. Given the inherent roustness of mny clsses of synchronous circuits to timing vritions, ely fult my only egre their performnce. However, most prcticl synchronous circuits operte correctly y ssuming tht the implementtion oeys certin timing constrints, hence they re no longer totlly roust. Therefore, in these circuits, ely fult my lso cuse the circuit to mlfunction, i.e. generte logic errors. In ition, the utonomous ehvior of synchronous circuits implies tht the existing test genertion n test ppliction methos for ely fults in synchronous circuits cnnot e pplie irectly to synchronous circuits. Inste, customize methos re necessry. In this pper, we stuy the two forementione types of ely fults in synchronous circuits, we propose test methoologies for ech of them, n we illustrte the effectiveness of our methos using one of the most estlishe esign styles of synchronous circuits, nmely hnshke circuits. The rest of this pper is orgnize s follows. First, in Section 2, we riefly introuce the esign n implementtion of hnshke circuits, s well s the full-scn technique use for testing stuck-t fults in these circuits. Then, in Section 3, we clssify the two types of ely fults in hnshke circuits n outline the chllenges in testing fults in ech of the two clsses. In Section 4, we propose test methos for oth types of ely fults n in Section 5 we provie experimentl results tht emonstrte the efficiency of these methos. 2. HANDSHAKE CIRCUITS As one of the most estlishe esign styles of synchronous circuits, hnshke circuits hve fully utomte esign flow from the high-level ehviorl escription to the physicl lyout, s well s test solutions for stuck-t fults. 2. Design n Implementtion of HS Circuits A hnshke circuit is network of hnshke components, connecte y point-to-point hnshke chnnels, where ll communiction tkes plce vi hnshking. It is the intermeite representtion in the fully utomtic compiltion of Hste progrm to VLSI circuit. In the esign flow of hnshke circuits, first, highlevel esign entry is written in CSP-like progrmming lnguge 93
Control lock Strt Hnshke control Request Acknowlege Ltch control si C se L q Z so Conitions Prmeters Locl clock(s) Inputs Outputs Logic Stte Dt pth Register Reset Figure : Gte-Level Implementtion of Hnshke Circuit clle Hste. Then, it is compile n trnslte in trnsprent wy into hnshke circuits. After tht, the gte-level implementtion of the hnshke circuit is generte y replcing ll iniviul components with their gte-level implementtions. The gte-level single-ril implementtion of hnshke circuit cn e prtitione into control lock n t pth s illustrte in Figure. The control lock opertes on hnshke signls, while the t pth works on Boolen signls. The interfce etween the control lock n the t pth consist of the following three types of signls: conitions, prmeters, n locl clock signls. The control lock uses the conition signls in comintion with its internl stte to etermine the next ction. Prmeters re use y the control lock to control the Boolen logic in the t pth, for instnce, y setting multiplexers in the correct stte. The locl clock signls re generte y the control lock to enle tpth register to cpture new t vlue. 2.2 Testing Stuck-At Fults Using Full-Scn Besies the functionl test metho in [6] n the prtil-scn metho in [9, ], full-scn test metho ws propose in [4, 5], exploiting commercil test tools for synchronous circuits to chieve high fult coverge while simplifying the test genertion proceure for hnshke circuits. Before scn insertion, comintionl loops in the circuit re remove y inserting trnsprent scn flip-flops. Then, ll stte-holing cells re replce y their scnnle equivlents, which re connecte together to form scn chin. After tht, the glol control signls n logic re e into the circuit n connecte to the scn elements, n the scn-testle netlist is generte. Menwhile, the netlist is remoele y replcing originl scn cells with their remoele equivlents to generte two seprte netlists for the control lock n the t pth respectively, which re rele y commercil test tools for performing test genertion. Then, test-protocol expnsion proceure trnsltes the initil protocols generte y the ATPG tools into the top-level protocols. The ove full-scn metho ws refine in [3] y introucing multiplexer-se scnnle C-elements, s illustrte in Figure 2. The propose metho significntly reuces the overhe in performnce n re of the scn testle circuit. Moreover, the ltch in Figure 2 is often shre with n existing scn ltch/flip-flop in the tpth, which further reuces the test cost. However, ny two Figure 2: A Mux-se Scn C-Element multiplexer-se scn elements connecte in series cnnot cpture the circuit response t the sme time, hence they cnnot e enle t the sme time n re, thus, connecte to ifferent scn enle signls. Therefore, testing the control lock is performe for severl prtitions respectively, n test control lock is emee in the circuit to control the test proceure. 3. CHALLENGES OF DELAY TESTING There re two types of ely fults in synchronous circuits epening on the two ifferent consequences of the fult. The first type of ely fults only slows own the performnce of the circuit without cusing ny logic error. This is common when the component ffecte y the fult is ely-insensitive. If we only consier ely fults moele t gte output which increse the ely, ely fults in the control prt of hnshke circuit fll into this ctegory. Despite not cusing logic error, we my still wnt to test for this type of ely fults, since the circuit shoul not e expecte to e unresonly slow. The secon type of ely fults cuses n synchronous circuit to mlfunction n prouce logic errors, when the ely fults result in violtion of inherent timing constrints tht nee to e stisfie for the circuit to operte correctly. Such timing constrints exist in lmost ll prcticl synchronous circuits, since the clss of ely-insensitive circuits uilt with sic gtes is quite limite [6]. For instnce, the t pth in hnshke circuit usully nees to follow unle t, setup, n hol time constrints. Oviously, the secon type of ely fults is necessry to test for, n trgete ely fults in the t pth of hnshke circuit fll into this ctegory. Similr to synchronous circuits, t-spee ely-test methos re necessry to cpture the fult effect in synchronous circuits. If the ely fult is in the control prt of the hnshke circuit n it only egres the performnce ut oes not cuse ny logic error, the fult effect cn e cpture y pplying the test clock ccoring to pre-specifie cceptle performnce, just like in synchronous circuits. However, if the ely fult is in the t pth n violtes some timing constrint, such s the unle t constrint, hence cuses the circuit to fil uring norml opertion, the fult effect is more ifficult to cpture, since the spee of n synchronous hnshke circuit is inherent to the circuit n it is usully ifficult to know the exct ely of certin logic pth. Hence, it is lmost impossile to clock the circuit uring test in such wy tht the ely mismtch cn e ientifie. A possile solution to the ove prolem is to switch the circuit from test moe to norml opertion moe immeitely fter the test ptterns re pplie n the fult is ctivte, so tht the fult effect my e cpture in time. However, there re severl ifficulties in performing t-spee test for synchronous hnshke circuits y switching etween test moe n norml opertion moe. First, the test ptterns shoul e generte crefully to mke sure tht they will not cuse ny 94
hzrs or rces when the circuit is switche to norml opertion moe. Secon, the switching mechnism etween test moe n opertion moe shoul e crefully esigne so tht it neither impcts the timing of norml opertion, nor cuses ny hzrs or rces. To chieve this, creful physicl esign my e necessry to mke sure tht test control signls follow certin timing constrints, n roust switching metho is esirle to simplify or even eliminte these timing constrints. In ition, the test ptterns for t-spee ely test nee to mke sure tht the eterministic fult effect is cpture y scn ltches or flip-flops, or oserve on the primry outputs when the circuit settles in stle stte. As we know, unlike synchronous circuit, n synchronous circuit hs no clock signl to control the feeck pths, hence once it is switche to norml synchronous opertion moe, it my perform sequence of opertions n it is impossile, in generl, to single-step the circuit. The test ptterns must gurntee not only tht the eterministic fult effect is cpture correctly, ut lso tht the fult effect is not overwritten n oes not ispper uring the susequent opertions. This complictes the fult simultion n utomtic test pttern genertion processes significntly. Moreover, the violtion of timing constrint my cuse logic errors on multiple its of the t pth, hence the fult effect my not e unique n the finl response of the fulty circuit is ifficult to erive if the circuit progresses through sequence of opertions. 4. PROPOSED METHODS Since there re two cses of ely fults in hnshke circuits, s escrie in the previous section, we propose two methos to test for ech of them, respectively. First we present the metho to test for ely fults tht only egre the performnce. Then, we focus on testing for ely fults tht cuse the circuit to mlfunction. The propose methos re uilt upon the multiplexer-se full scn test metho in [3] with miniml itionl hrwre. 4. Test for Performnce Degrtion As iscusse in Section 3, the trgete ely fults in the control lock of hnshke circuit o not cuse ny logic error; therefore, they re teste for egring the performnce of the circuit. The propose test metho for ely fults in the control lock mkes use of the multiplexer-se full-scn metho [3] for stuckt fults in hnshke circuits. After scn insertion, synchronous hnshke circuits cn e teste similrly to synchronous circuits. Since scn cells connecte in series cnnot cpture the circuit response t the sme time, the control lock is prtitione into severl prts for test genertion, n fults in ifferent prts re teste ccoringly. For ech prt, the input netlist for ATPG is synchronous circuit generte through scn insertion, remoelling of synchronous cells, n itionl moifictions. Hence, test ptterns for not only stuck-t fults ut lso ely fults, such s trnsition fults or pth ely fults, cn e generte using commercil EDA tools. The propose test metho only supports the scn shifting moe, since the functionl justifiction moe cnnot e irectly pplie to the control lock. In the scn shifting moe, the stte trnsition from the first test vector to the secon vector is initite in the lst scn lo cycle, n the trget fult is sensitize. Then, the circuit response is cpture t reference clock cycle time which is erive ccoring to pre-specifie cceptle performnce of the circuit, n then scnne out n compre to the correct response. This proceure is similr to tht of ely test in synchronous circuits, except tht reference clock is use rther thn n t-spee clock. si C se c se s z se clk Figure 3: A Revise Mux Bse Scn C-Element 4.2 Test for Timing Constrints Dely fults in the t pth of hnshke circuits my increse the computtion time, which not only my reuce the performnce of the t pth, ut, more importntly, my lso violte the unle t constrint n cuse the circuit to mlfunction. Therefore, these ely fults re more criticl to test for. However, these ely fults cnnot e hnle in the sme wy s in synchronous circuits. First, test ptterns cnnot e pplie y simply shifting through the scn chin, since the scn ltch/flip-flop my e shre with the control lock. A two-step test ppliction proceure is usully necessry to set the stte of the control lock n then sensitize n etect the fult in the t pth. Secon, the circuit response is ifficult to e cpture y pplying n tspee clock. As result, the propose metho cptures the circuit response y switching the circuit to synchronous opertion moe rther thn using the test clock. Aitionl hrwre support is necessry for the two-step test ppliction proceure. For ech multiplexer-se scn cell in the control lock, multiplexer (shown in she lines) is inserte, s illustrte in Figure 3, where the scn ltch is shre y the control lock n the t pth lock. As result, there re two scn pths controlle y the itionl control signl se s. The originl scn pth is selecte when se s is set to low, while the multiplexer in the control lock is ypsse when it is set to high. Although the inserte multiplexers introuce minor hrwre overhe, they o not cuse ny performnce overhe since they re only on the scn pth. The propose timing of test ppliction is the following. In the first step, when control signl se s is set to while ll other se signls re set to, test vector is shifte into the scn chin to set the stte of the control lock. Then, ll se signls for ll prtitions of the control lock re set to to isolte the control lock from the scn chin. After tht, in the secon step, se s is set to, n the test vectors generte for the t pth re shifte in through the lterntive scn pth. At the en of this step, the lst scn shift opertion initites the lunch phse n sensitizes the trget ely fult. When the lst shift opertion is complete, the circuit is set to synchronous opertion moe uring which the circuit response is cpture. This is chieve when the ltches or flip-flops ehin the fult re enle, or when the stte of the control circuit chnges ccoring to the conition signls from the t pth. After it stilizes, the circuit is set ck to test moe. If the fult effect is not lrey cpture y the scn ltches/flip-flops or propgte to the primry outputs (i.e. reflecte in the stte of the control lock), n itionl test clock is pplie to cpture the fult effect y the cor- L q so z 2 95
i e G... Figure 4: A Controlle Dely Chin Control o c Hol Figure 5: DFT of n Itertion responing ltches/flip-flops. Then, the circuit is set to scn shift moe n the circuit response is scnne out n compre to the correct response to check whether the fult exists. When the stte of the control lock is set n isolte from the scn chin uring the first step of the test ppliction proceure, mechnism is necessry to preserve this stte from ny utonomous chnges, which will hppen if the stte is not stle. Since the timing constrints uner test re, in fct, ely mtchings etween the t pths n the ely chins, the stte tht the control lock is set to uring the test is the one necessry right efore the ely chin is exercise. Thus it cn e hel y simply mking the ely chin controllle. As illustrte in Figure 4, n AND gte (shown in she lines) is inserte t the eginning of ech ely chin, n signl e is use to control the ely chin. When e is low, the ely chin is isle n no rising event cn propgte through it, while when e is set to high, the ely chin works s norml. During the first step of test ppliction, e is set to to preserve the stte of the control lock. Then, when the circuit is switche ck to norml synchronous opertion moe, it is set to to enle the control lock to operte normlly. Since the inserte control gte cn e incorporte into the ely chin, there is nerly no hrwre n no performnce overhe ue to its introuction. The generte test ptterns for the ove test metho nee to e le not only to sensitize the fult, ut lso to cpture the eterministic fult effect. The prt of the test pttern pplie to the t pth to exercise the fult cn e generte using ATPG tools for synchronous circuits, since the propose metho exercises the fult in wy similr to testing synchronous circuit. The prt of the test pttern pplie to the control lock in the first step nees to mke sure tht fult effect is correctly cpture when the circuit is switche ck to norml opertion moe. To reuce the test genertion compliction ue to the utonomous ehvior when the circuit is switche to synchronous opertion moe, which ws iscusse in the previous section, we propose DFT strtegy which constrins the utonomous ehvior of the circuit uring test. Hol elements [, 5] re inserte etween the hnshke components when necessry, s illustrte in Figure 5 for exmple, to mke sure tht uring test i) the ltches/flip-flops following the fult re clocke only once to cpture n mintin the immeite circuit response, or ii) the wrong stte its in the control circuit re preserve until the circuit stilizes. Since ech hol component is implemente s single AND gte, the hrwre overhe is negligile. c' S o Bse on the propose DFT strtegy, the test genertion for violtion of timing constrints is gretly simplifie. The proceure of test genertion tkes plces in two steps. First, for ny trget ely fult in the t pth, ny test genertion tool for synchronous circuits my e use to generte the prt of test ptterns for the t pth lock se on the remoele input netlist. The loction where the fult effect propgtes to is mrke. Secon, functionl test ptterns re foun se on high-level simultion, in orer to exercise the t pth uner test. If the fult effect loction mrke in the previous step is not flip-flop/ltch in the t pth, which mens tht the fult is in the t pth for gur evlution, the test ptterns re require to exercise the corresponing gure sttement. Otherwise, the test ptterns re require to exercise the expression tht correspons to the t pth uner test, in which cse the mrke flip-flops/ltches nee to e clocke t lest once. Only test pttern tht hols the sme vlue on the prmeter signls when exercising the t pth uner test, s in the previously generte other prt of the pttern, is eligile to e selecte. The snpshot of the trnsient stte of the control lock is kept when the t pth is out to e exercise, n the signl vlue on the loction of ny scn element in the control lock in the snpshot is collecte to form the other prt of the test pttern. Through this process, we otin the two prts of the test ptterns tht re pplie uring ech of the two steps of the test ppliction proceure, respectively. The test ptterns generte through the ove two steps re vli se on the following oservtions. First, lthough the test ptterns etermining the conitionl signls re generte in the first step without consiering the ehvior of the control lock, they will not cuse unesire ehvior of the control lock. If the fult uner test is in the t pth for gur evlution, its effect propgtes through the control signls n les the control lock into n erroneous stte, which is then cpture to oserve the fult. Otherwise, if the fult is in the t pth for t computtion, the control lock must e set to the pproprite stte efore computtion expression in the corresponing Hste progrm to excite n cpture the fult effect. Note tht this stte must e etween gur evlutions, such s in the execution of the sttement S in the o sttement illustrte in Figure 5. At this time, the evlution of ny preceing gur hs een complete, its result hs een cpture y the control lock, n the control signls re not vli ny more. Hence, ny chnge on the control signl oes not influence the ehvior of the control lock. Secon, the test ptterns tht re pplie to the control lock to etermine the vlues of the prmeter signls will not conflict with the test ptterns for the t pth lock, since only consistent pirs re selecte uring the test genertion. 5. EXPERIMENTAL RESULTS The propose ely test methos re implemente se on the esign tool set for hnshke circuits from Hnshke Solutions []. First, the netlist generte fter scn insertion y htscn n its synchronous moel for ATPG tools re preprocesse such tht they re consistent with the revise scn metho. Aitionl test hrwre, such s controlle ely chins n hol components re lso inserte for testing for timing constrint violtions. Then, the timing constrints in the circuit re ientifie n list of them is generte using htpost. After tht, the ely fult moel (trnsition fults or pth ely fults) is chosen, n the fult-list is generte. For ech fult in this list, the type of fult (i.e. cusing performnce egrtion or cusing timing constrint violtion) is etermine The uthors woul like to thnk Hnshke Solutions for proviing their esign tool-set s prt of collortion uner the DARPA CLASS progrm. 96
Fults in control lock Fults in tpth lock Circuit No. of No. of Are Hrwre No. of fults Fults No. of fults Fults Totl fult Nme Inputs Outputs Overhe (Untestle) Detecte (Untestle) Detecte Coverge convto8 8 48 24 524() 464 52() 36 88.76% conv3to8 56 33 878() 782 94() 72 88.99% fifo8 5 9 66 () 99 296() 83.89% gc 23 39 25 286() 83 93(2) 859 85.83% es-roun 27 23 327 24 258() 88 472(4) 863 85.38% es 27 24 5456 252 4683() 452 69552(784) 3993 86.79% Tle : Results of ATPG for Trnsition Dely Fults ccoring to its loction. Then, for ech fult tht egres the performnce, the test ptterns re generte n pplie through the propose metho in Section 4.. For ech timing constrint in the list, the functionl test vectors tht exercise the timing constrint uner test re foun through high-level simultion-se serch, n the prt of test ptterns tht is pplie on the control lock is otine from the snpshot of the netlist simultion of the circuit. Then, for ech fult tht violtes liste timing constrint, the prt of the test ptterns tht is pplie on the t pth is generte through ATPG tools. After tht, the two prts of the test ptterns re pplie to the circuit uring the two steps of the test ppliction process, respectively, s iscusse in Section 4.2. Lstly, for oth types of fults, the generte test ptterns re vlite through simultion. We experimente with the propose methos on set of exmple hnshke circuits synthesize using the esign tool flow from Hnshke Solutions. Trnsition ely fults in oth the control n t pth locks in ech circuit re teste y the propose metho, which employs TetrMx R to perform prt of the test genertion tsk. The results re reporte in Tle. The nme of ech circuit is liste in the first column in Tle, n the numer of inputs, the numer of outputs, n the circuit re (in 2-input NAND-gte equivlent) for ech circuit re liste in the secon, thir, n fourth columns, respectively. Note tht circuit es is fully pipeline DES encoer/ecoer, while es-roun only performs one roun of DES encoing/ecoing opertion. The re of DFT hrwre overhe of the propose metho for ech circuit is shown in the fifth column, inicting tht the hrwre overhe is negligile, especilly for lrge circuits. The totl numer of trnsition fults n the numer of etecte fults in the control lock of ech circuit re liste in the sixth n seventh columns respectively, with the numer in the prentheses inicting the numer of untestle fults reporte y TetrMx R. The sme numers re liste for the t pth lock of ech circuit in the eighth n ninth columns. Finlly, the totl fult coverge for ech circuit is given in the tenth column. For the circuits tht we experimente with, fult coverge of over 85% is chieve y the propose methos. 6. CONCLUSION Two types of ely fults tht either egre the circuit performnce or cuse logic errors re istinguishe in synchronous hnshke circuits. In orer to ress the ely test chllenges rising from the utonomous ehvior of synchronous circuits, test methos n DFT techniques tht simplify the complexity of test genertion hve een evelope for oth of these types of ely fults. The efficiency of the propose test methos hs een emonstrte through experimentl results on severl hnshke circuit exmples. 7. REFERENCES [] Hnshke solutions. http://www.hnshkesolutions.com. [2] S. Bnerjee, S. T. Chkrhr, n R. K. Roy. Synchronous test genertion moel for synchronous circuits. In Proc. of the 9th Interntionl Conference on VLSI Design, pges 78 85, 996. [3] G. Gill, A. Agiwl, M. Singh, F. Shi, n Y. Mkris. Low overhe testing of ely fults in high-spee synchronous pipelines. In Proc. Interntionl Symposium on Avnce Reserch in Asynchronous Circuits n Systems, pges 46 56, 26. [4] P. J. Hzewinus. Testing ely insensitive circuits. Ph.D. Thesis, Deprtment of Computer Science, Cliforni Institute of Technology, 992. [5] M. Kishinevsky, A. Konrytev, L. Lvgno, A. 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