Chapter 4 Data Acquisition & Computer Control Now that we have some tools to look at random data we need to understand the fundamental methods employed to acquire data and control experiments. The personal computer has revolutionized data acquisition and experimental control over the last two decades. It is now possible to run complex experiments and acquire data in real time to hard disks at very rapid rates all from a laptop computer! The fundamental language of computers is digital so we begin with converting the analog world to the digital world. 4.1 Analog to Digital Conversion (ADC) Many of the signals we are interested in are inherently analog. To be able to work with them on a computer we will need to acquire the signal in digital form. This task is performed with an analog to digital converter (ADC). An ADC is a device which takes as an input an analog signal and returns as an output a digital sequence corresponding 1
2 to the analog signal. If we assume a binary digitization we can express this ability as COUNT = 2 n V in V ref (4.1) where V in is the signal being digitized, V ref is the reference voltage - the maximum voltage that can be uniquely digitized, 2 n is the number of unique digital sequences available, and COUNT is the returned digital sequence. Note we have assumed that the minimum voltage to be digitized is V in = 0. This is known as a unipolar ADC. If we are working with a signal that can be positive or negative we need to use half of the available COUNTs (2 n 1 ) to handle the negative signal values and half to handle the positive signal values. This is known as bipolar ADC. Assuming an infinite number of binary values we can express the signal being digitized as ( b1 V in = V ref 2 + b 2 1 2 + + b n 2 2 + b ) n+1 n 2 + n+1 (4.2) Of course we do not have an infinite number of binary values (or bits) hence we necessarily truncate our digitization at the n th bit ( b1 V in V ref 2 + b 2 1 2 + + b ) n 2 2 n where the first neglected term, b n+1, represents the conversion, or quantization error. (4.3) Thus the ADC operation replaces V in by a discrete voltage which is a multiple of V ref /2 n such that V in COUNT V ref 2 n 1 2 V ref 2 n (4.4) The quantum value V ref /2 n is known as the least significant bit (LSB) value and clearly is the resolution of the ADC process. The figures on the next page gives a graphical sense for ADC conversion. A logical question is how frequently can an ADC be performed, e.g., what is the effective throughput of the ADC? Two typically reported values are the conversion time and the sample rate. The conversion time is the time it takes to convert V in to a digital value at a specified accuracy and resolution. The value is typically reported for the time it takes to convert the maximum voltage difference and depending on the type of ADC the
Data Acquisition & Computer Control 3 5 4 V out *2 n /V ref or COUNT 3 2 1 0 0 1 2 3 4 5 V in *2 n /V ref Error*2 n /V ref 0.5 0 0.5 0 1 2 3 4 5 V in *2 n /V ref conversion time may be a function of the variation in V in. The conversion time generally does not include any dead time (for instance time to reset the ADC to a zero digital value and any other overhead). The sample rate is the maximum number of voltage samples that can be digitized per second. This may not be equal to the inverse of the conversion time as the sample rate does include all overhead plus the conversion time. In todays market place it is standard to find ADCs from 8-bit to greater than 24-bit (A few very pricey 30-bit systems exist) and with sample rates from 10kHz to greater than 1Ghz. The standard inexpensive data acquisition cards for PCs will generally have 12-bit ADCs that operate in the 100khz range but for not much more cost 16-bit or greater than 1Mhz can be had.
4 4.1.1 Error Sources in ADC The previous figure is the ideal response, or transfer function, of and ADC. In reality no ADC will always perform in this manner and we expect some deviation from the ideal. A challenge when comparing the specification sheets for various ADC devices is the relative lack of standard parameters to characterize the digitization error. We will define some general error types that may be known by various names. Differential linearity error (DLE) occurs when the sawtooth pattern seen in the quantization error figure becomes irregular. This means that the voltage at which the ADC transitions from one quanta to the next is not constant but varies by some small amount. Clearly for the device to behave monotonically (meaning that a larger V in is always given a binary value greater than or equal to a smaller V in ) the DLE must be less than or equal to 1 LSB. Offset error is the difference between the actual V in that will trigger a transition from the COUNT=0 state to the COUNT = 1 LSB state from the theoretical value which is 1 2 (V ref/2 n ). The voltage difference is known as the offset voltage. Gain error is the amount by which the slope of the straight line through the transfer function (shown in the previous figure) differs from 1. Aperture error is an error that results from exactly when V in is sampled. Imagine a sine wave being sampled. If the exact time of sampling differs slightly from the ideal time then the sine wave s value will have changed and the resultant digital value will have an error - on top of any errors as already described. A way of characterizing this error is to consider the sampling of a high speed sine wave that varies from V in = 0 to V in = V ref. The rate at which the signal is changing is known as the slew rate. Thus we can write [ Vref slew rate = dv dt = d ] dt 2 sin(2πft) (4.5) = πfv ref cos(2πft) (4.6)
Data Acquisition & Computer Control 5 The worst case occurs where cos = 1. If we set dv = 1 2 LSB (V ref/2 n+1 ) we can determine the aperture error as aperture error = dt max = 1 πf2 n+1 (4.7) 4.1.2 ADC Types Not surprisingly there are two common ADC types, serial and parallel. As the names imply in serial ADC the digital representation of V in is determined in a serial fashion 1 bit at a time or slower. In a parallel ADC each bit is determined simultaneously and the highest speed ADC devices are parallel. Serial ADC The basic algorithm in a serial ADC is that an accurate reference voltage is compared to V in and a single bit is determined. Thus to complete an n bit A/D conversion n cycles through a serial ADC are required. While this inherently requires a relatively large number of iterations through the ADC it does not necessarily mean that serial ADCs are slow. In fact, the serial ADC is the most flexible architecture available to designers of ADC devices. The highest resolution (e.g., most bits) devices are serial devices. While the fastest ADC devices are not serial a serial device with reasonably fast characteristics can be manufactured. There are several variations of the serial ADC including: ramp or integrating ADCs (e.g., single-slope and dual-slope), delta-sigma ADCs, successive approximation ADCs, bitserial pipelined ADCs and algorithmic ADCs. Integrating ADCs tend to be the slowest devices (but potentially the highest resolution). The basic algorithm of an integrator type ADC involves integrating the input voltage for a fixed number of clock cycles - 2 n. The result then leads directly to the use of Eq 4.1 to determine COUNT. Clearly an integrator requires at minimum 2 n clock cycles to perform the ADC and the cost of adding 1-bit is double! The advantage is that very high resolution A/D conversions can be achieved.
6 The most common type of serial ADC device is the successive approximation ADC so let s take a closure look at this architecture. The successive approximation algorithm is as the name implies an approach that in a sequential manner approximates each bit. A pictorial chart of a 3-bit successive approximation ADC is The first approximation is made by comparing V in to V ref /2. If V in > V ref /2 than the most significant bit (MSB) is set to 1, if not the MSB is set to 0. Now the device takes advantage of its acquired knowledge and continues down only the TRUE side of the tree
Data Acquisition & Computer Control 7 - e.g., whichever value the MSB was set too. In the second step V in is compared to either V ref /4 or 3V ref /4, and the appropriate value for MSB-1 is determined. Finally V in is compared to an odd multiple of V ref /8 and MSB-2 is determined. Clearly n comparisons are required for and n bit conversion. The key to accuracy of a successive approximation ADC device is the ability to generate accurate comparison values (e.g., the appropriate fractions of V ref ). This relies on an digital to analog conversion DAC (which we will discuss shortly). If the DAC is linear then the result should be good. If the DAC is not linear than the possibility of embarking down the wrong branch of the search ladder is very real and a poor result will be achieved. Parallel or Flash ADC When speed of the A/D conversion processes is important a parallel ADC (known commonly as a flash ADC) is the ADC of choice. The flash architecture basically relies on brute force to test all the possible quantization levels simultaneously. To test all of the possible quantization levels 2 n 1 comparisons must be made. This is achieved generally be voltage division of V ref. Voltage division requires an appropriate resistance to scale the reference voltage and hence 2 n 1 resistors are required. Thus for even moderate resolution devices, say 12-bits, a lot of electronics is required. Note that the circuitry requirements double for each additional bit. The upper limiting factor on resolution of flash type ADCs is their need to dissipate heat. Eventually the thermal characteristics start to create an environment the renders the determination of further bits futile. 4.1.3 Bit Codes We have talked mostly about unipolar digital representations of numbers and we have implicitly assumed that the digital representation is an unsigned binary number that has the MSB on the left-hand-side and the LSB on the right-hand-side. How a number is represented is known as its bit code. The first point to be aware of is that all digital devices do not code a number in the same fashion. Many of you
8 may have encountered this variation if you have ever tried to move binary data from an older Apple computer (in the motorola processor days) to an IBM compatible computer. There are two standard forms in which a sequence of bytes will be stored: big-endian and little-endian. Big-endian is an order in which the big end (most significant value in the sequence) is stored first. Little-endian is an order in which the little end (least significant value in the sequence) is stored first. Note that each individual byte is still stored in the same manner - MSB on the left LSB on the right. Just the byte order is reversed. As an example in a 2 byte integer (16-bit integer). The number 1024 in binary is written 00000010 00000000. This is the way we think of the number normally (most significant information on the left) and is known as big-endian. The little-endian representation of 1024 would be 00000000 00000010 which is the number 2 in big-endian! Thus it is imperative to know which endian was used in writing binary data when moving the data between computers. The Intel world is little-endian (including the current Apple computers) while the Motorola world (and many RISC-processor based workstations) is big-endian. There is a third class - bi-endian, that means hardware can function in both big-endian and little-endian modes which has advantages for networking in particular. So what is your iphone? ios in genial and hence your iphone and ipad are little-endian while your laptop is big-endian, which could matter if you are looking at data acquired from an iphone on your laptop! A second issue is how are negative (bipolar) numbers coded? There are several variants but the standard method is known as the two s compliment code. Clearly only 2 n 1 counts are available in either the positive or negative direction. In two s compliment code a positive number is represented as a binary number as described above (either little-endian or big-endian). A negative number is expressed by taking the compliment (opposite) of each bit corresponding to the positive of the number and then adding 1 to the LSB (an actual addition so other bits may be affected). Consider a 4-bit system. The number 3 is represented as 0011. -3 is represented as 1101 which in a unipolar code would be 13. Let s look at a table of all possible values on a 4-bit system.
Data Acquisition & Computer Control 9 Number two s compliment unipolar value 7 0111 7 6 0110 6 5 0101 5 4 0100 4 3 0011 3 2 0010 2 1 0001 1 0 0000 0-1 1111 15-2 1110 14-3 1101 13-4 1100 12-5 1011 11-6 1010 10-7 1001 9-8 1000 8 Looking at the unipolar value of the code another way of thinking about two s compliment coding is that the binary numbers wrap around at 2 n 1. Thus for COUNT < 2 n 1 the two s compliment is just the same as a unipolar coding but for COUNT > 2 n 1 the two s compliment value is found as COUNT 2 n. Check it. In our previous example the two s compliment value was -3 13 2 n = 3. 4.2 Digital-to-Analog Conversion DAC A digital to analog converter (DAC) is a device that takes a digital value and converts it to an analog voltage. Similar to an ADC we can define the transfer function of an n-bit
10 DAC as V out = COUNT V ref 2 n (4.8) where V out is the voltage output for a digital value of COUNT. Clearly a DAC can only output discrete values where for a unipolar output the resolution is 1/2 n and for a bipolar output the resolution is 1/2 n 1. An example of a sine wave generate by a DAC is shown below. DACs are characterized in a similar manner to ADCs - gain and offset error, and differential linearity error. The analogies are obvious and we will not review them here.