DATASHEET CA1 High Frequency NPN Transistor Array The CA1 consists of five general purpose silicon NPN transistors on a common monolithic substrate. Each of the completely isolated transistors exhibits low 1/f noise and a value of f T in excess of 1GHz, making the CA1 useful from DC to MHz. Access is provided to each of the terminals for the individual transistors and a separate substrate connection has been provided for maximum application flexibility. The monolithic construction of the CA1 provides close electrical and thermal matching of the five transistors. Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # CA1M CA1 - to 1 1 Ld SOIC M1.1 CA1MZ (Note) CA1MZ - to 1 1 Ld SOIC (Pb-free) M1.1 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 1% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. Features FN Rev.. Jun, Gain Bandwidth Product (f T )................. >1GHz Power Gain.................. db (Typ) at 1MHz Noise Figure..................dB (Typ) at 1MHz Five Independent Transistors on a Common Substrate Pb-Free Plus Anneal Available (RoHS Compliant) Applications VHF Amplifiers Multifunction Combinations - RF/Mixer/Oscillator Sense Amplifiers Synchronous Detectors VHF Mixers IF Converter IF Amplifiers Synthesizers Cascade Amplifiers Pinout CA1 (SOIC) TOP VIEW 1 Q 1 1 Q 1 1 SUBSTRATE Q 1 1 11 Q Q 1 9 FN Rev.. Page 1 of 9 Jun,
Absolute Maximum Ratings The following ratings apply for each transistor in the device Collector-to-Emitter Voltage, V CEO.....................1V Collector-to-Base Voltage, V CBO.......................V Collector-to-Substrate Voltage, V CIO (Note 1).............V Collector Current, I C............................... ma Operating Conditions Temperature Range..........................- C to 1 C Thermal Information Thermal Resistance (Typical, Note ) JA ( C/W) SOIC Package............................. 1 Maximum Power Dissipation, P D (Any One Transistor).....mW Maximum Junction Temperature (Die)................... 1 C Maximum Junction Temperature (Plastic Packages)........ 1 C Maximum Storage Temperature Range.......... - C to 1 C Maximum Lead Temperature (Soldering 1s)............. C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor of the CA1 is isolated from the substrate by an integral diode. The substrate (Terminal ) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS (For Each Transistor) Collector-to-Base Breakdown Voltage I C = 1 A, I E = - V Collector-to-Emitter Breakdown Voltage I C = 1mA, I B = 1 - V Collector-to-Substrate Breakdown-Voltage I C1 = 1 A, I B =, I E = - V Emitter-to-Base Breakdown Voltage (Note ) I E = 1 A, I C =. - V Collector-Cutoff-Current V CE = 1V I B = - -. A Collector-Cutoff-Current V CB = 1V, I E = - - na DC Forward-Current Transfer Ratio I C = ma - I C = 1mA 9 - I C =.1mA - Base-to-Emitter Voltage I C = ma.1.1.91 V I C = 1mA... V I C =.1mA... V Collector-to-Emitter Saturation Voltage I C = 1mA, I B = 1mA -.. V Magnitude of Difference in V BE Q 1 and Q Matched -. mv Magnitude of Difference in I B, I C = 1mA -. A DYNAMIC CHARACTERISTICS Noise Figure f = 1kHz, R S =, I C = 1mA -. - db Gain-Bandwidth Product, I C = ma - 1.1 - GHz Collector-to-Base Capacitance V CB = V, f = 1MHz - See Fig. - Collector-to-Substrate Capacitance V CI = V, f = 1MHz - - Emitter-to-Base Capacitance V BE = V, f = 1MHz - - Voltage Gain, f = 1MHz, R L = 1k, I C = 1mA - - db Power Gain Cascode Configuration - db Noise Figure f = 1MHz, V+ = 1V, I C = 1mA -. - db FN Rev.. Page of 9 Jun,
Electrical Specifications Input Resistance Common-Emitter Configuration - - Output Resistance, I C = 1mA, f = MHz -. - k Input Capacitance -. - Output Capacitance - - Magnitude of Forward Transadmittance - - ms NOTE:. When used as a zener for reference voltage, the device must not be subjected to more than.1mj of energy from any possible capacitance or electrostatic discharge in order to prevent degradation of the junction. Maximum operating zener current should be less than 1mA. Test Circuits PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 1k V+ BIAS-CURRENT ADJ R L.1 F 1 F 1 Q V O 1 F.1 F Q.1 F V I GEN FIGURE 1. VOLTAGE-GAIN TEST CIRCUIT USING CURRENT-MIRROR BIASING FOR Q 1. - V O SHIELD 1 C (NOTE ). k. H V I 1. H 1. C 1 (NOTE ) OHMITE Z1 1 Q 1 Q Q k 1 1 1 1% 1 TEST POINT NOTES:. This circuit was chosen because it conveniently represents a close approximation in performance to a properly unilateralized single transistor of this type. The +1V use of Q in a current-mirror configuration facilitates simplified biasing. The use of the cascode circuit in no way implies that the transistors cannot be used individually.. E.F. Johnson number 1-1-1 or equivalent. FIGURE. 1MHz POWER-GAIN AND NOISE-FIGURE TEST CIRCUIT FN Rev.. Page of 9 Jun,
GENERAL RADIO 11-P1 1MHz GENERATOR ATTN 1MHz TEST SET BOONTON 91C RF VOLTMETER 1V DC POWER SUPPLY FIGURE A. POWER GAIN SET-UP VHF NOISE SOURCE 1MHz 1MHz NOISE FIGURE METER HEWLETT PACKARD HPA TEST SET POST AMPLIFIER HEWLETT PACKARD HPA 1V DC POWER SUPPLY 1V DC POWER SUPPLY FIGURE B. NOISE FIGURE SET-UP FIGURE. BLOCK DIAGRAMS OF POWER-GAIN AND NOISE-FIGURE TEST SET-UPS Typical Performance Curves R SOURCE = f = 1Hz R SOURCE = 1k f = 1Hz f = 1Hz NOISE FIGURE (db) 1 f = 1kHz f = 1kHz f = 1Hz f = 1kHz NOISE FIGURE (db) 1 f = 1kHz f = 1kHz.1.1 1. FIGURE. NOISE FIGURE vs COLLECTOR CURRENT f = 1kHz.1.1 1. FIGURE. NOISE FIGURE vs COLLECTOR CURRENT FN Rev.. Page of 9 Jun,
Typical Performance Curves (Continued) GAIN-BANDWIDTH PRODUCT (GHz) 1. 1.1 1..9. 1 9 1 BASE-TO-EMITTER VOLTAGE (V) 1..9......1 T A = - C T A = 1 C 1 1 FIGURE. GAIN-BANDWIDTH PRODUCT vs COLLECTOR CURRENT FIGURE. BASE-TO-EMITTER VOLTAGE vs COLLECTOR CURRENT CAPACITANCE ().. 1. 1. 1. 1.... f = 1MHz C EB C CI C CB 1 9 1 BIAS VOLTAGE (V) FIGURE A. CAPACITANCE vs BIAS VOLTAGE FOR Q TRAN- SISTOR BIAS (V) CAPACITANCE () C CB C CE C EB C CI PKG TOTAL PKG TOTAL PKG TOTAL PKG TOTAL - V - V - V - V Q 1..19.9.1..1. 1. Q.1.1...1.. 1. Q...1....1 1. Q..19....1. 1. Q.1.1.9.11.1..9 1. FIGURE B. TYPICAL CAPACITANCE VALUES AT f = 1MHz. THREE TERMINAL MEASUREMENT. GUARD ALL TERMINALS EXCEPT THOSE UNDER TEST. FN Rev.. Page of 9 Jun,
Typical Performance Curves (Continued) VOLTAGE GAIN (db) 1 1 -,, R L = 1 FOR TEST CIRCUIT SEE FIGURE 19 I C = 1mA I C =.ma I C = ma I C =.ma -1 1M 1M 1M 1G VOLTAGE GAIN (db) 1 1 I C = 1mA I C =.ma I C =.ma I C = ma -,, R L = 1k -1 FOR TEST CIRCUIT SEE FIGURE 19 1M 1M 1M 1G FIGURE 9. VOLTAGE GAIN vs FREQUENCY FIGURE 1. VOLTAGE GAIN vs FREQUENCY DC FORWARD CURRENT TRANSFER RATIO 1 9.1 1. 1 FIGURE 11. DC FORWARD-CURRENT TRANSFER RATIO (h FE ) vs COLLECTOR CURRENT INPUT CONDUCTANCE (g 11 ) OR SUSCEPTANCE (b 11 ) (ms) 1 1M,, I C = 1mA b 11 g 11 FIGURE 1. INPUT ADMITTANCE (Y 11 ) vs FREQUENCY 1G FN Rev.. Page of 9 Jun,
Typical Performance Curves (Continued) INPUT CONDUCTANCE (g 11 ) OR SUSCEPTANCE (b 11 ) (ms) 9 1 f = MHz g 11 b 11 1 9 1 OUTPUT CONDUCTANCE (g ) (ms) 1. 1. 1.1 1..9........1 1M I C = 1mA g b 1 1G OUTPUT SUSCEPTANCE (b ) (ms) FIGURE 1. INPUT ADMITTANCE (Y 11 ) vs COLLECTOR CURRENT FIGURE 1. OUTPUT ADMITTANCE (Y ) vs FREQUENCY OUTPUT CONDUCTANCE (g ) (ms) f = MHz b... g.......1 1 9 1........1. 1.9 11 1 OUTPUT SUSCEPTANCE (b ) (ms) MAGNITUDE OF FORWARD TRANSADMITTANCE ( Y 1 ) (ms) 1 f = MHz Y 1 1-1 1 9 1 11 1 - - - - PHASE-ANGLE OF FORWARD TRANSADMITTANCE ( 1 ) ( ) FIGURE 1. OUTPUT ADMITTANCE (Y ) vs COLLECTOR CURRENT FIGURE 1. FORWARD TRANSADMITTANCE (Y 1 ) vs COLLECTOR CURRENT FN Rev.. Page of 9 Jun,
Typical Performance Curves (Continued) MAGNITUDE OF FORWARD TRANSADMITTANCE ( Y 1 ) (ms) 1 1M -1 I C = 1mA - - Y 1 1 1M M - - - - - -9-1 1G PHASE-ANGLE OF FORWARD TRANSADMITTANCE ( 1 ) ( ) MAGNITUDE OF REVERSE TRANSADMITTANCE ( Y 1 ) (ms) f = MHz 1 Y 1.1 1 9 1 - -9-1 -11-1 -1-1 -1 11 1 PHASE-ANGLE OF REVERSE TRANSADMITTANCE ( 1 ) ( ) FIGURE 1. FORWARD TRANSADMITTANCE (Y 1 ) vs FREQUENCY FIGURE 1. REVERSE TRANSADMITTANCE (Y 1 ) vs COLLECTOR CURRENT I C = 1mA MAGNITUDE OF REVERSE TRANSADMITTANCE ( Y 1 ) (ms)......1 1M 1 Y 1-9 -9-1 -1-11 -11-1 1G PHASE-ANGLE OF REVERSE TRANSADMITTANCE ( 1 ) ( ) FIGURE 19. REVERSE TRANSADMITTANCE (Y 1 ) vs FREQUENCY FN Rev.. Page of 9 Jun,
Small Outline Plastic Packages (SOIC) N INDEX AREA 1 e D B.(.1) M C A M E -B- -A- -C- SEATING PLANE A B S H.(.1) M B A1.1(.) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y1.M-19.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.1mm (. inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (.1 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate.. N is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured.mm (.1 inch) or greater above the seating plane, shall not exceed a maximum value of.1mm (. inch). 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x C M1.1 (JEDEC MS-1-AC ISSUE C) 1 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A.. 1. 1. - A1..9.1. - B.1...1 9 C..9.19. - D.9.9 9. 1. E.19.1.. e. BSC 1. BSC - H.... - h.99.19.. L.1.. 1. N 1 1 - Rev. 1 / Copyright Intersil Americas LLC 199-. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN Rev.. Page 9 of 9 Jun,