Power Managemen Channel DMX Dimmer Applicaion Noe Absrac AN0 Auhor: Pero Kobluk Associaed Projec: Yes Associaed Par Family: CY8C7 GET FREE SAMPLES HERE Sofware Version: PSoC Designer. Associaed Applicaion Noes: None Basic principles of Channel DMX Dimmer operaion are described in his Applicaion Noe. A DMX dimmer can be used o conrol he brighness of remoe lighing in heaers, discos, and concer halls. The device is conrolled via a DMX inerface. The srucure, device funcion algorihm, inerconnecion circuis, DMX Proocol, and fundamenal design aspecs based on he PSoC device are considered. Inroducion Nowadays compuerconrolled equipmen echniques, consoles, and conrol panels are used o conrol effecs and sage lighing in heares, discos, concer halls, ec. The DMX Dimmer is used o conver he device inpu signal ino an analog represenaion of lamp brighness (power). The DMX Dimmer has he following characerisics (see Table ). Table. Channel DMX Dimmer Characerisics Number of Channels Lamp Power Power Supply AC Synchronizaion Depending on TRIAC Used DC 5V, 00 ma AC 00V, 7 Hz, Auomaic Turning Address Range From o 5 Service Feaures DMX Bus SleepMode Suppor DMX Proocol DMX proocol was esablished by he Unied Saes Insiue for Theare Technology (USITT) in 98. This proocol represens sandard inerface for daa communicaion beween devices ha are used for lighing. In 990, revisions were made and now he proocol is known as USITT DMX5. The DMX proocol uses he RS85 sandard, which defines elecrical inerface, volage, and curren. This sandard suppors receiver and ransmier ground connecion o he cable core screen in order o lower he influence of exernal noise and improve elecrical safey. Bu he values of ransmier and receiver ground line volage can be differen, which causes curren o pass hrough he cable screen. If he value of his curren is oo grea, he DMX cable and he circui can be desroyed. In order o correcly work devices ha use DMX, o conrol he inerface, and also improve usage safey, i is necessary o implemen galvanic isolaion on he DMX receiver devices. The DMX daa sream is passed in he form of a burs ha is repeaed coninually. This daa burs consiss of he synchro preamble ha informs he receiver when i sars. Augus 5, 005 Documen No. 00 Rev. **
This sream conains he values of each channel from o 5, or less (see Figure, Table ). The bi rae in he DMX proocol is 50 kb. So, he duraion of every bi is µs. The number of channels passed is no fixed, bu is limied by he sandard, which is from o 5. If he informaion is given over all 5 channels, hen he maximum frequency ha he informaion is updaed is a,5 Hz. The maximum frequency ha he informaion is ransmied can be 8 Hz, which corresponds o channels. Upon a long signal delay (more han s), he device can ener DMX sleep mode. Figure. Srucure of a DMX5 Signal 7 9 Sar bye Channel Channel 5 5 8 Table. Daa Sream Descripion and Duraion Iem Descripion Duraion Space for Break (Rese) Min. 88 µs Mark Afer Break (MAB) 8 µs s Slo Time µs Mark Time Beween Slos 0 µs s 5 Sar Bi µs Leas Significan Daa Bi µs 7 Mos Significan Daa Bi µs 8 Sop Bi µs Lamp Power Phase Conrol The TRIAC and lamp inerconnecion circui example is shown in Figure. This seup allows he conrol of lamp brighness by varying he delay beween AC line zerocrossing and TRIAC ON evens (see Figure ). When conrol impulses are sen o he TRIAC, i swiches o ON sae. The TRIAC OFF sae is auomaically riggered when he volage falls o zero a he nex zerocrossing even. Noe The dimmer can be used wih varying AC frequencies; herefore, he AC line frequency needs o be measured in order o provide correc dimmer operaion regardless of he acual power supply parameers. 9 Mark Before Break (MBB) 0 µs s Augus 5, 005 Documen No. 00 Rev. **
Figure. TRIAC and Lamp Inerconnecion Circui Example TRIAC CONTROL TRIAC 00 V AC~ LAMP Figure. Timeable of Lamp Power Phase Conrol 00 V AC ~ AC mains zerocrossing Triac conrol Delay Delay Delay Volage in Lamp DMX Dimmer The DMX Dimmer block diagram is shown in Figure. The DMX Receiver receives daa in accordance o he prese address range and ranslaes hem in he TRIAC Conrol Uni. When he value of he volage is zero, he AC Synchronizer (zerocrossing deecor) generaes he lockou pulses ha are used o delay iniializaion of he couners. The TRIAC Conrol Uni has independen couners. When he lockou pulse eners from he AC Synchronizer, he couners sar heir operaion. If he couner reaches he prese brighness compare value, he conrol impulse for he TRIAC ON even is generaed o urn he TRIAC on. Noe The power supply of he AC Synchronizer and lamp mus be he same. Figure. DMX Dimmer Block Diagram DMX AC DMX Receiver Synchronizer from AC Triac Conrol Uni Channel Channel *** Channel 5 Channel Augus 5, 005 Documen No. 00 Rev. **
DMX Dimmer Operaion Figure 5 illusraes he DMX Dimmer circui. Figure 5. DMX Dimmer Circui VCC VCC J (B) R 00k (A) 00 AC DV n8 R 0k R5 00k DF0 D 8A R 5.k R 0k (C) DV 8V (D) C 7u UA V 8 Gnd V LM VCC OUT 7 R7.7k U HL 5 VCC R 70R F00 DMX SLP SW8 SW SW SW SW9 TR TR TR SLP U 8 Vcc 7 P0[7] P0[] P0[5] P0[] 5 P0[] P0[] P0[] P0[0] 5 P[7] P[] 7 P[5] P[] 8 P[] P[] 0 P[] P[0] 9 9 SMP Xres 0 8 P[7] P[] 7 P[5] P[] P[] P[] 5 P[] P[0] Vss SW9 CY8C7_DIP8 SW8 SW7 SW SW5 F00 SW SW SW SW SW7 SW5 SW SW DMX TR5 TR TR TR TR5 TR TR TR TR R9 7R R0 7R R 7R R 7R R 7R R 7R C 0.7u C 0.7u C 0.7u C5 0.7u C 0.7u C7 0.7u 8 7 5 Triacs J J DMX 5 7 5 U VCC 8 DO/RI DO/RI RO RE DE GND DI 75LBC7A R8 k U5 HL 5 R5 70R SW S SW S SW S0 VCC VCC VCC J DC C8 0u C9 0.u C0 0.u C 0.u C 0.u U Vs Vou SYNCin SYNCou 0Vin 0Vou DCP00505BP 8 5 C 0u C 0.u U7 LP9505.0 IN OUT GND C5 0u C 0.u C7 0.u In order o isolae he high volage secion from oher pars of he circui, i is necessary o do galvanic isolaion using he opoisolaor, U HL. Zerocrossing deecion is implemened using U, a lowcos LM comparaor. A Poin A (afer he diode bridge), he volage is in he form of a fullyrecified sinusoid (Figure ). Figure. Clocking Uni Volages of Poins A, B, C Relaive o Poin D Poin A Poin B Poin C 8.7 V 8 V Comparaor Ou AC Synchronize Ou Augus 5, 005 Documen No. 00 Rev. **
The zener diode DV and capacior C forms he 8V DC level relaive o poin «D». Volage is scaled down o.v by he volage divider formed from R and R. The.V is used as a reference for negaive comparaor inpu. In poin «В», volage is in he form of a fullyrecified sinusoid. Volage is supplied on posiive inpu of he comparaor by he volage divider across R and R 5. The comparaor deecs zerocrossing evens and ransmis hem via he opocoupler, U. The complexiy of zerocrossing deecion is compensaed for by sable and reliable operaion, noiseimmuniy, and esing in many indusrial applicaions, including auomaed welding machines. The DMX receiver operaes from PSoC s RX8 receiver and Couner8 (Figure 7). The signal is supplied for he RX8 receiver and Couner8 hrough he RS85 differenial receiver, U 75LBC7A, and he opocoupler, U 5. In order o provide galvanic isolaed power supply for he U receiver, he U DCP00505BP DC/DC converer and U 7 lowdrop LP9505.0 DC regulaor are used. The TRIAC conrol uni is buil using PWM generaors and he oupu signal is differeniaed using a firs order RC high pass filer. Figure 7. PSoC Inernal User Module Configuraion Augus 5, 005 Documen No. 00 Rev. ** 5
I is imporan o provide good hea sink for he TRIACS, which are used o conrol he power lamp. This is why hey are placed ouside he PCB. Figure 8 shows wo differen TRIAC circuis (depending on lamp power, low or high). The TRIAC, wih a builin opocoupler, is used for he galvanic isolaion conrol circui. This isolaes he circui from he power circuis. Diode D b provides differenial nework capacior discharge. Figure 8. TRIAC Inerconnecion Circui (a) Low Lamp Power, (b) High Lamp Power TRIAC DRIVER CONTROL R Db ~AC LINE K S0T0 (a) TRIAC DRIVER POWER TRIAC CONTROL R Db R CS0io ~AC LINE K MOT0 (b) SW, SW, and SW are used o se he address of he device and enable DMX bus sleep mode. The maximum number of channels specified by he DMX5 Proocol is 5. The saring channel address is se by DIP swiches, described as follows: SW/ is he address MSB, bi 8, SW/ 7, SW/, SW/ 5, SW/, SW/, SW/, SW/, SW/ is he address LSB, bi 0. SW/ and SW/ are reserved. The DMX receiver receives he signal on he RX8. The Couner8 is used o deec he break signal, he duraion of which is a minimum 88 µs. The DMX line is sen on he RX8 receiver and Couner8 simulaneously (see Figure 7). The break signal is deeced by riggering a couner inerrup. The GPIO inerrup is used o rese Couner8. The GPIO inerrup is acivaed from he same DMX line. RX8 chooses he daa byes from he DMX bus, and incremens he sofware channel couner. CMP comparaor is used o generae zerocrossing inerrups, because he GPIO inerrup resource is already aken and PSoC has no dedicaed flag regisers o deermine which GPIO pin riggered he inerrup. Program Operaion The daa are received in realime from he DMX line and TRIAC conrol uni. Tha is why i is very imporan o separae hese funcions. If one of hese funcions misses is specified deadline, fauly operaion can occur. SW/ is used o se DMX bus sleep mode. If here is no signal on he DMX line for more han s, (see he DMX Proocol), sleep mode acivaes and all lamps are swiched off. If sleep mode is no enabled, he device coninues o power iself a he lamp s las values of brighness (power). Augus 5, 005 Documen No. 00 Rev. **
Using he sofware PWM o conrol he TRIACS is no an opimal soluion. Program operaion is based on processing shor inerrups. When here is no acive inerrup handling, he device is waiing bu inacive. The duraion of he daa burs, which is received by he RX8, is only µs. Wih he PSoC sysem clock (IMO) of MHz, he daa burs akes 05 cycles. The sum of he inerrup handler execuion imes mus be less han his ime. Five sources of inerrups are used (see Table ). To minimize heir duraion hey are wrien in assembly. Table. Inerrup Sources # Source Type IMO Cycles (Maximum) Couner8 Terminal Coun 5 RX8 Receiver Full 8 GPIO Rising Edge Analog Column Rising Edge 9 5 Sleep Timer Terminal Coun 78 The PSoC iniializaion flowchar is shown in Figure 9. Iniializaion consiss of wo funcions. Firs, AC line frequency calibraion occurs and second, iniializaion of variables and modules occurs. These variables are necessary for device operaion. Iniializaion Figure 9. PSoC Iniializaion Flowchar bcoun = 0 wfrequency = 0 M8C_EnableInMask (INT_MSK0, INT_MSK0_ACOLUMN_); M8C_EnableGIn; CMPPRG Sar (CMPPRG HIGHPOWER); wfrequency == 0 M8C_DisableInMask (INT_MSK0, INT_MSK0_ACOLUMN_) Couner8_WriePeriod(75) CounerCLK = VC CounerENABLE = Row0Inpu VC = VCDivider = CalibraionFrequency (Couner8_bReadCouner()) bpower = 0 bpower = 0 bpower = 0 bpower = 0 bpower5 = 0 bpower = 0 bsl = 0 M8C_EnableInMask (INT_MSK0, INT_MSK0_ACOLUMN_) Couner8_EnableIn() Couner8_Sar() RX8_EnableIn() M8C_EnableInMask (INT_MSK0,INT_MSK0_GPIO) M8C_EnableInMask(INT_MSK 0, INT_MSK0_SLEEP) PWM8 EnableIn() PWM8 EnableIn() PWM8 EnableIn() PWM8 EnableIn() PWM8_5_EnableIn() PWM8 EnableIn() IDLE Loop Augus 5, 005 Documen No. 00 Rev. ** 7
AC line frequency calibraion is carried ou only when he device is urned on and is inended o adjus TRIAC urnon angle seing appropriaely for he uilized line frequency. There are 55 lamp brighness levels. The value of he PWM generaor period is se consan and equal o 5 clock pulses. The VC divider supplies he clock. The duraion of he PWM period mus be equal o exacly ½ of AC line period (Figure 0). Figure 0. Calibraion Procedure AC Line Half Cycles AC Line Couner8 T= CounValue F mains PWM8 Period Afer Calibraion This is done by uning he VC divider during he calibraion procedure. I operaes in he following way: Couner8 sars couning during AC line zerocrossing comparaor inerrups ( half cycles). The coun value is used for VC divider calculaion in he CalibraionFrequency() rouine using he following formulas: Cn Cn Value Clock = f Equaion 5 = f Equaion PWM Clock Cn Cn Value Clock 5 = PWM Clock Equaion For increased measuremen precision, he calibraion procedure inegraes half cycles of he AC line frequency. For correc Couner8 and PWM8 during hese half cycles, he clock frequency is reduced by a facor of by seing VC = insead of he normal value VC=. wfrequency is a flag ha shows ha calibraion has compeed. Once he program sars, his flag is rese and he AnalogColumn inerrups are enabled. The flag rese is done in he maser program by he AnalogColumn inerrup handler. Afer ha, he values of he necessary dividers are se and Couner8 seings are modified for use as a break deecor. A he second par of PSoC iniializaion, he variables and necessary modules for device iniializaion are carried ou. Firs, he variables, which conain he brighness of each lamp, are rese. Nex, he necessary inerrup permission flags are se and wo modules sar: Couner8 and CMP. When he break signal passes over he DMX line, he Couner8 inerrup handler is brough in. The waddresscouner variable is rese and he RX8 is resared in he Couner8 inerrup handler (Figure ). Figure. Couner8 Inerrup Flowchar VC = Cn VC 5 Value cal Equaion Couner8 INTERRUPT waddresscouner RESET RX8 RESET VC cal, he value during he calibraion procedure, is se o 00 and f is he AC line frequency. Reurn Augus 5, 005 Documen No. 00 Rev. ** 8
The GPIO is used for he zeroing of Couner8 (his is in he absence of an enable signal on he Couner8). See Figure. Figure. GPIO Inerrup Flowchar GPIO INTERRUPT Couner8 Reurn RESET The SleepTimer inerrup handler flowchar is shown in Figure. Figure. SleepTimer Inerrup Flowchar SleepTimer INTERRUPT Iniializaion of he variables ha conain lamp brighness value is done under he following condiions: DMX bus sleepmode suppor swiched ON and inerrup handler is no se from RX8 bsl flag during he onesecond imeou period. The AnalogColumn inerrup handler from he comparaor bus consiss of wo funcions. Firs he device relaive o he AC line frequency is calibraed and second, he PWMs are iniiaed. The flowchar of he AnalogColumn inerrup handler is shown in Figure. Once he wfrequancy flag is cleared (calibraion has no ye occurred), incremenaion of he bcoun couner is done. When he couner value is equal o zero, he Couner8 sars. When he couner value is equal o, he Couner8 sops and he calibraion compleion flag is se. If calibraion was done, he inerrup handler from he comparaor sops all PWMs and ses PulseWidh of all PWMs according o prese lamp brighness (which is saved in he bpower variables in main.c). PRT0DR[] == bsl == 0 bpower = 0; bpower = 0; bpower = 0; bpower = 0; bpower5 = 0; bpower = 0; Reurn Augus 5, 005 Documen No. 00 Rev. ** 9
Figure. AnalogColumn Inerrup Flowchar Analog Column INTERRUPT wfrequency == 0 bcoun == bcoun == 0 PWM8_ PWM8_ PWM8_ PWM8_ PWM8_5 PWM8_ STOP STOP STOP STOP STOP STOP Couner8 STOP wfrequency = PulseWidh = bpower PulseWidh = bpower PulseWidh = bpower PulseWidh = bpower PulseWidh5 = bpower5 PulseWidh = bpower bcoun Couner8 START bcoun PWM8_ PWM8_ PWM8_ PWM8_ PWM8_5 PWM8_ START START START START START START Reurn If he daa bye eners from he DMX line, he RX8 inerrup handler is invoked (see Figure 5). I reads he daa and saus byes. If wcounaddress conains more han 5 channels, or errors in he bye saus are deeced (OverrunError, FramingError), he RX8 sops. Couner8 is used o resar he RX8 inerrup handler. This means ha a new daa burs has enered. On he oher hand (he value of address couner is correc and here are no errors), he device address is formed in he wswich variable and hen compared wih he value of he address couner. If he address of any lamp maches he value of he address couner, he daa bye is pu in he corresponding variable. Afer he comparison, he address couner is incremened. The RX8 inerrup handler also ses he bsl flag, which means he DMX bus is acive. If he value of lamp brighness is 55, he TRIACS will malfuncion (because volage of he AC line frequency is no enough o suppor he TRIAC ON sae). Therefore, lamp brighness mus be no greaer han 5. The difference beween 5 and 55 is 0.0%, which is impercepible o he human eye. In order o increase noise immuniy (oscillaions of elecric supply nework), all PWMs sop when heir couner value is equal o zero. This riggers he TerminalCoun inerrup handler for each PWM. This echnique eliminaes phase error accumulaion caused by AC frequency measuremen errors. Augus 5, 005 Documen No. 00 Rev. ** 0
Figure 5. RX8 Inerrup Flowchar RX8 INTERRUPT bsaus =RX8_bReadRxSaus bdaa=rx8_breadrxdaa bsl= bdaa == 55 bdaa=5 (FramingError ) (waddresscouner >5) (OverrunError) RX8 STOP wswich = PRTDR wswich = PRTDR[7] if(waddresscouner =wswich0) bpower=bdaa; if(waddresscouner =wswich) bpower=bdaa; if(waddresscouner =wswich) bpower=bdaa; if(waddresscouner =wswich) bpower=bdaa; if(waddresscouner =wswich) bpower5=bdaa; if(waddresscouner =wswich5) bpower=bdaa; waddresscouner Reurn Augus 5, 005 Documen No. 00 Rev. **
TRIAC Conrol, Synchronizaion Signal Waveforms Figure shows he four waveforms colleced. AC line frequency Signal on AC Synchronizer oupu (in Figure 5 i is called F00 ) Signal on PWM oupu TRIAC conrol pulse Figure. TRIAC Conrol and Synchronizaion Signal Waveforms Figure 7. Board Augus 5, 005 Documen No. 00 Rev. **
Summary The opimal srucure for a mulichannel dimmer sysem (more han channels) is a wochip design (Figure 8). The DMX Proocol receiver can be implemened using he lowcos, CY8Cxxx PSoC device family. The channel PWM generaor can be buil using he CY8C9xxx family or even a sofware implemened mulichannel PWM generaor. In his case, he second chip can be from he CY8Cxxx family as well. Figure 8. Channel DMX Sysem Family or 9 Family Lamp OPTO DMX Receiver Daa Ready for Nex ZeroCrossing Module Frequency Calibraion PWM Conrol Up o TRIACS Lamp AC Zero Crossing Deecor Augus 5, 005 Documen No. 00 Rev. **
Abou he Auhor Name: Tile: Background: Conac: Pero Kobluk Applicaion Engineer Pero graduaed from Naional Universiy Lviv Polyechnic (Ukraine) in 00 wih a degree specializing in compuer sysems. pero_kobluk@ukr.ne In March of 007, Cypress recaaloged all of is Applicaion Noes using a new documenaion number and revision code. This new documenaion number and revision code (00xxxxx, beginning wih rev. **), locaed in he fooer of he documen, will be used in all subsequen revisions. PSoC is a regisered rademark of Cypress Semiconducor Corp. "Programmable SysemonChip," PSoC Designer, and PSoC Express are rademarks of Cypress Semiconducor Corp. All oher rademarks or regisered rademarks referenced herein are he propery of heir respecive owners. Cypress Semiconducor 98 Champion Cour San Jose, CA 95709 Phone: 08900 Fax: 08970 hp://www.cypress.com/ Cypress Semiconducor Corporaion, 005007. The informaion conained herein is subjec o change wihou noice. Cypress Semiconducor Corporaion assumes no responsibiliy for he use of any circuiry oher han circuiry embodied in a Cypress produc. Nor does i convey or imply any license under paen or oher righs. Cypress producs are no warraned nor inended o be used for medical, life suppor, life saving, criical conrol or safey applicaions, unless pursuan o an express wrien agreemen wih Cypress. Furhermore, Cypress does no auhorize is producs for use as criical componens in lifesuppor sysems where a malfuncion or failure may reasonably be expeced o resul in significan injury o he user. The inclusion of Cypress producs in lifesuppor sysems applicaion implies ha he manufacurer assumes all risk of such use and in doing so indemnifies Cypress agains all charges. This Source Code (sofware and/or firmware) is owned by Cypress Semiconducor Corporaion (Cypress) and is proeced by and subjec o worldwide paen proecion (Unied Saes and foreign), Unied Saes copyrigh laws and inernaional reay provisions. Cypress hereby grans o licensee a personal, nonexclusive, nonransferable license o copy, use, modify, creae derivaive works of, and compile he Cypress Source Code and derivaive works for he sole purpose of creaing cusom sofware and or firmware in suppor of licensee produc o be used only in conjuncion wih a Cypress inegraed circui as specified in he applicable agreemen. Any reproducion, modificaion, ranslaion, compilaion, or represenaion of his Source Code excep as specified above is prohibied wihou he express wrien permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves he righ o make changes wihou furher noice o he maerials described herein. Cypress does no assume any liabiliy arising ou of he applicaion or use of any produc or circui described herein. Cypress does no auhorize is producs for use as criical componens in lifesuppor sysems where a malfuncion or failure may reasonably be expeced o resul in significan injury o he user. The inclusion of Cypress produc in a lifesuppor sysems applicaion implies ha he manufacurer assumes all risk of such use and in doing so indemnifies Cypress agains all charges. Use may be limied by and subjec o he applicable Cypress sofware license agreemen. Augus 5, 005 Documen No. 00 Rev. **