Performance and Reliability of the sub-100nm FDSOI with High-K K and Metal Gate Bich-Yen Nguyen, Anne Vandooren, Aaron Thean, Sriram Kalpat, Melissa Zavala, Jeff Finder, Ted White, Skip Egley, Jamie Schaeffer, Dina Triyoso, Darrell Roan, Michael Ramon, Sri Samavedam, Raghaw Rai, Lata Prabhu, Alexander Barr, Mariam Sadaka, Leo Mathew, Kurt Eisenbeiser, Marius Orlowski and Joe Mogab APRDL, Digital DNA Laboratories Semiconductor Products Sector Motorola Inc 6 th Annual Topical Research Conference on Reliability October 27-28, 2003 1
Outline Motivation High K FDSOI Fabrication Electrical results Mobility Performance Reliability Conclusions
Portable Communication Devices Trend Portable Longer Lasting Electronics Which Do More Things Better! Smaller, Lighter, More Data Anything you can imagine Zinc-Air Fuel-Cell NiCad Ni-MH Li-Ion 1980 1990 2000 2010
Power P(avg) = P(dynamic) + P(short) + P(static) + P(leakage) Active Power: P(dynamic) => Capacitive switching = CV 2 F P(short) => Crow-bar or transition current Standby Power: P(static) => DC power P(leakage) => Sub-threshold and gate leakage currents
CMOS Device Scaling Driving force High speed Low power consumption High package density Moore s Law The number of transistors per square inch on integrated circuits doubles every 18 months
S Bulk G BULK Bulk and SOI Transistors D Partially-Depleted SOI S G Tsi = 300-500A BOX D Fully-Depleted SOI (aka Ultra-thin body, depletedsubstrate transistor, etc.) S G Tsi < 150A BOX D 1. Scaling limited by diffused junctions (high halo & steep retrograde well) 2. Subthreshold slope degraded by increased doping 3. Higher junction leakage due to GIDL 4. Higher junction capacitance 5. Channel dopant fluctuations 1. Scaling limited by diffused junctions (but not so high halo needed) 2. Subthreshold slope degraded 3. Junction leakage can still be high 4. Lower junction capacitance 5. Channel dopant fluctuations 6. Floating-body effect 7. Self-heating? 1. Scaling limited by body thickness (intrinsic body) 2. Improved subthreshold slope 3. Junction leakage minimized 4. Lowest junction capacitance 5. No channel dopant fluctuations 6. No Floating-body effect 7. Self-heating? 8. VT adjustment (metal gate+intrinsic body)
Impact of Junction Capacitance (IBM study) (From: G.G. Shahidi, SOI technology for the GHz era, IBM J. Res. & Dev. Vol. 46 No. 2/3 Mar/May 2002) Gain from Cj reduction diminishes for every generation until 0.22um Gain increases beyond 0.18um!!! FDSOI The The change change comes comes from from the the need need for for higher higher doing doing concentration concentration to tocontrol SCE SCE in in bulk bulk Si. Si. As As such such Cj Cj start start forming forming a larger larger portion portion of of node node capacitance. capacitance.
C gate (ff/µm 2 ) 30 20 10 0 0 Mandates for Change in Gate Stack T ox (Å) 100 50 30 20 15 C gate C E C OX C Si 10 20 C ox (ff/µm 2 ) Ideal Metal Gate Poly Gate (5E19/cm 3 ) V g = V t +1V Na = 1E17/cm 3 30 Source As the Thickness of the Gate Oxide (T ox ) is Reduced: Poly Depletion Reduces Gate Capacitance Boron Penetration Causes V t Instability Gate Gate Oxide Gate Leakage Current (A/um) Time --> 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 Drain 07 03 01 99 PMOS NMOS 10X 3Å SiO2 Gate Dielectric 5 10 15 20 25 30 35 40 T ox (Å) 1nA/um Logic 1pA/um Wireless Leakage Through the Gate Oxide Becomes Unacceptable for Standby Power Dissipation in Wireless Applications 96
A Fundamental Change Is On The Horizon Source Gate Poly Drain Semiconductor Roadmap SiO2 1.5nm Today The Future S D G High k.. is almost here?
Solution Gate Stack Replacement Polysilicon Gate Metal Gate SiO 2 Gate Dielectric High K Dielectric Now Future Use a thicker gate oxide with a higher dielectric constant to reduce leakage C ox = ke o A/d ox
Gate Leakage Reduction by High K Dielectric Leakage Current (A/cm 2 ) 10-1 10-0 10-1 10-2 10-3 10-4 10-5 10-6 10-7 SiON Less leakage High k Lower power SiO2 5 10 15 20 25 30 35 Equivalent Oxide Thickness (Å) Ig limit For Logic Ig limit For wireless High-k means: 1. Transistors will have less leakage & power loss 2. Circuit design will have extra breathing room.
Tradeoff with EOT Gate SiO 2 Gate High K Gate High K SiO x Si substrate Si substrate Si substrate good interface low dielectric K poor interface high dielectric fair interface fair dielectric April 27, 2000 High K Gate Dielectrics 17
Undoped vs Doped Channel for SOI H. Shimada, IEEE Trans. Electron Dev. Vol. 44, Nov. 1997. Two approaches to achieve Vt requirements: 1. N+/P+ poly gate with highly doped Si film : problem of reduced mobility, dopant fluctuations,... 2. Midgap gate material with undoped Si film Advantages of Undoped Channel: 1. Reduce threshold voltage sensitivity to silicon thickness variation 2. Reduce transverse field leading to higher mobility 3. Reduce sensitivity to dopant fluctuation effects 4. Reduce process complexity by using single electrode for both n- and p-mosfets
TEM of FDSOI with High K and Metal Gate nitride L g =50nm CoSi 2 STI isolation Silicon film thickness: 140Å Undoped channel ALCVD HfO2 with TiN gate Raised SD extension regions Source/Drain anneal: 900 C Co silicidation Poly Si epi TiN Si epi 163Å TiN 32Å HfO 2 BOX IL 18Å 140Å Si
Mobility of FDSOI with High-K/Metal Gate 50% 1. Peak electron mobility improved by 40-50% due to change in gate stack (450cm2/Vs). 2. Peak electron mobility of TiN/HFO2 FDSOI is 10% higher than Poly-Si/SiO2 bulk devices due to the lowering of the effective field at operation 3. Hole mobility is not degraded and also improved over bulk mobility at operation
Electrical Results of Long Channel FDSOI Electrical Results of Long Channel FDSOI Lg= 10um Nearly ideal subthreshold slope of 62mV/dec low front and back interface trap density. Charge pumping measurements result in Dit ~ 3 to 6E11/cm2.eV at front interface. Vt,lin are -0.37V and 0.42V for p and nmosfets, respectively. No series resistance problem
Threshold Voltage Variation V T varies by +/-10mV at T si,avg = 142Å +/- 17% Low V T variation is due to the use of undoped channel
Short Channel FDSOI MOSFETs L g =65nm, T si =140Å, CET=29Å nmos: Ioff=2.58nA/mm Ion=442mA/mm SS=74mV/dec DIBL=54mV/V pmos: Ioff=6.4pA/mm Ion=198mA/mm SS=73.4mV/dec DIBL=52mV/V L g =50nm, T si =140Å, CET=29Å nmos: I off =19nA/mm I on =493mA/mm SS=76.8mV/dec DIBL=70mV/V pmos: I off =44pA/mm I on =212mA/mm SS=77mV/dec DIBL=75mV/V
Gate Leakage and Reliability V G1 = V T1 +1V V G2 = 0V I G, HfO2 < < I G, SiO2 At V G1,stress = 1.5V (E = 7.4MV/cm) for 1000sec, no change (slight I off decrease) At V G1,stress = 2V (E 10MV/cm) for 100sec, positive shift of V T by ~50mV and slight decrease in g max1. The degradation remains unchanged up to 1000sec
Time to exceed 50 mv (hr) Reliability of High K/Metal Gate 1.E+14 1.E+12 1.E+10 1.E+08 1.E+06 1.E+04 1.E+02 1.E+00 R FDSOI vs Bulk Time to 50 mv shift SOI metal gate Time to 50mV shift Bulk Expon. (Time to 50mV shift Bulk) Expon. (Time to 50 mv shift SOI metal gate) 1.E-02 0 0.5 1 1.5 2 2.5 3 Vstress (V) FDSOI: Both PMOS and NMOS meet CMOS90 reliability spec easily, thick SiO2 interfacial layer (~22 Å/33 A HfO2) used Vt shift in FDSOI is believed to be minimal due to low PID in HfO2 film due to thick interfacial oxide
Ring Oscilator Performance L g =65nm At V DD =1.2V stage delay = 15.8ps At V DD =1.5V stage delay = 12.6ps
Conclusions Conventional planar 50nm MOSFET processing with elevated SD, high-k and single metal electrode. Undoped channel efficiently reduces V T variation Symmetric V T for n and pmosfets using TiN or TaSiN metal gate on HfO 2 Excellent I on /I off device performance at 50nm gate length, with very good control of SCE at 14nm silicon film thickness. Hole mobility matches universal curve. Electron mobility about 10% degraded compared to universal curve at operating voltage. At same operating voltage (inversion charge), electron mobility in FDSOI HfO 2 is close to bulk mobility on SiO 2 due to reduced field in undoped devices. Good reliability for FDSOI devices with high-k and metal gate Functional ring oscillator with 15ps stage delay @1.2V demonstrated for the first time with FDSOI/metal gate/high-k technology