Delay-based clock generator with edge transmission and reset

LETTER IEICE Electronics Express, Vol.11, No.15, 1 8 Delay-based clock generator with edge transmission and reset Hyunsun Mo and Daejeong Kim a) Department of Electronics Engineering, Graduate School, Kookmin University, 861 1 Jeongneung-dong, Seongbuk-gu, Seoul 136 702, Korea a) kimdj@kookmin.ac.kr Abstract: When a pulse transmits through delay stages, it dies out after all unless the rising and falling delays are perfectly matched. Alternatively, an edge can be transmitted through the new generateand-reset delay stages if properly reset in time. A new delay-based clock generator adopting the delay stages is proposed on that account. It is attractive in that the maximum operating frequency can be comparable to that of the ring oscillator. Furthermore, the reset of the pulse in the delay stage cleans out the random noise as well, inhibiting any noise residue phenomenon. Keywords: delay stage, delay-based clock generator, ring oscillator Classification: Integrated circuits References [1] B. Kim, T. Weigandt and P. Gray: IEEE ISCAS 4 (1994) 31. DOI:10.1109/ ISCAS.1994.409189 [2] B. Mesgarzadeh and A. Alvandpour: IEEE J. Solid-State Circuits 44 (2009) 1907. DOI:10.1109/JSSC.2009.2020229 [3] M. Woo, B. Moon and D. Kim: IEICE Trans. Electron. E92-C (2009) 1315. DOI:10.1587/transele.E92.C.1315 1 Introduction Typically, ring-type VCOs are of particular interest for the clock generation in terms of the integration and the cost, but suffer from larger timing jitter than that of delay-based clock generators [1, 2]. The jitter per cycle of oscillation is determined by the sum of timing error contributions of each inverter stage in the ring. The jitter accumulated by the end of the inverter contributes to a starting point of the next cycle, which is the noise residue phenomenon. On the other hand, delay-based circuits can produce multi-phase clocks with a good performance, but it needs the reference clock and phase comparison in the feedback configuration (e.g. DLLs). The author previously introduced a delay-based clock generator [3], however, it has also been achieved in the DLL framework. 1

Based on the previous work, a new mechanism which overcomes the limitation of VCOs especially in terms of the noise residue phenomenon is proposed. It does not need a reference clock by adopting the edge transmission-and-reset, and behaves completely on the delay-based concept. 2 Delay-based clock generation Pulse transmission: Fig. 1(a) shows a model for the transmission of the pulse through the inverter-type delay stages. The rising delay, d r, and the falling delay, d f, consist of RC delays ( ¼ 0:69RC), the product of turn-on resistance and parasitic capacitance of the transistor. When the pulse passes through a delay stage, the high duration ratio of the input and output pulses is as follows; d ¼ h out h in ¼ h in þ d f d r h in ¼ 1 þ d f d r h in ¼ 1 þ 0:69 ðr p1 R n1 ÞC 1 þðr n2 R p2 ÞC 2 ð1þ h in where h in and h out are the high durations for the input and the output pulse, respectively. It deviates from 1 if the turn-on resistance of pmos and nmos transistors is mismatched. If the ratio is kept to be constant, the high duration at the end of the N delay stages reaches h 0 d N where h 0 ¼ T=2, that (a) (b) (c) (d) Fig. 1. Pulse transmission models (a) Conventional inverter-type delay stages with delay model (b) Proposed pulse transmission stages with delay model (c) Timing diagram of the pulse being degraded during the transmission (d) Edge transmission and reset at the interval of d unit. 2

of the input to the 1 st stage. The duty-cycle error is accumulated as the pulse goes through the stages, consequently, and it deteriorates the pulse to be vanished when d>1 as shown in Fig. 1(c). The output duty-cycle ratio D in Eq. (2) gives a criterion for the pulse to be transmitted alive. The maximum number of the stages N can be calculated so that D approaches near 1, or 0. (full high or low duration) D ¼ h 0d N ¼ 1 T 2 dn where 0 <D<1 ð2þ Fig. 1(b) shows the edge transmission and reset by adopting the proposed resettable delay stages. The unit delay stage consists of the input transistor M 1 and an inverter to generate the rising edge, and the transistor M 2 to reset the pulse. C 1 and C 2 represent parasitic capacitors. When the previous rising edge arriving at node turns on M 1 and passes through the inverter, a new rising edge is generated at node fi. Successively, M 3 drain voltage in the next stage falls down and turns on M 2, which in turn resets the existing pulse at node fi. Therefore, the combined delay of R n1 C 1 and R p C 2 (R n1, R p are the on resistances of M 1 and the pmos of inverter) constitute the unit delay d unit.as shown in the timing diagram of Fig. 1(d), the incoming pulse at node triggers the repetition of the edge generation and reset at the interval of d unit. The pulse width of d unit enables the infinite edge transmission, and avoids any duty-cycle error accumulation because it is kept to be constant. Clock generation: A conventional current-starved VCO is shown in Fig. 2(a) with a random noise v N incorporated in the second stage. A period jitter is ingenerated as all the stage delays contribute to the total period. Even after the noise diminishes, the residual noise voltages still exist at the parasitic capacitances over the next couple of periods. The simplest delay-based clock generator (DCG) is just using the proposed three resettable delay stages in the loop configuration as shown in Fig. 2(b). The unit stage consists of N 1 (input transistor), P 1 (reset transistor), I 1 (logic evaluation gate), and an additional transistor to take in the trigger pulse enabled only once and for all at the first stage. The trigger pulse should be a single shot as shown in Fig. 2(c). An edge is generated by the previous output and reset by the next edge at the interval of d unit ¼ 2 where ¼ 0:69RC is the delay time for single inversion. When the rising edge arrives at the last stage (node fi) going through the loop, it generates the new rising edge at the starting stage (node ). Direct cascading of multiple stages in the ring effectively configures the infinite number of stages in series, which leads to the never-ending pulses at each stage output with the period of 3 d unit. When the node is staying at high, the subsequent low state at node X passes through I 2,N 3 and P 2, and is reset to high. It also moves backward from X through P 1 and I 1 ; thereby, N 2 pulls down the node slightly before P 2 turns on, avoiding any contention between them. Therefore, there is no constraint on the size of pmos that can be adopted as the reset transistor. In this regard, Fig. 2(d) shows the 4-stage extension adopting the unit delay stage. The period shown in Fig. 2(e) is resolved into the four phases 3

corresponding to N because the identical stages are contained. The period T ¼ N d unit ¼ 2N is exactly the same to that of the ring oscillator. Further, Fig. 2(f ) shows that the duty cycle of the first stage output can be adjusted to be 50% when it is reset by fi instead of. To sum up, the proposed DCG can be configured with any integer number of stages (N 3) since it transmits the edge of the pulse triggered by a single shot, which is distinguished from other oscillators. (a) (b) (c) (d) (e) (f) Fig. 2. (a) Conventional current-starved VCO with noise incorporated (b) proposed 3-stage DCG (c) and its timing diagram of the uncombined outputs (d) proposed 4-stage DCG configuration (e) and its timing diagram of combined output with noise at d 2 (f ) timing diagram to get 50% duty-cycle rate Sticking to the basic principle of the proposed DCG, a variable delaybased clock generator (VDCG) can be implemented by adopting the variable delay cells; the proposed variable delay cell (generate-and-reset cell, G&R cell) employs either a current sink or a current source as shown in Fig. 3(a) and (b), respectively. To produce a variable delay, the charging current is varied enforced by the analog control voltage v C. Fig. 3(c) shows a detailed circuit diagram of the G&R cell along with the bias stage. The G&R cell is composed of a current source (M 1 ) controlled by v C, input switch transistor (M 2 ), a MOS capacitor (C), the reset switch (M 5 ) driven by the reset signal R, and the logic evaluator (I 1 ). M 2 and M 3 are switch transistors for the input or the trigger edge to be taken in, respectively; M 3 is active only in the first stage. M 4 steers the cell current to the ground to minimize the switching noise when the input clock is disabled. In such an environment, Fig. 3(d) shows the 4-stage VDCG which complies with the 4-stage DCG in Fig. 2(d). In order to produce the inter- 4

(a) (b) (c) (d) (e) (f) Fig. 3. (g) (a) Proposed variable delay cell (current sink type) (b) proposed variable delay cell (current source type) (c) detailed circuit of proposed variable delay cell (G&R cell) (d) 4-stage VDCG configuration (e) and its timing diagram with edge combine (f ) edge combiner with pulse generation first, then combine (g) edge combiner with odd-even combine first, then pulse generation and merge. 5

polated frequency (f EC ¼ 1=d unit 1=2) without respect to N, the edge combination (EC) is referred. Generally, d unit should be controlled so that the edge combiner can operate properly; thereby VDCG is preferable than DCG. The output at node can be produced as shown in the timing diagram of Fig. 3(e) either by combining all stage edges altogether or by combining odd and even-stage edges independently to secure the timing margin, then added. The high duration of the combined pulse should be shorter than d unit (the period) to build the low duration in the pulse. The noise tolerance is depicted when a random noise of one period intervenes in the 2 nd stage. The delay from to is affected, and as the noise is reset by the next stage, there are no effects on the other nodes and the next pulse. Two kinds of the edge combiner were developed: pulse generation first, then combine as shown in Fig. 3(f ), edge combine of separate odd-even stages first, then pulse generation and merge as shown in Fig. 3(g). The pulse generation to produce narrower width than d unit is triggered at the clock terminal of the positive edge-triggering D F/F, and then is self reset through the inverter chain; the pulse width is determined mostly by the reset path delay. Edges are merged using the pseudo-nmos OR gate which in practice constrains the speed of the whole edge combiner. The former is a better option in term of speed because the shorter width of pulses comes into the pusedonmos OR gate. The latter, on the other hand, needs a smaller hardware at the cost of harsher input condition to the pusedo-nmos OR gate. 3 Noise response and simulation results Fig. 4(a) depicts a behavioral circuit model in terms of the response to the external noise. When V X arrives at the inverter logic threshold, a falling edge occurs after the inverter. The enforced noise v N on the gate voltage of M 1, the current source shown in Fig. 3(c), creates the error current i which gives the timing perturbation of t. If the current i is assumed to be much smaller than the bias current I, the total delay would be as follow d unit þ t ¼ C V logic ¼ C V logic 1 þ i 1 C V logic 1 i for i I I þ i I I I I ð3þ where the inverter delay is ignored. By utilizing the small-signal analysis with i ¼ g m v N, the period jitter is associated with v N : t ¼ C V logic I 2 d unit I i C V logic ¼ i I ¼ g m I v N ¼ s ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi W 2C ox L pffiffi v N ð4þ I where g m is the transconductance of M 1. When the compulsory noise Vn is applied to a stage during the single period, the period jitter of the uncombined output is inversely proportional to N since the noise influences only on the specified stage making no difference on the other stages. Fig. 4(b) shows the simulated results of the 4-stage VDCG by varying v N, and compared with Eq. (4). The circuit parameters used in the 6

(a) (b) (c) (d) (e) Fig. 4. Circuit and simulated results (a) circuit model for noise calculation (b) noise response of proposed 4-stage VDCG (c) period jitters by 5% noise of full v C range (d) period jitters by 15% noise of full v C range (e) operation speed comparison among ring oscillator, DCG without EC, and VDCG with EC. simulations are g m ¼ 88:4 [µs], I ¼ 73:7 [µa], and C ¼ 150 [ff]. Note that the simulated values do not correspond with the calculation when the nonlinear property of the circuit becomes dominant as v N increases. Fig. 4(c) and (d) show the simulated results of the cycle jitters for the uncombined VDCG outputs (N ¼ 3, 4, 8 with d unit ¼ 6:2 ns), and a 3-stage VCO output operating at f O ¼ 460 MHz by varying the noise magnitude of 5% and 15% of the full v C range, respectively. The jitter has been observed over the five cycles even after the noise was abolished after T 1. The VCO period does not return to the normal over the 7

following several periods because the noise voltages have been stored in the node capacitances. The residual jitters induced by the v C noise of 5% and 15% are observed over 3 and 4 cycles after the noise is eliminated. On the other hand, the proposed VDCG returns to the normal as soon as the noise vanishes, that is to say, it does not create any noise residue because the cell is reset along with the noise after the edge is generated. Fig. 4(e) compares the speeds of the ring oscillator, DCG without edge combine, and VDCG with edge combine with respect to the number of stages N. The size of nmos (1.25 µm/0.35 µm) and pmos (2.5 µm/0.35 µm) is chosen all the same in the comparative circuits. Little difference in speed is observed between the ring oscillator and DCG; it complies with the speed consideration mentioned earlier. The speed of VDCG, independent of N, is constrained by the maximum speed of the edge combiner. Considering both the jitter and the speed at the same time, the proposed VDCG with EC can be an optimized option. Table I summarizes the characteristics of the proposed VDCG using a CMOS 0.35 µm process. V DSAT is the overdrive voltage of the corresponding transistor. Table I. Simulated performance summary for the proposed 4-stage VDCG Process CMOS 0.35 µm Supply voltage: V DD 3.3 V Min. unit delay: d unitðminþ 104 ps Max. edge-combined output frequency @ V CðmaxÞ 1.8 GHz Range of control voltage (v C ): V T ðv DD V T V DSAT Þ :2.1 V Min. possible supply voltage: V T þ 2V DSAT :900 mv 4 Conclusion A delay stage to transmit the edge of pulse without accumulating any dutycycle error and its application to the delay-based clock generator has been proposed. The clock generation is possible with any number of stages more than three at the comparable speed of the counterpart oscillator, and it needs a single-shot trigger pulse as it is a perfect delay-based circuit. It does not suffer from any noise residue accumulation due to the cell reset unlike other ring-type oscillators. A voltage controlled delay-based clock generator with edges combined was also provided. Acknowledgments This work was supported by BK Plus with the Educational Research Team for Creative Engineers on Material-Device-Circuit Co-Design funded by the Ministry of Science, ICT & Future Planning (Grant No: 22A20130000042). It was supported by research program of Kookmin University and IC Design Education Center (IDEC), Korea. 8