Zero Steady State Current Power-on-Reset Circuit with Brown-Out Detector

Zero Steady State Current Power-on-Reset Circuit with Brown-Out Detector Sanjay Kumar Wadhwa 1, G.K. Siddhartha 2, Anand Gaurav 3 Freescale Semiconductor India Pvt. Ltd. 1 sanjay.wadhwa@freescale.com, 2 siddhartha.gk@freescale.com, 3 anand.gaurav@freescale.com Abstract A novel Power on reset (POR) circuit with Brown out (BO) detector having zero steady state current consumption is proposed. The circuit has been designed in 65nm CMOS process at a single supply of 1.1V. Both the POR and BO thresholds are independently adjustable in the circuit. Simulation results show that the POR threshold does not depend upon the supply ramp-rate at fixed process and temperature corner. BO circuit works for a large range of supply ramp down rates. Due to zero steady state current consumption, the proposed circuit is well suited for low power applications. 1. Introduction Low power design has been a topic of interest of researchers and designers that has compelled the industry to produce circuit designs with very low supply voltage and current consumption. POR and BO detector circuits are an integral part in today s System on Chip (SoC) designs. A POR circuit provides a reset signal to the chip when supply ramps up so that the chip always starts in a known state [1]. A BO detector provides reset signal to the chip when the chip supply voltage falls below a level required for its reliable operation. Resetting of the chip in BO event avoids any unpredictable behavior of the overall system. Normally, two separate circuits are employed to generate POR and BO reset signals so as to have independent control over POR and BO thresholds. The proposed circuit works both as a POR and BO detector with independently adjustable thresholds, with wide supply ramp up and ramp down rates without consuming any steady state current [2, 3]. 2. Circuit Diagram The proposed circuit is shown in Fig. 1. The POR and the BO portions of the circuit are shown with dashed outlines. 2.1 Detector Circuit In Fig. 1, the detector circuit in the POR portion consists of a resistor divider R1, R2 & R ds of PMOS transistor M1 followed by two inverters INV1 and INV2. Voltage at node d1 is given as R2 V(d1) = R1+ R2 + R ds VDD (1) Fig. 3 shows the simulation waveforms of the POR detector circuit with VDD ramp-rate equal to 500us, ramping up from 0 to 1.1V. As VDD starts rising from 0V, initially node d1, output of the detector, det_out and gate of M1, det_en are at 0V (low) and node d2 follows VDD. As VDD crosses threshold voltage (V thp ) of M1, V(d1) starts rising. When V(d1) crosses the trip voltage of the inverter INV1, node d2 goes low. As a result, node det_out goes high and starts following VDD. Thus, det_out remains low till VDD crosses the trip voltage of INV1. The VDD voltage at which det_out goes high is called POR de-assertion threshold. Both R ds of M1 and trip voltage of INV1 vary with process corner and temperature and therefore, POR deassertion threshold will vary with process corner and temperature. The RC time constant of V(d1) rise will be very low as compared to the VDD ramp up rate due to very low capacitance at node d1 (only the gate capacitance of INV1 will be present ). Due to low RC time constant at node d1, det_out will go high at the same voltage determined by the process corner and temperature at different VDD ramp up rates. Thus, the POR de-assertion threshold will remain constant at different VDD ramp up rates. 2.2 Pulse latch circuit The pulse latch circuit in the POR portion of the proposed circuit shown in Fig. 1 latches the detector output, det_out rising edge. In pulse latch circuit, det_out is connected to source of PMOS transistor M2.

Fig. 1. Proposed POR and BO detector circuit As VDD starts rising from 0V, node PL5 starts following it because C0 (Poly-Nwell Cap) maintains the initial voltage difference (0V) across it. The trip voltages of INV4 and INV6 are kept low (~200mV) to quickly bring node PL1 and node latch_out low. Node PL3, connected to the gate of M2, also goes low and M2 is turned on. As node latch_out goes low, INV5 also starts charging node PL5 due to latch action. As shown in the simulation results in Fig. 4, during VDD ramp up, initially, det_out and pulse latch output, latch_out are low. Voltage at node latch_out is buffered by a chain of buffers to generate voltage at node det_en and at POR output, por_out_b. Thus, till the time node latch_out remains low, both node det_en and por_out_b remain low. In this condition, POR remains asserted and chip remains in reset state. As VDD exceeds the POR de-assertion threshold, node det_out goes high and start following VDD as shown in Fig. 3. Since M2 is on, node PL4 also goes high. Thus, INV3 trips, node PL5 goes low and node latch_out, det_en and POR output, por_out_b go high. Node PL3 goes high after 3 inverter delays after node PL5 goes low (delay of INV6, INV7 and INV8) and turns off M2. With det_en high, M1 turns off, shutting the direct current path through it and bringing node det_out to low. Since M2 is already off, this low transition at node det_out does not propagate through the pulse latch circuit to the POR output. With M2 being off, node PL4 becomes floating and may slowly discharge by the leakage current of M2. If V(PL4) discharges below the trip voltage of INV3, node PL5 will go high and por_out_b will go low, asserting the POR again. This will reset the chip and cause malfunctioning. To avoid this situation, an NMOS transistor M3 with drain, gate and source connected to VDD, node latch_out and node PL4 respectively has been added. When node latch_out goes high, M3 turns on and pulls node PL4 to VDD - V thn where V thn is the threshold voltage of M3. Therefore, node PL4 will never discharge below VDD V thn ensuring that node por_out_b will remain high. During VDD ramp up, node PL4 starts rising due to gate to source capacitance (C gs ) of PMOS transistor in INV3. If V(PL4) rises above the trip voltage of INV3, node PL5 will go low, node latch_out and node por_out_b will go high. Thus, POR output, por_out_b

will go high even before VDD has crossed the POR deassertion threshold. To avoid this condition of false POR de-assertion, a small value (~100f F) capacitor C2 (Poly-Nwell Cap) has been placed between node PL4 and VSS. Capacitor C2 forms a voltage divider with C gs of PMOS transistor in INV3. Due to C2, V(PL4) does not rise beyond the trip voltage of INV3 and node latch_out remains low, preventing false POR deassertion condition. 2.3 BO detector circuit The BO detector circuit shown in Fig. 1 works on the principle of storing charge on a capacitor to be utilized during brown out event. During supply brown out, this stored charge is used to pull-up or pull-down different POR internal nodes so that POR output, por_out_b goes low. The circuit has a diode connected PMOS transistor M4 with source connected to VDD and gate-drain connected to capacitor C1 (Poly-Nwell Cap) at node cap_vdd. When VDD ramps-up to its full voltage, cap_vdd is charged at least to (VDD-V thp ) through M4 and node g1 is pulled low by NMOS transistor M6. In this condition, NMOS transistors M7, M8 and PMOS transistor M9 are off. The drain of M7, M8 and M9 are connected to node PL4, node latch_out and node PL5 respectively. Depending upon the number of nodes needed to be pulled high or pulled low in POR circuit during BO event, the number of outputs from BO circuit can be selected. This property of proposed BO detector circuit makes it generic in nature and it can be used with different types of POR circuits. BO circuit with multiple pull-up and pulldown outputs is shown in Fig. 2. M4 goes into cutoff. However, due to leakage currents, V(cap_vdd) starts discharging but capacitor C1 slows down the rate of discharge of cap_vdd. During BO event, when VDD drops below V(cap_vdd) by more than V thp of PMOS transistor M5, it turns on and pulls node g1 towards cap_vdd ( M6 is kept very weak to enable sufficient charging of node g1) and subsequently, node PL4, node latch_out are pulled low and node PL5 is pulled high towards cap_vdd. This initiates a positive feedback action in latch composed of INV4 and INV5 and POR output, por_out_b goes low. A high value resistor can also be used in place of M4 to charge C1. The advantage of having a resistor in place of M4 would that it will charge cap_vdd to full value of VDD. The RC time constant of diode connected M4 and C1 will determine the slowest BO rate that can be detected. 3. Simulation results Fig. 3 and Fig. 4 show the simulation results of only the POR detector circuit and pulse latch circuit respectively, with VDD ramping up from 0V to 1.1V in 500us. The simulation results in Fig. 3 and Fig. 4 have been explained in section 2.1 and 2.2. Fig. 5 and Fig. 6 show the simulation results of complete circuit shown in Fig. 1 with VDD ramp up rates of 10us and 25ms respectively at TYP corner, 25C. For the sake of clarity, only POR action has been shown in Fig. 5 and Fig. 6. Fig. 2. BO Detector Circuit with multiple pull-up and pull-down outputs Fig. 3. POR detector simulation results with VDD ramp-rate = 500us When VDD is stable, the BO detector does not consume any leakage current because all the current paths from VDD to VSS are off. During a BO event, when VDD drops below V(cap_vdd), PMOS transistor

Fig. 4. Pulse latch simulation results with VDD ramp-rate 500us It is clear from Fig. 5 and Fig. 6 that POR assertion and de-assertion voltages are nearly same for 10us and 25ms VDD ramp up rates. This feature greatly enhances the reliability of chip power up for different VDD ramp up rates. It is also clear from Fig. 5 and Fig. 6 that after POR action is over, the current consumption of the proposed circuit is almost zero in steady state. Only leakage current of the order of na flow in the circuit because in all the constituent modules of the proposed circuit, direct current paths from VDD to VSS are off after POR output, por_out_b is de-asserted. Fig. 7 and Fig. 8 show the simulation results of complete circuit shown in Fig. 1 with brown out event. In Fig. 7 and Fig. 8, VDD falls to 250mV from 1.1V in 1us and 25ms respectively and ramps up again to 1.1V in 10us. These simulation results are also at TYP corner, 25C. Fig. 5. Simulation results showing POR action with VDD ramp-rate = 10us Fig. 7. Simulation results showing BO detection with VDD ramp down rate during BO = 1us Fig. 6. Simulation results showing POR action with VDD ramp-rate = 25ms In Fig. 7, node cap_vdd is at about 780mV before BO event and drops to about 750mV during BO event due to charging of node g1 and node PL5. POR output, por_out_b is pulled low and as VDD ramps up again, it

goes high after VDD crosses POR de-assertion threshold. In Fig. 8, node cap_vdd starts decreasing with VDD ramp down because of slow VDD ramp down rate in BO event. Before BO event, node cap_vdd is charged to about 850mV because of large time given for it to settle as compared to Fig. 7. As VDD falls to 250mV, POR output, por_out_b goes low and again goes high when VDD crosses the POR de-assertion threshold. The ramp down rate of node cap_vdd voltage with VDD ramp down can be reduced by increasing the capacitor value C1 and/or by increasing the resistance (R ds ) of diode connected transistor M4. The value of C1 and R ds determine the maximum time in which VDD can ramp down during BO event. The larger the time required, the larger should be the value of C1 and R ds. VDD is ramped up from 0V to 1.1V in the given ramp up time. It is apparent from Table 1 that POR deassertion threshold remains almost constant for a wide range of VDD ramp up rates (10us to 25ms) across different process and temperature corners. Table 2 shows the BO detect thresholds across different process and temperature corners at different VDD ramp down rates. The ramp down rates for VDD during BO event was varied from 10us to 25ms from 1.1V to 0V. It is apparent from Table 2 that the BO threshold decreases with the increase in VDD ramp down rate. At slow VDD ramp down during BO event, the BO threshold decreases because voltage on node cap_vdd decreases much faster which makes it more difficult to charge node g1 and node PL5. Table 2: BO detector thresholds across process and temperature corners at different VDD ramp down rates Corner VDD ramp down rate during BO event (VDD = 1.1V) 10us 1ms 25ms Typ_fet, 25C 475m 352m 247m wcs_4sig_fet, 105C bcs_4sig_fet, -25C 546m 333m 217m 445m 349m 264m 4. Design methodology Fig. 8. Simulation results showing BO detection with VDD ramp down rate during BO = 25ms Table 1 shows the POR de-assertion thresholds at different VDD ramp up rates across different process and temperature corners. Worst case (wcs) and best case (bcs) process parameters with 4-sigma variation have been taken. Table 1: POR de-assertion thresholds across different process and temperature corners at different VDD ramp up rates Corner VDD ramp up rate (VDD = 1.1V) 10us 1ms 25ms Typ_fet, 25C 763m 732m 730m wcs_4sig_fet, 105C bcs_4sig_fet, -25C 791m 765m 763m 721m 695m 693m Equation (1) shows the voltage at node d1 which is a fraction of VDD value. The fraction depends upon the values of R1, R2 and R ds of M1 in detector circuit. The POR will assert itself, i.e. will remain low till V(d1) crosses the trip voltage of inverter INV1. Therefore, depending upon the value of POR deassertion voltage required, the values of R1, R2 and R ds of M1 and trip voltage of inverter INV1 should be decided. Trip voltage of INV1 can be adjusted by the sizes of PMOS and NMOS transistors in INV1. The BO detector threshold depends upon the RC time constant of C1 and R ds of M4 and should be chosen depending upon the slowest VDD ramp down rate required. The sizes of M5 and M9 will also decide the BO threshold. For higher BO threshold, sizes of M5 and M9 should be large and vice-versa. The large sizes of M5 and M9 would charge node g1 and PL5 and discharge node PL4 faster, resulting in higher BO threshold. Table 3 shows the sizes of the transistors and value of the capacitors used in the proposed circuit shown in Fig. 1. These sizes have been obtained for a typical

POR de-assertion threshold of 750mV and typical BO threshold of 450mV at 1.1V VDD voltage. Table 3: Sizes of devices in the proposed circuit Device Name Size Device Name Size( W/L) C1 20pF INV3/PMOS 1.2u/0.06u (X2) M1 0.8u/0.24 INV3/NMOS 1.0u/0.06u (X2) M2 0.3u/0.2u INV4/PMOS 0.12u/0.09u M3 0.5u/0.06u INV4/NMOS 1.0u/0.06u M4 0.3u/5u INV4/NMOS 1.0u/0.06u M5 3u/0.16u INV4/NMOS 1.0u/0.06u M6 0.5u/3.0u INV5/NMOS 0.5u/0.06u M7 4.0u/0.1u INV5/NMOS 0.12u/0.06u M8 4.0u/0.1u INV6/NMOS 0.32u/0.06u M9 0.12u/0.12u INV7/NMOS 0.32u/0.06u INV1/PMOS 0.4u/0.06u INV7/NMOS 0.23u/0.06u INV1/NMOS 0.2u/0.06u INV8/NMOS 0.32u/0.06u INV2/PMOS 0.5u/0.06u (X2) R1 10K INV2/NMOS 0.5u/0.06u (X2) R2 25K C2 100f - - b) Both POR and BO circuits work for large variation in VDD ramp up and ramp down rates. c) Very low variation in POR de-assertion threshold occurs at different VDD ramp rates at particular process and temperature corner. d) Zero steady sate current consumption makes the circuit ideal for low power applications. 6. References [1] Yasuda, T.R.; Yamamoto, M.; Nishi, T. A power on reset pulse generator for low voltage applications, IEEE ISCAS 2001, Volume 4, 6-9 May 2001, pp 598 601. [2] Gola et. Al, Power on Reset circuit having a low static power consumption, US patent 5528184, Jun. 18, 1996. [3] Gubbins, Brown-Out Detector, US patent 2004 / 0239413 A1, Dec. 2, 2004. Fig. 9 shows the layout of the proposed POR with BO circuit. The circuit consumes a total die size of only 120umX60um. Fig. 9. Layout of the proposed circuit (120um X 60um) 5. Conclusion A novel POR with BO detector circuit with zero steady state current has been proposed. Simulation results show that a) The design is able to work at low supply voltage, down to 1.1V