PD -9697A Features l Advanced Process Technology l Ultra Low On-Resistance l 175 C Operating Temperature l Fast Switching l Repetitive Avalanche Allowed up to Tjmax l Lead-Free Description This HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in a wide variety of applications. G HEXFET Power MOSFET D D S TO-22AB V DSS = 3V R DS(on) = 2.4mΩ S D G I D = 75A G D S Gate Drain Source Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ 1V (Silicon Limited) 26 I D @ T C = 1 C Continuous Drain Current, V GS @ 1V (Silicon Limited) 18 A I D @ T C = 25 C Continuous Drain Current, V GS @ 1V (Package Limited) 75 I DM Pulsed Drain Current c 12 P D @T C = 25 C Power Dissipation 29 W Linear Derating Factor 2. W/ C V GS Gate-to-Source Voltage ± 2 V E AS (Thermally limited) Single Pulse Avalanche Energyd 29 mj E AS (Tested ) Single Pulse Avalanche Energy Tested Value h 82 I AR Avalanche Currentc See Fig.12a, 12b, 15, 16 A E AR Repetitive Avalanche Energy g mj T J Operating Junction and -55 to 175 T STG Storage Temperature Range C 3 (1.6mm from case ) 1 lbfyin (1.1Nym) Soldering Temperature, for 1 seconds Mounting Torque, 6-32 or M3 screw i Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case j.51 R θcs Case-to-Sink, Flat, Greased Surface i.5 C/W R θja Junction-to-Ambient ij 62 www.irf.com 1 7/22/1
Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 3 V V GS = V, I D = 25µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.21 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 1.9 2.4 mω V GS = 1V, I D = 75A e V GS(th) Gate Threshold Voltage 2. 4. V V DS = V GS, I D = 15µA gfs Forward Transconductance 12 S V DS = 1V, I D = 75A I DSS Drain-to-Source Leakage Current 2 µa V DS = 3V, V GS = V 25 V DS = 3V, V GS = V, T J = 125 C I GSS Gate-to-Source Forward Leakage 2 na V GS = 2V Gate-to-Source Reverse Leakage -2 V GS = -2V Q g Total Gate Charge 16 24 I D = 75A Q gs Gate-to-Source Charge 51 nc V DS = 24V Q gd Gate-to-Drain ("Miller") Charge 58 V GS = 1V e t d(on) Turn-On Delay Time 24 V DD = 15V t r Rise Time 1 I D = 75A t d(off) Turn-Off Delay Time 48 ns R G = 3.2 Ω t f Fall Time 37 V GS = 1V e L D Internal Drain Inductance 4.5 Between lead, nh 6mm (.25in.) L S Internal Source Inductance 7.5 from package and center of die contact V GS = V V DS = 25V C iss Input Capacitance 632 C oss Output Capacitance 198 C rss Reverse Transfer Capacitance 11 pf C oss Output Capacitance 593 C oss Output Capacitance 21 C oss eff. Effective Output Capacitance 35 ƒ = 1.MHz V GS = V, V DS = 1.V, ƒ = 1.MHz V GS = V, V DS = 24V, ƒ = 1.MHz V GS = V, V DS = V to 24V f Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 75 MOSFET symbol (Body Diode) A showing the I SM Pulsed Source Current 12 integral reverse (Body Diode)Ãc p-n junction diode. V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 75A, V GS = V e t rr Reverse Recovery Time 34 51 ns T J = 25 C, I F = 75A, V DD = 15V Q rr Reverse Recovery Charge 29 44 nc di/dt = 1A/µs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) Notes: Repetitive rating; pulse width limited by max. junction Limited by T Jmax, see Fig.12a, 12b, 15, 16 for typical temperature. (See fig. 11). repetitive avalanche performance. Limited by T Jmax, starting T J = 25 C, L =.1mH R G = 25Ω, This value determined from sample failure population. 1% I AS = 75A, V GS =1V. Part not recommended for use above tested to this value in production. this value. This is only applied to TO-22AB pakcage. ƒ Pulse width 1.ms; duty cycle 2%. ˆ R C oss eff. is a fixed capacitance that gives the same charging time θ is measured at T J approximately 9 C as C oss while V DS is rising from to 8% V DSS. 2 www.irf.com
I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) Gfs, Forward Transconductance (S) 1 1 VGS TOP 15V 1V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V 1 VGS TOP 15V 1V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V 1 1 1 4.5V 6µs PULSE WIDTH Tj = 25 C.1 1 1 1 1 V DS, Drain-to-Source Voltage (V) 4.5V 6µs PULSE WIDTH Tj = 175 C 1.1 1 1 1 1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1. 24 T J = 25 C 1. T J = 175 C 2 16 T J = 175 C 1. 12 1. T J = 25 C 8 V DS = 25V 6µs PULSE WIDTH.1 2. 3. 4. 5. 6. 7. 8. 9. 1. V GS, Gate-to-Source Voltage (V) 4 V DS = 1V 38µs PULSE WIDTH 2 4 6 8 1 12 14 16 18 I D, Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance Vs. Drain Current www.irf.com 3
I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) 12 1 V GS = V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 2 16 I D = 75A V DS = 24V VDS= 15V 8 Ciss 12 6 8 4 2 Coss Crss 4 1 1 1 V DS, Drain-to-Source Voltage (V) 4 8 12 16 2 24 Q G Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1. 1. T J = 175 C 1 1 1 OPERATION IN THIS AREA LIMITED BY R DS (on) 1msec 1µsec 1. T J = 25 C 1 LIMITED BY PACKAGE 1msec 1. V GS = V.1..4.8 1.2 1.6 2. 2.4 V SD, Source-to-Drain Voltage (V) DC 1 Tc = 25 C Tj = 175 C Single Pulse.1.1 1. 1. 1. V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
I D, Drain Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) 3 25 LIMITED BY PACKAGE 2. I D = 75A V GS = 1V 2 1.5 15 1 1. 5 25 5 75 1 125 15 175 T C, Case Temperature ( C).5-6 -4-2 2 4 6 8 1 12 14 16 18 T J, Junction Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig 1. Normalized On-Resistance Vs. Temperature 1 Thermal Response ( Z thjc ) D =.5.1.1.2.1.5.2.1 R 1 R 1 R 2 R 2 R 3 R 3 τ J τ J τ 1 τ 1 τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i/ri τ C τ Ri ( C/W) τi (sec).8133.44.248.971.18658.8723.1 SINGLE PULSE ( THERMAL RESPONSE ) 1E-6 1E-5.1.1.1.1 t 1, Rectangular Pulse Duration (sec) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc Tc Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
V GS(th) Gate threshold Voltage (V) E AS, Single Pulse Avalanche Energy (mj) V DS L 15V DRIVER 12 1 I D TOP 26A 42A BOTTOM 75A 8 R G 2V V GS tp Fig 12a. Unclamped Inductive Test Circuit tp D.U.T IAS.1Ω V (BR)DSS - V DD A 6 4 2 25 5 75 1 125 15 175 Starting T J, Junction Temperature ( C) I AS Fig 12b. Unclamped Inductive Waveforms Q G Fig 12c. Maximum Avalanche Energy Vs. Drain Current 1 V V G Q GS Q GD 4.5 4. 3.5 I D = 1.A I D = 1.mA ID = 25µA I D = 15µA Current Regulator Same Type as D.U.T. Charge Fig 13a. Basic Gate Charge Waveform 3. 2.5 5KΩ 2. 12V V GS.2µF.3µF D.U.T. V - DS 1.5 1. -75-5 -25 25 5 75 1 125 15 175 3mA T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature 6 www.irf.com
Avalanche Current (A) E AR, Avalanche Energy (mj) 1 Duty Cycle = Single Pulse 1 1.1.5.1 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax 1 1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1 tav (sec) Fig 15. Typical Avalanche Current Vs.Pulsewidth 3 25 2 15 1 5 TOP Single Pulse BOTTOM 1% Duty Cycle I D = 75A 25 5 75 1 125 15 175 Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 15, 16: (For further info, see AN-15 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 15, 16). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure 11) P D (ave) = 1/2 ( 1.3 BV I av ) = DT/ Z thjc Fig 16. Maximum Avalanche Energy I av = 2DT/ [1.3 BV Z th ] Vs. Temperature E AS (AR) = P D (ave) t av www.irf.com 7
- D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =1V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs V DS R D R G V GS D.U.T. - V DD 1V Pulse Width 1 µs Duty Factor.1 % Fig 18a. Switching Time Test Circuit V DS 9% 1% V GS t d(on) t r t d(off) t f Fig 18b. Switching Time Waveforms 8 www.irf.com
TO-22AB Package Outline(Dimensions are shown in millimeters (inches)) TO-22AB Part Marking Information EXAMPLE: T HIS IS AN IRF11 LOT CODE 1789 ASSEMBLED ON WW 19, 2 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead - Free" INT ERNAT IONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR = 2 WEEK 19 LINE C TO-22AB package is not recommended for Surface Mount Application. Notes: 1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/ 2. For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (31) 252-715 TAC Fax: (31) 252-793 Visit us at www.irf.com for sales contact information. 7/21 www.irf.com 9