Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use l Lead-Free Benefits PD - 95072A IRFR3709ZPbF IRFU3709ZPbF HEXFET Power MOSFET V DSS R DS(on) max Qg 30V 6.5m: 7nC l l l Very Low R DS(on) at 4.5V V GS Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current D-Pak IRFR3709ZPbF I-Pak IRFU3709ZPbF Absolute Maximum Ratings Parameter Max. Units V DS Drain-to-Source Voltage 30 V V GS Gate-to-Source Voltage ± 20 I D @ T C = 25 C Continuous Drain Current, V GS @ V 86f A I D @ T C = C Continuous Drain Current, V GS @ V 6f I DM Pulsed Drain Current c 340 P D @T C = 25 C Maximum Power Dissipation 79 W P D @T C = C Maximum Power Dissipation Linear Derating Factor 39 0.53 W/ C T J Operating Junction and -55 to 75 C T STG Storage Temperature Range Soldering Temperature, for seconds 300 (.6mm from case) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.9 C/W R θja Junction-to-Ambient (PCB Mount) g 50 R θja Junction-to-Ambient Notes through are on page www.irf.com 2/2/04
IRFR/U3709ZPbF Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions BV DSS Drain-to-Source Breakdown Voltage 30 V V GS = 0V, I D = 250µA ΒV DSS / T J Breakdown Voltage Temp. Coefficient 22 mv/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 5.2 6.5 mω V GS = V, I D = 5A e 6.5 8.2 V GS = 4.5V, I D = 2A e V GS(th) Gate Threshold Voltage.35.80 2.25 V V DS = V GS, I D = 250µA V GS(th) / T J Gate Threshold Voltage Coefficient -5.6 mv/ C I DSS Drain-to-Source Leakage Current.0 µa V DS = 24V, V GS = 0V 50 V DS = 24V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage na V GS = 20V Gate-to-Source Reverse Leakage - V GS = -20V gfs Forward Transconductance 5 S V DS = 5V, I D = 2A Q g Total Gate Charge 7 26 Q gs Pre-Vth Gate-to-Source Charge 4.7 V DS = 5V Q gs2 Post-Vth Gate-to-Source Charge.6 nc V GS = 4.5V Q gd Gate-to-Drain Charge 5.7 I D = 2A Q godr Gate Charge Overdrive 5.0 See Fig. 6 Q sw Switch Charge (Q gs2 Q gd ) 7.3 Q oss Output Charge nc V DS = 6V, V GS = 0V t d(on) Turn-On Delay Time 2 V DD = 6V, V GS = 4.5V e t r Rise Time 2 I D = 2A t d(off) Turn-Off Delay Time 5 ns Clamped Inductive Load t f Fall Time 3.9 C iss Input Capacitance 2330 V GS = 0V C oss Output Capacitance 460 pf V DS = 5V C rss Reverse Transfer Capacitance 230 ƒ =.0MHz Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd mj I AR Avalanche Currentc 2 A E AR Repetitive Avalanche Energy c 7.9 mj Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 86f Conditions MOSFET symbol D (Body Diode) A showing the I SM Pulsed Source Current 340 integral reverse G S (Body Diode)c p-n junction diode. V SD Diode Forward Voltage.0 V T J = 25 C, I S = 2A, V GS = 0V e t rr Reverse Recovery Time 29 44 ns T J = 25 C, I F = 2A, V DD = 5V Q rr Reverse Recovery Charge 25 37 nc di/dt = A/µs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) 2 www.irf.com
I D, Drain-to-Source Current (Α) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRFR/U3709ZPbF 00 0 VGS TOP V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V BOTTOM 2.25V 00 0 VGS TOP V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V BOTTOM 2.25V 0. 0.0 2.25V 20µs PULSE WIDTH Tj = 25 C 0. V DS, Drain-to-Source Voltage (V) 0. 2.25V 20µs PULSE WIDTH Tj = 75 C 0. V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 0 2.0 I D = 30A V GS = V.5 T J = 75 C 0. T J = 25 C V DS = 5V 20µs PULSE WIDTH 0 2 3 4 5 6 7 8 V GS, Gate-to-Source Voltage (V).0 0.5-60 -40-20 0 20 40 60 80 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature www.irf.com 3
I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) IRFR/U3709ZPbF 000 00 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 6.0 5.0 I D = 2A V DS = 24V V DS = 5V C iss 4.0 0 C oss 3.0 C rss 2.0.0 V DS, Drain-to-Source Voltage (V) 0.0 0 5 5 20 25 Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 0 0 OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 75 C T J = 25 C V GS = 0V 0 0.0 0.5.0.5 2.0 2.5 V SD, Source-to-Drain Voltage (V) Tc = 25 C Tj = 75 C Single Pulse µsec msec msec 0 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
I D, Drain Current (A) V GS(th) Gate threshold Voltage (V) IRFR/U3709ZPbF 90 80 Limited By Package 2.5 2.0 70 60 50 40.5.0 I D = 250µA 30 20 0 25 50 75 25 50 75 T C, Case Temperature ( C) 0.5 0.0-75 -50-25 0 25 50 75 25 50 75 T J, Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Threshold Voltage vs. Temperature D = 0.50 Thermal Response ( Z thjc ) 0. 0.0 0.00 0.20 0. 0.05 0.02 0.0 R R 2 R 3 R R 2 R 3 τ J τ J τ τ τ 2 τ 3 τ 2 τ 3 Ci= τi/ri Ci= τi/ri SINGLE PULSE ( THERMAL RESPONSE ) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc E-006 E-005 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) τ C τ Ri ( C/W) τi (sec) 0.8 0.000260 0.640 0.00697 0.45 0.02259 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
E AS, Single Pulse Avalanche Energy (mj) IRFR/U3709ZPbF 5V 450 R G V DS 20V V GS tp L D.U.T IAS 0.0Ω DRIVER - V DD A 400 350 300 250 200 I D TOP 6.6A 8.4A BOTTOM 2A Fig 2a. Unclamped Inductive Test Circuit 50 tp V (BR)DSS 50 0 25 50 75 25 50 75 Starting T J, Junction Temperature ( C) Fig 2c. Maximum Avalanche Energy vs. Drain Current I AS Fig 2b. Unclamped Inductive Waveforms V DS L D V DD - Current Regulator Same Type as D.U.T. 50KΩ V GS Pulse Width < µs Duty Factor < 0.% D.U.T 2V.2µF.3µF D.U.T. V - DS Fig 4a. Switching Time Test Circuit V DS 90% V GS 3mA I G I D Current Sampling Resistors % V GS Fig 3. Gate Charge Test Circuit t d(on) t r t d(off) t f Fig 4b. Switching Time Waveforms 6 www.irf.com
IRFR/U3709ZPbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 5. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Vds Id Vgs Vgs(th) Qgs Qgs2 Qgd Qgodr Fig 6. Gate Charge Waveform www.irf.com 7
IRFR/U3709ZPbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q and Q2. Power losses in the high side switch Q, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) I Q gd V in f I Q gs 2 V in f i g ( ) Q g V g f Q oss 2 V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs and Q gs2, can be seen from Fig 6. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. i g Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ( ) P loss = I rms 2 R ds(on) ( ) Q g V g f Q oss 2 V in f Q rr V in f *dissipated primarily in Q. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. As Q turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Q oss Characteristic 8 www.irf.com
IRFR/U3709ZPbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR20 WITH ASSEMBLY LOT CODE 234 ASS EMBLED ON WW 6, 999 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 96A 2 34 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 6 LINE A OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 2 34 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 999 WEEK 6 A = ASSEMBLY SITE CODE www.irf.com 9
IRFR/U3709ZPbF I-Pak (TO-25AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-25AA) Part Marking Information EXAMPLE: THIS IS AN IRFU20 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 9, 999 IN THE ASS EMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE IRFU20 99A 56 78 PART NUMBER DATE CODE YE AR 9 = 999 WEEK 9 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE IRFU20 56 78 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 999 WEEK 9 A = AS S EMBL Y S IT E CODE www.irf.com
D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) IRFR/U3709ZPbF TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA-54. 3 INCH NOTES :. OUTLINE CONFORMS TO EIA-48. 6 mm Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L =.4mH, R G = 25Ω, I AS = 2A. ƒ Pulse width 400µs; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. When mounted on " square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information. 2/04 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/