AND7/D NIS Better ORing Diode Operation Notes Prepared by: Ryan Liu ON Semiconductor APPLICATION NOTE eneral Description The NIS is a simple and reliable device consisting of an integrated control IC with a low R DS(on) power MOSFET, using hybrid technology. It is designed to replace Schottky diodes in ORing applications to obtain higher system power efficiency. It can be connected to allow load sharing with automatic switchover of the load between two or more input power supplies. A single NIS is able to run up to 0 A without any air flow. To meet high current requirement ( i.e. 0 A), the NIS is designed to drive more than four paralleled additional NTD0N0 MOSFETs. The unique package design of NIS offers higher thermal efficiency to minimize cooling requirements. This application note presents more details of the 0 A and 0 A demonstration boards. Both of them can be easily connected to power sources and loads for any test purpose. Applications Paralleled N Redundant Power Supplies Telecommunications Power Systems High Reliability, Distributed Power Networks NIS Simplified Block Diagram (Pin ): Input pin for internal voltage regulator. Bias (Pin ): Output of internal voltage regulator. It is.0 V under normal operating conditions. It provides power for internal components only. No external connections are necessary at this pin. ate (Pin ): ate driver output for internal and external N Channel MOSFET. The gate turn on time is typically ns. Source (Pin ): Power input, connected to the system power source output. This is the anode of the rectifier. Drain (Pin ): Power output, connected to the system load. This pin is the cathode of the rectifier and will be common to the cathodes of the other rectifiers, when used in a high side configuration. UVLO Function: The UVLO is set for a trip point of. V rising and. V falling of the bias supply. Before the bias voltage reaches. V, the UVLO disables the gate driver. As soon as the bias voltage reaches. V or more, the UVLO enables the gate driver. Bias ate Drain Voltage Regulator V UVLO mv D S MOSFET NTD0N0 Figure. Source Semiconductor Components Industries, LLC, 00 September, 00 Rev. Publication Order Number: AND7/D
AND7/D UVLO V_gate. V. V Figure. 0 V, Typically 0 V T V_cap NIS Basic Operating Circuit and Sequence The BERS will function as a normal silicon rectifier if there is no bias power applied to the. In order to achieve the full benefit of the BERS internal MOSFET, the must be more than.0 volts above the source (anode) pin. This level will disable the UVLO and supply voltage to the input regulator. S V in S Source Drain V_cap V_gate S NIS NIS0N0 (Optional) D V o T Output Load Timing Sequence: In the ORing applications, the should be energized before the forward current is applied to the BERS. This recommended procedure allows the gate drive control circuit to respond quickly to any current polarity changes. It is permissible to allow the voltage on and the input power supply (PS), V in to rise simultaneously. The may trail the V in voltage, but these methods would allow body diode conduction during the interval where is lower than V in plus the.0 threshold. This mode of operation will not damage the device as long as the power dissipation does not cause the maximum junction temperature for the NIS to be exceeded. Under no circumstance should the voltage go more negative than the pin source (anode). It is recommended that a signal diode (N) be installed in series with the pin. The number of external MOSFETs recommended in Table is based upon no airflow or heat sink other than the normal printed circuits board (PCB) installation. The test data is taken from the 0 A demonstration board. If a specific system application already provides cooling air flow or metal heatsinking, then the actual number of added MOSFETs may be decreased from the recommendation. Table. Recommended Selection of External MOSFETs Based on Load Currents Under No Air Flow and No Heat Sink Condition Recommended Selection Max Load Current Rating (A) Single NIS 0 NIS and One NTD0N0 0 NIS and Two NTD0N0 0 NIS and Three NTD0N0 0 NIS and Four NTD0N0 0 Figure. Basic Operation Circuit
AND7/D TEST CIRCUIT Lead Ceramic V_reg_in Vin_ ECAP D Source Drain V_cap ate NIS IC Jump_ L stray Output ESR R Load PS S D C Filter Ceramic NTD0N0 N =,,,... ECAP ESR R snub C snub D L stray Lead Ceramic Vin_ ECAP Source Drain V_cap ate NIS IC Jump_ ESR S PS S D NTD0N0 N =,,,... R snub C snub Figure. Test Circuit Basic Test Circuit The test circuit in Figure is set to test peak reverse current and recovery time for multiple power source operation. With Vin_ > Vin_, the load current will flow through IC and its paralleled MOSFETs. After switching on S (Shut Vin_), IC and its paralleled MOSFETs will take over the power transfer path, and current will go through them instead of IC and its paralleled MOSFETs. Meanwhile, since V o > Vin_ (after shutting Vin_) a small amount of reverse current will be forced to go through IC and its MOSFETs, which will terminate the conduction of this switch. Note that in ORing applications it is probable to have an instance where the PS voltages Vin_, Vin_ iterated up to Vin_n, are higher than the power source. The signal blocking diodes must be used in series with each of the pins to protect them from reverse voltages. The high switching speed of the BERS diode makes the distributed circuit board inductance and capacitance become non trivial. The demonstration board has loops provided to monitor the currents with a suitable probe. Specific applications will have wire or PCB distribution bus inductances. The demonstration boards and specific systems have a combination of low ESR ceramic filter and some aluminum electrolytic (E cap) type capacitors. The E caps give some energy storage, but their ESRs provide the needed RLC circuit damping resistance. The type (KME, LXF, LXV) and Farad value can be selected for the optimum damping factor. The NIS and any attendant NTD0N0 s require some amount of reverse current to achieve turn off. This will generate some ½ Li energy in the stray inductance which must be dissipated. For the 0 A demonstration board with four MOSFETs, the (turn off) current will be about A. This generates about. Joule per H of stray inductance. The snubber resistors Rsnub, Rsnub and capacitors Csnub and Csnub must be applied across the BERS anode to cathode to absorb the energy and prevent undamped oscillations.
AND7/D Bias Power Circuit Notes: The ORing circuits are applied to protect power busses from an event (short circuit) that is not well controlled. As a result, the circuit must be resistant to unpredictable response of the external components. Most power supplies execute a controlled power down after the overcurrent is detected. It is possible that a failing PS would not respond predictably and may cause voltage spikes as the short circuit bounces open and closed. The BERS is a V part, and can tolerate over voltage from a to V bus. The NIS0 V CC is rated at Vdc and has an internal Zener. The boost converter NCP0 V DD is rated at.0 V, and should have a. V Zener protection diode in parallel. Both of these voltage boosters should have a current limiting resistor in series with the respective power bus voltage and their V CC or V DD for protection from PS over shoot. Using the NIS in ORing circuits The NIS is ideally suited to the ORing application as compared to the Schottky diodes, but there are subtle performance differences. Application note AND9/D describes the reverse current required to switch off the NIS. The reverse current will be provided by the applications failing PS, as required by the power bus ORing design. The BERifference: The obvious advantage of the BERS over Schottky diodes is the low loss, highly conductive switch path that it provides. The incredibly low R DS(on) of m creates an interesting situation. The benefit of low thermal loss is obvious. The side effect of the highly conductive channel is that relatively large currents can flow in either direction with an extremely small driving voltage. There is no barrier voltage or other effect that would give a zero current condition the ability to switch the state of the device. The ON Semiconductor NIS has a very sensitive comparator carefully placed near the FET. Yet it still requires about one amp of reverse current to generate sufficient offset voltage that can reset the device to its off state. The Schottky, or any other diode device which has a junction, also has a barrier voltage that must be overcome before current will flow. As the forward current in a Schottky diode falls and approaches zero, the diode forward voltage collapses to zero and effectively shuts off the conduction channel. Why Use ORing Diodes At All? ORing diodes are costly and they waste power. It is true that multiple power supplies will work if the outputs are just wired together in parallel. Two volt AC/DC power supplies taken off the shelf and wired together in parallel will give five volts output when they are both powered up, but they may not share the load very well. The one with the highest set point will provide almost all the current. But if one of them is powered off, the other will supply the entire load current. It will also bias up the output filter capacitor of the first (off) power supply. The ORing diodes are used for one single purpose; to protect the system power bus. If one of the power supplies has a failure in the output rectifier or filter capacitors that causes it to short circuit, then the ORing diode protects the system bus from being shorted. The ORing diode will also prevent the system bus from dumping a charge current into a powered down supply that is installed while the system is still on. This function is more the business of a hot swap controller, but it also works with ORing diodes. The ORing system works best if the design has forced current sharing to get the greatest PS utilization. ORing does not protect the individual power supplies from catastrophic failures. Be aware of Schottky specific design constraints: Schottky has been used for ORing for some time. The design and test specifications used in ORing applications may have included the non ORing, junction diode properties for validation. Schottky ORing diode characteristic of zero current switch off may be an expected parameter even though this feature is not important for the function of PS ORing. Test procedures may use individual power supply de activation by method of power down or forced OVP, then the voltage of that PS is verified to be zero. This test method does not validate an ORing function, but it is easier and quicker to perform. The proper test method for ORing diode requires that the test unit power supply must be shorted or have an output current over load (OCP) applied. The proper test method for hot swap must have the system powered up and functional with the test PS previously removed from the system. It must be cold or have no voltage on its output terminals. The input power to the test unit PS must be off at the start of the test and must remain off for the full length of the test. The test must begin with the insertion or connection of the cold power supply in the system. If the cold PS output stays near zero volts, the ORing diode passes the test. If the cold PS output is forced to some voltage higher than 0. volts, the diode fails the test.
AND7/D OVP Detection Notes: In some cases, the overvoltage protection (OVP) may be forced during test to validate that the OVP of an individual PS is functional at the end item test level. This test may also validate that the forced OVP results in a shut down and detection for that particular supply. In most operating current ranges, the BERS will probably have a slightly higher positive ratio of dynamic impedance than the Schottky diode. Therefore the test PS will reach its OVP threshold then shut down before the bus exceeds the upper voltage limit. However, the power supply which shuts down will not sink enough reverse current to switch off the BERS ORing diode. The OVP disabled PS will stop driving current so the system bus does not OVP, but it also is not supplying power even though the outputs may be floating in the range of normal bus voltage. For good design practice, the system designer must use the OVP detection and not depend solely upon the power supply output voltage as a means of detecting power supply failures. Another OVP design problem that may be found in ORing systems with forced current sharing is that as one of the power supplies starts to over voltage, it drives up the power bus voltage. The current sharing method would cause all power supplies in the system to raise their voltages together. Each of the power supplies has an OVP threshold that will not be identical to the others. Two or more power supplies could reach their separate OVP limits and shut down in sequence. Only one of the power supplies had the control loop fault yet it can cause the chain reaction of multiple PS shut downs.
AND7/D 0 A DEMONSTRATION BOARD V_reg_in_ D N Vin_ J Source Drain C C C V_cap ate ND * IC NIS C C C R C. 0. F D R C7.0 F/ 0 V D BASLT C 0. F/ 0 V D BASLT BASLT V CC PWRND COMP PWRND V RE SIND 7 DRIVE PWRND IC NIS0 R R k C 0. F/0 V.0 k C 0. F M NTD0N0 V_reg_in_. D J J C C * C C9 C7 C0 M NTD0N0 C C9 * C C N Vin_ J Source Drain C C C V_cap ate ND * IC NIS C7 C C9 R C. 0. F D R C0 C Charge Pump Circuit (Optional) * Vdc, 00 to 00 F Aluminum Electrolytic Capacitor, Low ESR Type LXV or equivalent. C.0 F/ 0 V D BASLT C 0. F/ 0 V D7 BASLT BASLT V CC PWRND COMP PWRND V RE SIND 7 DRIVE PWRND IC NIS0 C0 0. F. J R k C R7.0 k Charge Pump Circuit (Optional) 0. F/0 V V O ND Figure. 0 A Demonstration Board Schematic
AND7/D 0 A DEMONSTRATION BOARD (continued) NOTE: The selection of input and output capacitors vary, based on the PCB layout and the maximum load in the applications. Figure. Figure 7. Top PCB Layout Figure. Bottom PCB Layout 7
AND7/D 0 A DEMONSTRATION BOARD (continued) Table and Figure 9 present the current sharing data at different load conditions. Table. Current Sharing Test Results Current Sharing Rating (A) Load Current NIS NTD0N0.0. 0.9.0.7. 0...0 7.0 0 0. 9. 0 CURRENT RATIN (A) 0 NIS NTD0N0 0 0 0 0 0 LOAD CURRENT (A) Figure 9. Current Sharing vs. Load Current Table. Thermal Test Results Under No Air Flow and No Heat Sink Condition Load Current (A) Thermal Data NIS Max Temp ( C) NTDN0 Max Temp ( C) 0 7 Reverse Current and Recovery Time Test Results Figure 0 shows the waveforms at a typical load condition (0 A). The reverse current is. A, the recovery time is 0 ns. In Figure 0, the slope (di/dt) of the waveform (Ch) is a function of the parasitic inductance and capacitance of the system. With increasing the current path length and the component spaces on the PCB, decreasing the slope (di/dt). Ch: ate Voltage of NIS (0 V/DIV) Ch: Output Voltage (0 V/DIV) Ch: Current Through NIS (.0 A/DIV) Figure 0.
AND7/D 0 A DEMONSTRATION BOARD V O ND D V_reg_in_ B C7 0. F N L L L L L L C9 V_reg_in_ C C C C * C0 C C C IC0 Source Drain V_cap ate Vin_ ND D N C0 C0 C07 C0 * C0 C0 C0 C0 C0 D0 C.0 F/ 0 V D0 BASLT V CC BASLT COMP DRIVE PWRND PWRND D0 BASLT C9 0. F/ 0 V V RE SIND PWRND 7 IC0 NIS0 R0 k R07 k C 0. F/0 V Charge Pump Circuit (Optional) C7 0. F NIS R0. C 0. F R0.0 NTD0N0 M0 R0.0 NTD0N0 M0 R0.0 NTD0N0 M0 R0.0 NTD0N0 M0 L0 L0 L0 L0 L0 L0 C09 C * C0 C C C C Source Drain V_cap ate Vin_ C C C C7 C C NIS R. C 0. F * ND C C C C C R.0 D M NTD0N0 R BASLT D BASLT.0 M NTD0N0 R IC NIS0 C.0 F/ 0 V PWRND V CC PWRND COMP D BASLT SIND V RE.0 PWRND DRIVE C9 0. F/ 0 V 7 M NTD0N0 R Figure. 0 A Demonstration Board Schematic R k R7 k.0 C 0. F/0 V M NTD0N0 Charge Pump Circuit (Optional) * Vdc, 00 to 00 F Aluminum Electrolytic Capacitor, Low ESR Type LXV or equivalent. 9
AND7/D 0 A DEMONSTRATION BOARD (continued) Figure. Figure. Top PCB Layout Figure. Bottom PCB Layout 0
AND7/D 0 A DEMONSTRATION BOARD (continued) Table and Figure present the current sharing data at different load conditions. Table. Current Sharing Test Results Current Sharing Ratings (A) Io (A) NIS M0 M0 M0.0.... 0.....0... 0....0...0.0 0. 7. 7.0 7. 9.... 0 9.7 9. 9.. 0. 0. 0... CURRENT RATIN (A) NTD0N0 (M0) 0 NTD0N0 (M0) NIS NTD0N0 (M0) NTD0N0 (M0) 0 0 0 0 0 0 0 0 70 LOAD CURRENT (A) Figure. Current Sharing vs. Load Currents Table. Thermal Test Results Under No Air Flow and No Heat Sink Condition Devices Max Load Current Rating (A) Max Thermal Rating Typical Single NIS 0 NIS and One NTD0N0 0 7 NIS and Two NTD0N0 0 NIS and Three NTD0N0 0 NIS and Four NTD0N0 0 Reverse Current and Recovery Time Test Results Figure presents the waveforms at a typical load condition (0 A). The reverse current is. A, the recovery time is 0 ns. Conclusion The application note describes the NIS device operation and the details of 0 A and 0 A demonstration boards. Ch: ate Voltage of NIS (0 V/DIV) Ch: Output Voltage (0 V/DIV) Ch: Output Current (.0 A/DIV) Figure.
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