D 2 Pak TO

Logic-Leve Gate Drive dvanced Process Technoogy Surface Mount (IRLZ34NS) Low-profie through-hoe (IRLZ34NL) 75 C Operating Temperature Fast Switching Fuy vaanche Rated Lead-Free Description PD - 95583 IRLZ34NSPbF IRLZ34NLPbF HEXFET Power MOSFET V DSS = 55V R DS(on) = 0.035Ω I D = 30 Fifth Generation HEXFETs from Internationa Rectifier utiize advanced processing techniques to achieve extremey ow on-resistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are we known for, provides the designer with an extremey efficient and reiabe device for use in a wide variety of appications. The D 2 Pak is a surface mount power package capabe of accommodating die sizes up to HEX-4. It provides the highest power capabiity and the owest possibe onresistance in any existing surface mount package. The D 2 Pak is suitabe for high current appications because of its ow interna connection resistance and can dissipate up to 2.0W in a typica surface mount appication. The through-hoe version (IRLZ34NL) is avaiabe for owprofie appications. D 2 Pak TO-262 bsoute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 30 I D @ T C = 0 C Continuous Drain Current, V GS @ V 2 I DM Pused Drain Current P D @T = 25 C Power Dissipation 3.8 W P D @T C = 25 C Power Dissipation 68 W Linear Derating Factor 0.45 W/ C V GS Gate-to-Source Votage ±6 V E S Singe Puse vaanche Energy mj I R vaanche Current 6 E R Repetitive vaanche Energy 6.8 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range Sodering Temperature, for seconds 300 (.6mm from case ) C Therma Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 2.2 R θj Junction-to-mbient ( PCB Mounted,steady-state)** 40 C/W www.irf.com 07/20/04 G D S

Eectrica Characteristics @ T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 55 V V GS = 0V, I D = 250µ V (BR)DSS / T J Breakdown Votage Temp. Coefficient 0.065 V/ C Reference to 25 C, I D = m 0.035 V GS = V, I D = 6 R DS(on) Static Drain-to-Source On-Resistance 0.046 Ω V GS = 5.0V, I D = 6 0.060 V GS = 4.0V, I D = 4 V GS(th) Gate Threshod Votage.0 2.0 V V DS = V GS, I D = 250µ g fs Forward Transconductance S V DS = 25V, I D = 6 I DSS Drain-to-Source Leakage Current 25 V DS = 55V, V GS = 0V µ 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 V GS = 6V n Gate-to-Source Reverse Leakage -0 V GS = -6V Q g Tota Gate Charge 25 I D = 6 Q gs Gate-to-Source Charge 5.2 nc V DS = 44V Q gd Gate-to-Drain ("Mier") Charge 4 V GS = 5.0V, See Fig. 6 and 3 t d(on) Turn-On Deay Time 8.9 V DD = 28V t r Rise Time 0 I D = 6 ns t d(off) Turn-Off Deay Time 2 R G = 6.5Ω, V GS = 5.0V t f Fa Time 29 R D =.8Ω, See Fig. L S Interna Source Inductance 7.5 nh Between ead, and center of die contact C iss Input Capacitance 880 V GS = 0V C oss Output Capacitance 220 pf V DS = 25V C rss Reverse Transfer Capacitance 94 ƒ =.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 30 (Body Diode) showing the G I SM Pused Source Current integra reverse (Body Diode) p-n junction diode. S V SD Diode Forward Votage.3 V T J = 25 C, I S = 6, V GS = 0V t rr Reverse Recovery Time 76 ns T J = 25 C, I F = 6 Q rr Reverse Recovery Charge 90 290 nc di/dt = 0/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. ( See fig. ) V DD = 25V, starting T J = 25 C, L =6µH R G = 25Ω, I S = 6. (See Figure 2) ƒ I SD 6, di/dt 270/µs, V DD V (BR)DSS, T J 75 C Puse width 300µs; duty cyce 2%. Uses IRLZ34N data and test conditions ** When mounted on " square PCB ( FR-4 or G- Materia ). For recommended footprint and sodering techniques refer to appication note #N-994. 2 www.irf.com

I D, Drain-to-Source Current () 00 0 VGS TOP 5V 2V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V I D, Drain-to-Source Current () 00 0 VGS TOP 5V 2V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH 0. T J = 25 C 0. 0 V DS, Drain-to-Source Votage (V) 20µs PULSE WIDTH 0. T J = 75 C 0. 0 V DS, Drain-to-Source Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, Drain-to-Source Current () 00 0 T = 25 C J T = 75 C J V DS= 25V 20µs PULSE WIDTH 0. 2 3 4 5 6 7 8 9 V GS, Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) 3.0 2.5 2.0.5.0 0.5 I D = 27 V GS = V 0.0-60 -40-20 0 20 40 60 80 0 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized On-Resistance Vs. Temperature www.irf.com 3

C, Capacitance (pf) 400 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED 200 C rss = Cgd C iss C oss = C ds Cgd 00 800 C oss 600 400 Crss 200 0 0 V DS, Drain-to-Source Votage (V) V GS, Gate-to-Source Votage (V) 5 2 9 6 3 0 I D = 6 V DS = 44V V DS = 28V FOR TEST CIRCUIT SEE FIGURE 3 0 4 8 2 6 20 24 28 32 Q, Tota Gate Charge (nc) G Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage I SD, Reverse Drain Current () 00 0 T = 75 C J T = 25 C J V GS = 0V 0.4 0.6 0.8.0.2.4.6.8 2.0 V SD, Source-to-Drain Votage (V) I D, Drain Current () 00 OPERTION IN THIS RE LIMITED BY RDS(on) 0 µs 0µs ms T C = 25 C T J = 75 C ms Singe Puse 0 V DS, Drain-to-Source Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating rea 4 www.irf.com

40 V DS R D I D, Drain Current () 30 20 Fig a. Switching Time Test Circuit V DS 90% R G V GS 5.0V Puse Width µs Duty Factor 0. % D.U.T. -VDD 0 25 50 75 0 25 50 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Therma Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERML RESPONSE) Notes:. Duty factor D = t / t 2 0.0 2. Peak T J= P DM x Z thjc TC 0.0000 0.000 0.00 0.0 0. t, Rectanguar Puse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Therma Impedance, Junction-to-Case www.irf.com 5

L V DS D.U.T. R G V - DD 5.0 V I S t p 0.0Ω Fig 2a. Uncamped Inductive Test Circuit V (BR)DSS t p V DD V DS E S, Singe Puse vaanche Energy (mj) 250 200 50 0 50 I D TOP 6.6 BOTTOM 6 V DD = 25V 0 25 50 75 0 25 50 75 Starting T J, Junction Temperature ( C) Fig 2c. Maximum vaanche Energy Vs. Drain Current I S Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF 5.0 V Q GS Q GD D.U.T. V - DS V GS V G 3m Charge I G I D Current Samping Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 6 www.irf.com

Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-ppied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 4. For N-Channe HEXFETS www.irf.com 7

D 2 Pak Package Outine Dimensions are shown in miimeters (inches) D 2 Pak Part Marking Information T HIS IS N IRF 530S WIT H L OT CODE 8024 SSEMBLED ON WW 02, 2000 IN THE SSEMBLY LINE "L" Note: "P" in as semby ine pos ition indicates "L ead-f ree" OR INTERNT IONL RECTIFIER LOGO SSEMBLY LOT CODE F530S PRT NUMBER DT E CODE YER 0 = 2000 WEEK 02 LINE L INT E RNT IONL RE CT IF IE R LOGO S S E MB LY LOT CODE F530S PRT NUMBER DTE CODE P = DESIGNTES LED-FREE PRODUCT (OPTIONL) YER 0 = 2000 WEEK 02 = SSEMBLY SITE CODE 8 www.irf.com

TO-262 Package Outine Dimensions are shown in miimeters (inches) TO-262 Part Marking Information EXMPLE: THIS IS N IRL33L LOT CODE 789 S SEMBLED ON WW 9, 997 IN THE SSEMBLY LINE "C" Note: "P" in assemby ine position indicates "Lead-Free" OR INTERNTIONL RECTIFIER LOGO S S E MB L Y LOT CODE PRT NUMBER DT E CODE YE R 7 = 997 WEEK 9 LINE C INTERNTIONL RECTIFIER LOGO S S EMBLY LOT CODE PRT NUMBER DTE CODE P = DESIGNTES LED-FREE PRODUCT (OPTIONL) YER 7 = 997 WEEK 9 = SSEMBLY SITE CODE www.irf.com 9

D 2 Pak Tape & Ree Information Dimensions are shown in miimeters (inches) TRR.60 (.063).50 (.059) 4. (.6) 3.90 (.53).60 (.063).50 (.059) 0.368 (.045) 0.342 (.035) FEED DIRECTION TRL.85 (.073).65 (.065).90 (.429).70 (.42).60 (.457).40 (.449) 6. (.634) 5.90 (.626).75 (.069).25 (.049) 5.42 (.609) 5.22 (.60) 24.30 (.957) 23.90 (.94) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.50 (.532) 2.80 (.504) 27.40 (.079) 23.90 (.94) 4 330.00 (4.73) MX. 60.00 (2.362) MIN. NOTES :. COMFORMS TO EI-48. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MESURED @ HUB. 4. INCLUDES FLNGE DISTORTION @ OUTER EDGE. 26.40 (.039) 24.40 (.96) 3 30.40 (.97) MX. 4 Data and specifications subject to change without notice. IR WORLD HEDQURTERS: 233 Kansas St., E Segundo, Caifornia 90245, US Te: (3) 252-75 TC Fax: (3) 252-7903 Visit us at www.irf.com for saes contact information. 07/04 www.irf.com

Note: For the most current drawings pease refer to the IR website at: http://www.irf.com/package/