Next Generation Wireless Communication System - Cognitive System and High Speed Wireless - Yoshikazu Miyanaga Distinguished Lecturer, IEEE Circuits and Systems Society Hokkaido University Laboratory of Information Communication Networks Graduate School of Information Science and Technology Sapporo 060-0814, Hokkaido Japan
Key Technologies OFDM (Orthogonal Frequency Division Multiplexing) Wireless LAN 54MBPS (IEEE 802.11a,.11g) 300MBPS 600MBPS (IEEE 802.11n) Digital TV broadcasting WiMAX Next Generation Mobile Phone 3G LTE (super 3G, - 2010 in JP), 4G ( - 2015 in JP) MIMO (Multiple Input Multiple Output Communication Channels ) Wireless LAN 300MBPS 600MBPS (IEEE 802.11n) Over 1GBPS (IEEE802.11ac) Advanced WiMAX Next Generation Mobile Phone 2
channel A/D D/A S/P Basic OFDM System Mapping Input Data P/S Guard Interval IFFT S/P Delete GI Demapping Output Data FFT Equalizer P/S
Basic OFDM System 512 1024 p FFT within several nano second Coder: cov, blk Input Data Mapping S/P IFFT Guard Interval P/S D/A Low Power Design channel De-Coder: Viterbi, LDPC Output Data Demapping P/S Equalizer FFT Delete GI S/P A/D 512 1024 p FFT within several nano second
MIMO System Transmitter Receiver TX Encoder Encoder Mapper Mapper IFFT IFFT FFT FFT MIMO Detector De-Mapper De-Mapper Decoder Decoder RX
MIMO Decoding Circuit The mode when the receiver gets the training symbols The estimation of channel and the inverse matrix calculation should be completed. The mode when the receiver gets data symbols MIMO decoding should be applied. from FFT A, Β Channel Estimation H y (from 1st and 2nd training symbols) MIMO Detector G s Inverse Matrix G = 1 Η Memory
MIMO Decoding Circuit High speed & Low power. from FFT A, Β H (from 1st and 2nd training symbols) G = 1 Η y Channel Estimation Low Power Design Inverse Matrix Memory MIMO Detector G s Matrix Inversion within several nano second
Low Power Consumption Design Smaller number of Gates Switching power reduction Leak current reduction Parallel/Pipelined Calculation Lower Clock Rate Power Control Gated clock Dynamic Power Suspension of Module Block 8
and MORE Lower Voltage Input Supply Sub-threshold design Dynamic voltage control New Algorithm Design Lower calculation cost Complete Parallel/Pipelined Processing New Architecture Design Dynamic Architecture 9
COGNITIVE RADIO SYSTEM FOR THE NEXT GENERATION WIRELESS NETWORK
WHAT IS COGNITIVE RADIO?!? In 2000, FCC introduced a Cognitive Radio System which used efficiently frequency bands. In 2005, IEEE 802 Committee introduced an advance system, i.e., a cognitive radio system, in which an occupied frequency band is automatically selected and dynamically changed.
Conventional Radio Mode All available frequency bands are fixed. Accordingly, the frequency band possibly used for the system has been assigned as a prior information. time : t1 time : t2 time : t3 ch1 ch2 ch3 A B C A C B Freq. ch1 for system A ch2 for system B ch3 for system C time : t4 A B C FCC reports over 80% bands are not used at the specific location and time.
Cognitive Radio Mode The system finds out the available bands and then select some of suitable bands dynamically by itself. time : t1 ch1 ch2 ch3 A B C Freq. System A and B are conventional radio. System C is a cognitive radio. time : t2 A C ch1 for system A time : t3 C B C ch2 for system B time : t4 A B C ch3 for system C
Cognitive Radio Mode It changes the frequency bandwidths depending on communication environment. The resources of frequency bands are fully and optimally used. It has many communication modes. The high throughput is usually kept. The complexity of a system becomes high compared to a fixed radio system. High power-consumption and circuit size become considerably large.
Our cognitive system Our design of new cognitive system is based on MIMO-OFDM system. All parts of our system behaves as cognitive systems!!! 15
Cognitive MIMO-OFDM Con Sensor Processor MAC.11a OFDM 2x2 MIMO 300M OFDM.11n OFDM 450M VHT OFDM 4x2 MIMO 4x4 MIMO 8x4 MIMO RF
Cognitive MIMO-OFDM Intelligent Sensor is designed. A sensor tries to find out the information of current communication environment. Con Sensor Processor MAC The AI controller.11a OFDM determines 2x2 MIMO the optimum communication mode Cognitive OFDM 4x2 MIMO with suitable parameters in which lowest BER/PER can be designed..11n OFDM 4x4 MIMO From its decision, a specific mode and a RF アンテナ suitable 450M 1.8G New band OFDM are 8x4 selected MIMO automatically.
Cognitive MIMO-OFDM Con Sensor Processor MAC.11a OFDM 2x2 MIMO 300M OFDM.11n OFDM 450M VHT OFDM 4x2 MIMO 4x4 MIMO 8x4 MIMO RF
Cognitive MIMO-OFDM Con Cognitive MIMO-OFDM is designed. Its features are given as follows 20~100MHz band is determined dynamically. Minimum PER can be achieved. MAC The optimum throughput is selected among Sensor Processor 54M~1.8Gbps..11a OFDM 2x2 MIMO 300M OFDM.11n OFDM 450M VHT OFDM 4x2 MIMO 4x4 MIMO 8x4 MIMO RF
Modes in Cognitive MIMO-OFDM HU-VHT
Number of Butterfly Blocks HU-VHT
Required data paths for all FFTs Array of Butterfly blocks
Evaluation Hardware description language Logic synthesis Clock frequency technology Verilog HDL Design Analyzer 100MHz 90nmCMOS
Evaluation(consumption power) System FFT Conventional Proposed length (mw) (mw) 802.11a/n SISO 128 10.3 10.4 802.11n SISO 128 16.1 16.2 256 24.3 24.5 IEEE802.16e 512 38.1 38.2 SISO 1024 63.4 63.8 802.11n 4x4 MIMO 64 40.7 41.3 802.11n 2x3 MIMO 128 48.0 48.5 HU-VHT 2x2 MIMO 512 75.8 76.1 Conventional means each power consumption is given from a corresponding sub-module only. It does not means the power consumption of the total system.
Evaluation(circuit area) No. of gates Conventional Proposed 5.96 10 Area 1.79 1.16 5 3.87 10 5 Proposed structure can reduce a circuit scale by about 35%.
HIGH SPEED WIRELESS COMMUNICATION 26
Current Trend of MIMO-OFDM Systems IEEE802.11 Standards Development by Hokkaido Univ. (Only Baseband) 3Gbps Hokkaido Univ. 8x8 MIMO-OFDM (2010) 3.0 Gbps Transmit Speed 2Gbps 1Gbps 500M bps IEEE802.11n Optional (2009) 600Mbps IEEE802.11a (2002) 54Mbps IEEE802.11ac [2012] 3.0 Gbps Hokkaido Univ. 4x4 MIMO-OFDM (2008) 1.5 Gbps IEEE802.11n Draft (2007) 300Mbps Hokkaido Univ. 2x2 MIMO-OFDM (2006) 600 Mbps Hokkaido Univ. SISO-OFDM (2005) 300 Mbps 20MHz 40MHz 60MHz 80MHz Bandwidth
FPGA Board for Evaluation Gigabit Ethernet PHY Xilinx Gigabit Ethernet MAC STARC MAC Altera STARC PHY Output
Dynamic Architecture of Low Power OFDM BB Transmitter Sensor Monitering OFDM BB Receiver Sensor OFDM BB Receiver OFDM BB Transmitter Realization of High Throughput and Low Power
Block Diagram of 4x4 MIMO-OFDM Circuit Transmitter Scrambler Encoder Interleave Mapper Pilot & Puncture Insertion Receiver Demapper IFFT Re-order & GI Insertion Viterbi Decoding Preamble Insertion Frame & Freq. Synchronization FFT Re-order & Pilot Remove MIMO Channel Est. & Decoding De-interleave & Dummy Data Insertion De-scrambler
Matrix Operations Use of 2x2 Submatrices Conjugate Symmetry in Non Diagonal Submatrices P k = H H k H k + σ 2 k I Hermitian Transpose Conjugate Symmetry P 11 P 21 P P 12 13 P 14 P24 P23 P 22 P31 P32 P 41 P 42 Complexity Reduction P P33 34 P43 P44 A = C Strassen s Matrix Multiplication and Inversion Use of Conjugate Symmetry Submatrices B D = B A H B D
Performance Comparison Reference [2] [3] [4] Proposed Matrix 2 x 2 4 x 4 4 x 4 4 x 4 Detection Algorithm ZF ZF MMSE MMSE Hardware Configuration DSP TMS3206713 ASIC 90 nm 43 k gates ASIC 0.25 µm 89 k gates ASIC 90 nm 1.86 M gates Operating Freq. 225 MHz 500 MHz 167 MHz 160 MHz Latency Time 104 x K (µs) 180 x K (ns) 600 x K (ns) 187.5 (ns) K: No. of OFDM Subcarriers [2] V. Jungnickel, A. Forck, T. Haustein, et al., 1 Gbit/s MIMO-OFDM transmission experiments,'' IEEE Vehicular Technology Conference (VTC), 2005. [3] Johan Eilert, Di Wu, and Dake Liu, Efficient complex matrix inversion for MIMO software defined radio, IEEE ISCAS, 2007. [4] A. Burg, S. Haene, D. Perels, P. Luethi, N. Felber, and W. Fichtner, Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems, IEEE ISCAS, 2006.
Available Data Speed Necessary Conditions Clock Frequency Baseband Bandwidth Processing Latency GI Duration (400 ns) Maximum Transmission Speed (Mbps) 5/6 Coding Rate 64-QAM 400-ns GI Duration Bandwidth (MHz) A 2.6-Gbps MIMO-OFDM receiver is available by the proposed MMSE detector.
4x4 MIMO-OFDM with 512 SUBCARRIERS
Design Challenge of 8x8 MIMO-OFDM Task group of IEEE802.11ac mentions use of more than four antennas. The maximum number of spatial streams is eight. 8x8 MIMO-OFDM 1.2 Gbps at 40-MHz Channel 3.0 Gbps at 80-MHz Channel 6.0 Gbps at 160-MHz Channel (Use of two transceivers) High Speed and Low-Power Architecture for 8x8 MIMO-OFDM
Current Activities in Our Project Total design of 8x8 MIMO-OFDM transceiver Integrated design for multiple data streams Real-time processing for MIMO detection Low power design by intelligent power control Prototype fabrication of wireless system Integration of baseband, RF, antenna units
Block Diagram Blocks in FFT/IFFT, Viterbi decoding, MIMO decoding are dominant in circuit scale. Transmitter Scrambler Encoder Interleave & Puncture Mapper Pilot Insertion IFFT Re-order & GI Insertion Preamble Insertion Receiver FFT Demapper Viterbi Decoding Frame & Freq. Synchronization Re-order & Pilot Remove MIMO Channel Est. &Decoding De-interleave & Dummy Data Insertion De-Scrambler
Integrated Design Duplicate design Deploy identical circuit blocks for the number of spatial data streams Increase power and area in proportion to spatial data streams Integrated design A circuit block supports multiple-input and multiple-output data paths. Reduce power and area by resource sharing FFT FFT FFT FFT FFT FFT SISO FFT processors MIMO FFT MIMO FFT processor
Multi-Path Delay FFT Processor R8MDC (Radix-8 multiple path delay communicator) Based on 8-input and 8-output butterfly units Reduction of multipliers by FFT radix-8 algorithm A 8x8 MIMO FFT processor only needs 1/3 circuit area compared with eight SISO FFT processors.
Implementation of 8x8 MIMO-OFDM Circuit performance (100MHz clock, w/o MIMO decoding) Transmitter * memory buffer included No. of logic gates Power Dissipation (mw) IFFT 573,400 91.2 Interleave* 104,000 15.0 Pilot assignment* 219,000 32.2 Others* 348,500 47.3 Total 1,244,900 185.7 Receiver No. of logic gates Power Dissipation (mw) FFT 573,700 117.0 Synchronization 24,900 2.8 Channel Estimation 19,600 1.7 Viterbi decoding 2,724,300 251.6 Deinterleave* 677,200 73.4 Others* 219,500 33.4 Total 4,239,200 479.9
MIMO Detection Strassen s algorithm Systematic matrix operation based on 2x2 matrices Extension of square matrix operations 8x8 matrix inversion 4x4 matrix inversion 8 4x4 matrix multiplication 2x2 matrix inversion 8 2x2 matrix multiplication Division of submatrices in matrix inversion
Timing Chart Received signals in frequency domain after FFT y ( t) = H s ( t) + n ( t) k Preprocessing (matrix inversion) G k k H k = ( H H + σ k k k 2 1 k I) H H k MIMO decoding s ˆ ( t) = G k k: OFDM subcarrier index t: OFDM symbol index k y k ( t)
Implementation of MIMO Detector 8x8 MIMO detection can complete within guard interval (800 ns) duration. Complete real-time processing in MIMO detection, which is tolerant of time varying fading. 8x8 Full Pipeline 4x4 Full Pipeline * Wordlength (bits) 26 20 Operating Frequency 80MHz 160MHz Total cell area (μm 2 ) 61,570,100 8,813,200 Number of logic gates 15,392,500 2,203,300 Processing Latency 780 ns 190 ns Power Consumption 1.42 W 701.2mW *Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga, ``VLSI Implementation of a Complete Pipeline MMSE Detector for a 4x4 MIMO-OFDM Receiver,'' IEICE Transactions on Fundamentals, Vol.E91-A, No.7, pp.1757-1762, July 2008.
Prototype Fabrication Wireless transceiver 2x2 MIMO-OFDM transmitter and receiver FPGA baseband units RF transceiver (5150-5250 MHz frequency band) * *Shingo Yoshizawa, Shinya Odagiri, Yasuhiro Asai, Takashi Gunji, Takashi Saito, Yoshikazu Miyanaga, ``Development and Outdoor Evaluation of an Experimental Platform in an 80-MHz Bandwidth 2x2 MIMO-OFDM System at 5.2-GHz Band,'' IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), Sep. 2010.
FPGA Board 2x2 MIMO-OFDM Transceiver 400 M samples/s by 4x over sampling MMSE and MLD algorithms in MIMO detection
Summary New Trend of Wireless Communications MIMO-OFDM 802.16 WiMAX 3G LTE (super 3G, - 2010 in JP), 4G (- 2015 in JP) LTE : Long Term Evolution 802.11ac ( over 1GBPS wireless LAN) Cognitive Wireless System Ultra High Speed Wireless System 4x4 MIMO-OFDM 8x8 MIMO-OFDM 46
Who? Yoshikazu Miyanaga He is a professor in Graduate School of Information Science and Technology, Hokkaido University. He is an associate editor of Journal of Signal Processing, RISP Japan (2005- present). He was a chair of Technical Group on Smart Info-Media System, IEICE (IEICE TG-SIS) (2004-2006) and now a member of the advisory committee, IEICE TG-SIS (2006-present). He is also vice-president, IEICE Engineering Science (ES) Society. He is a fellow member of IEICE. He is also vice-president, Asia-Pacific Signal and Information Processing Association (APSIPA). He is a distinguished lecture (DL) of IEEE CAS Society (2010-2011) and now a Board of Governor (BoG) of IEEE CAS Society (2011-present). 47