Opportunities and Challenges in Ultra Low Voltage CMOS Rajeevan Amirtharajah University of California, Davis
Opportunities for Ultra Low Voltage Battery Operated and Mobile Systems Wireless sensors RFID tags Biomedical implants Mobile Phones, internet devices, and netbooks Maximize operating lifetime for stored energy (minimum energy operation) Wall-plug and Rack Mounted Systems Power-down and sleep modes in servers Maintain state in on-chip caches, SRAM memory while minimizing leakage power Moteiv Sky mote, 26 2
Delay: TOT CMOS Delay and Power Dissipation Total Power: CΔV Δt = = I P + P + = Pdynamic + Pshort circuit = αc + V dd L V I 2 dd static f + V + V CLV I dd dd I D I dd peak leak μc static tr + t 2 f C W L P f L V ( V V ) 2 ox dd th 2 leak dd Voltage scaling decreases all power components, at expense of increasing circuit delay. 3
Low Voltage CMOS Inverter Operation Thermal noise limit: 4kT q 1 mv Inverter gain limit: 8kT q 2 mv Equalized NMOS- PMOS off currents: Swanson and Meindl, JSSC 1972 2nkT q 57 mv 4
Supply Voltage Scaling With Technology Node 1.2 3 1 25 VDD (V.8.6.4 VDD (High Perf.) 2 15 1 Length (nm.2 VDD (Low Power) 5 MPU Physical Gate Length 27 29 211 213 215 217 219 221 From 27 ITRS Roadmap Year 5
Commercial Wireless Sensor Mote Moteiv Sky mote, 26 Jiang, IPSN/SPOTS 25 Current sensor node: 7 mw all active, 17 μw idle Power sources contribute significant volume and cost Smaller system (1 cm 3 ) desirable (less obtrusive military sensor, implantable biomedical device) Reduce power consumption, get energy from environment 6
Specific Opportunities for ULV Design Extremely low power mixed-signal circuits Analog design without operational amplifiers Low voltage swing on-chip interconnects Good current drive at low V DD desirable Power gates and cutoff devices to minimize leakage power during inactive state Need steep subthreshold slope to limit leakage current when blocks turned off Low voltage active mode and sleep mode memories, caches Need reliable operation under variable V DD Low voltage standard cells Operate at minimum energy point, balancing leakage and dynamic power 7
Low Voltage Sensor Interfaces Passive Sigma Delta Modulator ADC Reza et al., IEEE Trans. Nanotechnology 25 Initial evaluation of nanowire suitability for sensors: noise and power implications (Amirtharajah et al., Int l J. Nanotechnology 28) Exploit ultra low power, low area, energy scalable ADC architecture based on passive switched capacitor modulator, digital comparator IFC Pre-Annual Review - August 13, 28 8
Energy and Voltage Scalable Sensor Interfaces Test Chip (9 nm CMOS) Measured Noise Shaping Spectrum Passive modulator Sigma Delta ADC Chip verified over range of OSRs: about 1 bits, 45 nw power consumption for 1 khz input BW Useful ENOB from V DD = 1V down to 2 mv Submitted to VLSI 29 9
Energy Scalable Array Several operations confirmed, working out configuration issues Currently testing array Test Chip Features Sixteen tiles connected by island-style x and y routing Implemented in.25 μm CMOS from TSMC Includes test structures for low switching activity interconnect Includes multiple-input energy harvesting power supply (to appear ISSCC9) 1
Edge Position Signaling Modulator Demodulator Encode multiple bits per wire transition by modulating edge timing, Pulse Position (PPM), Pulse Width (PWM) Reduces worst case power consumption over binary signaling What is circuit implementation area and power overhead? Measured data from test chip: power vs. interconnect length IFC Pre-Annual Review - August 13, 28 11
Edge Position Signaling Crossover Plot shows wire length at which power saved over binary signaling for various throughputs and minimum V DD (nominal V DD = 2.5V) Edge position signaling useful for global wires (length > 7mm) IFC Pre-Annual Review - August 13, 28 12
Frequency Variation With High Ripple / AC Supply Ring Oscillator Output 1.2 1 Volts.8.6.4 t Hold VDD Vout.2 -.2 5 1 15 2 time (ns) Self-timed datapath must be initialized at power-on Must maintain state across power supply cycles
3T DRAM Cell Layout 3T DRAM Write M2 Read M3 Store M1 46 µm 2 gate size chosen for 1.2ms retention Vdd = 4 mv C < T < 5 C Hold time for 6 Hz supply
AC Supply Test Chip Photo and Summary POR OSC FIR Filter Published Symposium on VLSI Circuits, 27 Technology Dimensions Transistors I/O V DD AC Supply (V PP = 1.8 V) Core Freq. (max) Flip-Flop DRV Power (Core) 18 nm CMOS 2.6 mm x 2.6 mm 135K 1.8 V 6 Hz 1 khz 75.6 MHz 153 mv 127 113 µw
Challenges for Ultra Low Voltage Device variability (within die, across dies, and across wafers) Variations in threshold voltage drastically affect critical circuit performance parameters Examples: I on /I off ratios, gate delays, static memory noise margins, subthreshold slope for leakage limiting devices Noise and event tolerance Approaching fundamental noise limit may decrease reliability and MTTF Limited charge storage on circuit nodes may increase susceptibility to soft errors in both memory and logic 16
Sub-V t Design Challenges RDF.3 t Leakage V OUT (V).2.1 Active.1.2.3 V (V) IN on off Sub-V t static CMOS gates exhibit variation in logic levels (V OH, V OL ) From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
Sub-V t Logic Functionality Degraded logic levels adversely impact functionality V OUT (V).3.2.1.1.2.3 V (V) IN Voltage (V).3.2.1 CLK CLK 1 2 3 Time (µs) N2,Q N3 N4 N2 CLK N3 N4 Not completely off, causing functional failure From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
Sub-V t Logic Design Functional metric necessary to manage sizing trade-off t σv t 1 WL NAND NOR V OUT-NAND, V IN-NOR.2.1 NAND NOR.1.2 V OUT-NAND, V IN-NOR.2.1 NAND NOR Logic failure.1.2 V IN-NAND, V OUT-NOR V IN-NAND, V OUT-NOR From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
Sub-V t Standard Cell Library Occurrences 2 1 Leakage Active.1.2.3 V OL (V) t Occurrences 1 5 Outliers.2.25.3 V OH (V) 1 t 1 Occurrences 5 Occurrences 5.1.2.3 V OL (V) From Kwong et al., ISSCC 8.2.25.3 V OH (V) 28 IEEE International Solid-State Circuits Conference 28 IEEE
Sub-V t SRAM Challenges Hold SNM WL WL Read SNM NT 1. NC BL 1. BL NT NC NT, NC (V).8.6.4 Hold SNM preserved to low-voltages NT, NC (V).8.6.4 Read SNM degraded at low-voltages.2.2.2.4.6.8 1. NC, NT (V) From Kwong et al., ISSCC 8.2.4.6.8 1. NC, NT (V) 28 IEEE International Solid-State Circuits Conference 28 IEEE
SRAM Architecture and Bit-Cell Based on Verma, ISSCC 27 Buffer eliminates read SNM limitation Peripheral assists allow sub-v t writing and sensing From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
Volts Volts WR.3.2.1 WR Peripheral Assists VV DD Write 1 12 14 16 18 2.3.2.1 NT VV DD 1 1 NT NC 1 NC 1 12 14 16 18 2 µs RDBL Voltage Read.4.3.2.1 From Kwong et al., ISSCC 8 1 VV DD 6T Cell PCHRG 1 (256, 64 Cells) No sub-v t leakage 1 (256 Cells) 1 (64 Cells) 1 2 3 4 µs 28 IEEE International Solid-State Circuits Conference 28 IEEE
Sub-V t Timing Analysis Challenges Order-of-magnitude higher delay variation in sub-v t Occurrences Occurrences From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
Comprehensive Timing Simulations Increasing mean delay Path # σ /µ (Std. dev. over mean) Simulation of 3 timing paths illustrates trends in sub-vt delay variability.6.4.2 Delay (ns) 2 Mean delay [ns] From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE 4
Test-Chip Summary Process DC-DC Converter SRAM Logic Minimum Energy Point Minimum Functional V DD Area Performance 65nm CMOS.12mm 2 1.36mm 2.14mm 2 V DD = 5mV V DD = 3mV 1.86mm Core logic (2 power domains) 128Kb SRAM array 2.29mm DC-DC converter From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
Conclusions Many opportunities for ultra low voltage design exist Energy Constrained Applications: wireless sensors, mobile devices, biomedical implants Minimum Power Applications: sleep and minimum leakage modes in processors and memories Main challenge is device parameter variations Threshold voltage variation severely impacts delays, noise margins in logic and SRAM Very active area of circuits research ISSCC 29 Advanced Circuits Forum on Ultra Low Voltage 17
Acknowledgments Jamie Collier Liping Guo Travis Kleeburg Jeff Loo Mackenzie Scott Justin Wenck Joyce Kwong, MIT Prof. Anantha Chandrakasan, MIT National Science Foundation CAREER Award FCRP Interconnect Focus Center Xilinx University Program and Xilinx Research Labs U.S. Dept. of Education GAANN Fellowship TSMC 18