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FAN73611 Single-Channel High-Side Gate Drive IC Features Floating Channel for Bootstrap Operation to +V 25 ma/5 ma Sourcing/Sinking Current Driving Capability Common-Mode dv/dt Noise-Canceling Circuit 3.3 V and 5 V Input Logic Compatible Output In Phase with Input Signal Under-Voltage Lockout for V DD and V BS 8-Lead Small Outline Package (SOP) Applications Electronic Ballast Switching-Mode Power Supply (SMPS) September 15 The FAN73611 is a monolithic high-side gate drive IC that can drive MOSFETs and IGBTs operating up to + V. Fairchild s high-voltage process and commonmode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to V S =-9.8 V (typical) for V BS =15 V. The UVLO circuits prevents malfunction when V DD or V BS is lower than the specified threshold voltage. The output drivers typically source/sink 25 ma/5 ma; respectively, which is suitable for Plasma Display Panel (PDP) application, motor drive inverter, and switching mode power supply applications. 8-SOP Related Application Notes AN-76 Design and Applicaiton Guide of Boostrap Circuit for High-Voltage Gate-Drive IC AN-952 Design Guide for Selection of Bootstrap Components AN-812 Recommendations to Avoid Short Pulse Width Issues in HVIC Gate Driver Applications Description Ordering Information Part Number Package Operating Temperature Packing Method Description FAN73611MX (1) 8 SOP - C ~ 125 C Tape & Reel Lighting Application Note: 1. This device passed wave soldering test by JESD22A-111. 1 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73611 Rev. 1.3
Typical Application Diagrams 15V PWM C1 1 R BOOT D BOOT FAN73611 V DD V B R1 2 IN HO 7 3 NC V S 8 6 4 GND NC 5 C BOOT V IN R2 L1 D1 Figure 1. Step-Down (Buck) DC-DC Converter Application C2 FAN73611 Rev.1 V OUT Internal Block Diagram V DD 1 8 V B IN GND 2 4 K UVLO PULSE GENERATOR NOISE CANCELLER UVLO R R S Q Shoot-through current compensated gate driver 7 6 HO V S Pin 3 and 5 are no connection. FAN73611 Rev.2 Figure 2. Functional Block Diagram 1 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73611 Rev. 1.3 2
Pin Configuration Pin Definitions V DD IN NC GND 1 2 3 FAN73611 FAN73611 Rev.1 Figure 3. Pin Configuration (Top View) Pin # Name Description 1 V DD Supply Voltage 2 IN Logic Input for High-Side Gate Driver Output 3 NC No Connection 4 GND Ground 5 NC No Connection 6 V S High-Voltage Floating Supply Return 7 HO High-Side Driver Output 8 V B High-Side Floating Supply V B 7 HO V S 4 5 NC 8 6 1 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73611 Rev. 1.3 3
Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T A =25 C unless otherwise specified. Symbol Characteristics Min. Max. Unit V S High-Side Floating Offset Voltage V B -25 V B +.3 V V B High-Side Floating Supply Voltage -.3 625. V V HO High-Side Floating Output Voltage V S -.3 V B +.3 V V DD Low-Side and Logic Supply Voltage -.3 25. V V IN Logic Input Voltage -.3 V DD +.3 V dv S /dt Allowable Offset Voltage Slew Rate ± 5 V/ns P D Power Dissipation (2, 3, 4).625 W JA Thermal Resistance C/W T J Junction Temperature -55 +15 C T STG Storage Temperature -55 +15 C Notes: 2. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material). 3. Refer to the following standards: JESD51-2: Integrated circuits thermal test method environmental conditions, natural convection, and JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages. 4. Do not exceed power dissipation (P D ) under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit V B High-Side Floating Supply Voltage V S +1 V S + V V S High-Side Floating Supply Offset Voltage 6-V DD V V HO High-Side Output Voltage V S V B V V IN Logic Input Voltage GND V DD V V DD Supply Voltage 1 V T A Operating Ambient Temperature - +125 C 1 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73611 Rev. 1.3 4
Electrical Characteristics V BIAS (V DD, V BS ) = 15. V and T A = 25 C unless otherwise specified. The V IN and I IN parameters are referenced to GND. The V O and I O parameters are relative to V S and are applicable to the respective output HO. Symbol Characteristics Test Condition Min. Typ. Max. Unit Power Supply Section I QDD Quiescent V DD Supply Current V IN = V or 5 V, C LOAD = pf 1 A I PDD V DDUV+ V BSUV+ V DDUV- V BSUV- V DDHYS V BSHYS Operating V DD Supply Current V DD and V BS Supply Under-Voltage Positive Going Threshold Voltage V DD and V BS Supply Under-Voltage Negative Going Threshold Voltage V DD and V BS Supply Under-Voltage Lockout Hysteresis Voltage C LOAD = pf, f IN = KHz, RMS value 1 A V DD =Sweep, V BS =Sweep 7.8 8.8 9.8 V V DD =Sweep, V BS =Sweep 7.3 8.3 9.3 V V DD =Sweep, V BS =Sweep.5 V I LK Offset Supply Leakage Current V B =V S = V 1 A I QBS Quiescent V BS Supply Current V IN = V or 5 V, C LOAD = pf A I PBS Input Logic Section Operating V BS Supply Current C LOAD = pf, f IN = KHz, RMS Value 4 A V IH Logic 1 Input Voltage 2.5 V V IL Logic Input Voltage.8 V I IN+ Logic Input High Bias Current V IN =5 V 5 75 A I IN- Logic Input Low Bias Current V IN = V 2 A R IN Input Pull-Down Resistance K Gate Driver Output Section V OH High Level Output Voltage (V BIAS - V O ) No Load.1 V V OL Low Level Output Voltage No Load.1 V I O+ Output High, Short-Circuit Pulsed Current V HO = V, V IN =5 V, PW 1 µs 25 ma I O- Output Low, Short-Circuit Pulsed Current V HO =15 V,V IN = V, PW 1 µs 5 ma V S Allowable Negative V S Pin Voltage for IN Signal Propagation to HO V BS =15 V -9.8-7. V Dynamic Electrical Characteristics V DD =V BS =15 V, C LOAD = pf, and T A =25 C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit t on Turn-On Propagation Delay Time V S = V 7 1 17 ns t off Turn-Off Propagation Delay Time V S = V 7 1 17 ns t r Turn-On Rise Time 7 1 ns t f Turn-Off Fall Time 3 ns. 1 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73611 Rev. 1.3 5
Typical Characteristics t ON t R 17 15 13 11 9 7 1 1 Figure 5. Turn-On Propagation Delay t OFF t F 17 15 13 11 9 7 5 3 Figure 6. Turn-Off Propagation Delay 1 Figure 7. Turn-On Rise Time Figure 8. Turn-Off Fall Time 1 1 I QDD I QBS Figure 9. Quiescent V DD Supply Current Figure 1. Quiescent V BS Supply Current 1 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73611 Rev. 1.3 6
Typical Characteristics (Continued) I PDD V DDUV+ 1 1 1 Figure 11. Operating V DD Supply Current 1. 9.5 9. 8.5 8. I PBS V DDUV- 55 5 45 35 3 25 1. 9.5 9. 8.5 8. Figure 12. Operating V BS Supply Current 7.5 7. 7.5 7. Figure 13. V DD UVLO+ Figure 14. V DD UVLO- 1. 1. 9.5 9.5 V BSUV+ 9. 8.5 V BSUV- 9. 8.5 8. 8. 7.5 7.5 7. 7. Figure 15. V BS UVLO+ Figure 16. V BS UVLO- 1 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73611 Rev. 1.3 7
Typical Characteristics (Continued) V IH 3. 2.5 2. 1.5 1. 75 65 Figure 17. Logic HIGH Input Voltage V IL 3. 2.5 2. 1.5 1..5 1 1 Figure 18. Logic LOW Input Voltage I IN+ 55 45 R IN [K ] 35 25 Figure 19. Logic HIGH Input Bias Current Figure. Input Pull-Down Resistance V OH [mv] V OL [mv] Figure 21. High-Level Output Voltage Figure 22. Low-Level Output Voltage 1 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73611 Rev. 1.3 8
Typical Characteristics (Continued) V S -7-8 -9-1 -11-12 -13 Figure 23. Allowable Negative V S Voltage 17 15 V S -4-6 -8-1 -12-14 -16 1 12 14 16 18 17 15 Figure 24. Allowable Negative V S Voltage vs. Supply Voltage t ON 13 11 t OFF 13 11 9 9 7 1 12 14 16 18 7 1 12 14 16 18 Figure 25. Turn-On Propagation Delay vs. Supply Voltage Figure 26. Turn-Off Propagation Delay vs. Supply Voltage 1 1 5 t R t F 3 1 1 12 14 16 18 1 12 14 16 18 Figure 27. Turn-On Rise Time vs. Supply Voltage Figure 28. Turn-Off Fall Time vs. Supply Voltage 1 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73611 Rev. 1.3 9
Typical Characteristics (Continued) I QDD I PDD 1 1 1 12 14 16 18 Figure 29. Quiescent V DD Supply Current vs. Supply Voltage 1 1 1 I QBS I PBS 1 12 14 16 18 55 5 45 35 Figure 3. Quiescent V BS Supply Current vs. Supply Voltage 1 12 14 16 18 3 25 1 12 14 16 18 Figure 31. Operating V DD Supply Current vs. Supply Voltage Figure 32. Operating V BS Supply Current vs. Supply Voltage 1 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73611 Rev. 1.3 1
Switching Time Definitions 1µF 1nF GND IN 15V V DD V B 1µF.1µF 5% 5% IN 15V t ON t R t OFF t R V S FAN73611 1nF 9% 9% HO OUT 1% 1% FAN73611 Rev.2 FAN73611 Rev.2 Figure 33. Switching Time Test Circuit and Waveform Definitions 15V UF7.1µF V B 1µF V DD VS.1µF GND GND FAN73611 -Vs pf OUTPUT MONITOR IN HO FAN73611 Rev.3 Figure 34. Floating Supply Voltage Transient Test 1 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73611 Rev. 1.3 11
.35 8 C 5.12 4.72 5 A B 1.75 6.3 5.7 4.15 3.75.65 5. 1.27 PIN #1 ID 1 4 TOP VIEW 1.27.25 M C B A LAND PATTERN RECOMMENDATION 1.85 1.35 C 1.75 1.25 C B C.25.15.25.1 GAGE PLANE 8 4 SEATING PLANE FRONT VIEW.51.31 (8X) BEVEL 1.4 DETAIL "B" SCALE 2:1.1 C R.1.25..3 OPTION A BEVEL EDGE SIDE VIEW OPTION B NON-BEVEL EDGE NOTES: UNLESS OTHERWISED SPECIFIED A. THIS PACKAGE CONFORMS TO JEDEC MS-12 VARIATION A EXCEPT WHERE NOTED. B. ALL DIMENSIONS ARE IN MILLIMETERS C OUT OF JEDEC STANDARD VALUE D. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR EXTRUSIONS. E. LAND PATTERN AS PER IPC SOIC127PX175-8M F. DRAWING FILENAME: MKT-M8Brev2
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