.V CMOS Static RAM 1 Meg (4K x 1-Bit) IDT71V1SA/HSA Features 4K x 1 advanced high-speed CMOS Static RAM Equal access and cycle times Commercial: 1//1/2 Industrial: /1/2 One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power coumption via chip deselect Upper and Lower Byte Enable Pi Single.V power supply Available in 44-pin Plastic SOJ, 44-pin TSOP, and 4-Ball Plastic FBGA packages Description The IDT71V1 is a 1,4,7-bit high-speed Static RAM organized as 4K x 1. It is fabricated using IDT s high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT71V1 has an output enable pin which operates as fast as, with address access times as fast as 1. All bidirectional inputs and outputs of the IDT71V1 are LVTTL-compatible and operation is from a single.v supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V1 is packaged in a JEDEC standard 44-pin Plastic SOJ, a 44-pin TSOP Type II, and a 4-ball plastic 7 x 7 mm FBGA. Functional Block Diagram OE Output Enable A A1 Address s Row / Column Decoders I/O1 Chip Enable High Byte I/O I/O Write Enable 4K x 1 Memory Array 1 See Amps and Write Drivers Low Byte I/O I/O7 I/O BHE BLE Byte Enable s 4 drw 1 27 Integrated Device Technology, Inc. 1 OCTOBER 2 DSC-4/1
IDT71V1SA,.V CMOS Static RAM 1 Meg (4K x 1-Bit) Commercial and Industrial Temperature Ranges Pin Configuratio 1 2 4 A4 1 44 A A2 A1 A I/O I/O1 I/O2 I/O 2 4 7 9 1 4 42 41 4 9 7 VDD 11 SO44-1 4 SO44-2 VSS I/O4 I/O I/O I/O7 A1 A14 A1 A NC 1 14 1 1 17 1 19 2 21 22 2 1 29 2 27 2 2 24 2 A A A7 OE BHE BLE I/O1 I/O14 I/O1 I/O VSS VDD I/O11 I/O1 I/O9 I/O NC A A9 A1 A11 NC A BLE OE A A1 A2 NC B I/O BHE A A4 I/O C I/O9 I/O1 A A I/O1 I/O2 D VSS I/O11 NC A7 I/O VDD E VDD I/O NC NC I/O4 VSS F I/O14 I/O1 A14 A1 I/O I/O G I/O1 NC A A1 I/O7 H NC A A9 A1 A11 NC Pin Description FBGA (BF4-1) Top View 4 tbl 2a SOJ/TSOP Top View 4 drw 2 Truth Table (1) OE BLE BHE I/O-I/O7 I/O-I/O1 Function H X X X X High-Z High-Z Deselected Standby L L H L H DATAOUT High-Z Low Byte Read L L H H L High-Z DATAOUT High Byte Read L L H L L DATAOUT DATAOUT Word Read L X L L L DATAIN DATAIN Word Write L X L L H DATAIN High-Z Low Byte Write L X L H L High-Z DATAIN High Byte Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled NOTE: 1. H = VIH, L = VIL, X = Don't care. 4 tbl 2.42 2
IDT71V1SA,.V CMOS Static RAM 1 Meg (4K x 1-Bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings (1) VDD Symbol Rating Value Unit VIN, VOUT Supply Voltage Relative to VSS Terminal Voltage Relative to VSS. to +4. V. to VDD+. V TBIAS Temperature Under Bias to + o C TSTG Storage Temperature to + o C PT Power Dissipation 1.2 W IOUT DC Output Current ma NOTE: 4 tbl 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. Capacitance (TA = +2 C, f = 1.MHz, SOJ package) Symbol Parameter (1) Conditio Max. Unit CIN Input Capacitance VIN = dv pf CI/O I/O Capacitance VOUT = dv 7 pf NOTE: 4 tbl 1. This parameter is guaranteed by device characterization, but not production tested. DC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) Recommended Operating Temperature and Supply Voltage Grade Temperature VSS VDD Commercial C to +7 C V See Below Industrial -4 C to + C V See Below Recommended DC Operating Conditio 1. For 71V1SA1 only. 2. For all speed grades except 71V1SA1.. VIH (max.) = VDD+2V for pulse width less than, once per cycle. 4. VIL (min.) = 2V for pulse width less than, once per cycle. 4 tbl 4 Symbol Parameter Min. Typ. Max. Unit VDD (1) Supply Voltage.1.. V VDD (2) Supply Voltage... V Vss Ground V VIH Input High Voltage 2. VDD+. V VIL Input Low Voltage. (4). V IDT71V1SA 4 tbl Symbol Parameter Test Condition ILI Input Leakage Current VDD = Max., VIN = VSS to VDD ILO Output Leakage Current VDD = Max., = VIH, VOUT = VSS to VDD Min. Max. Unit µa µa VOL Output Low Voltage IOL = ma, VDD = Min..4 V VOH Output High Voltage IOH = 4mA, VDD = Min. 2.4 V DC Electrical Characteristics (1,2) (VDD = Min. to Max., VLC =.2V, VHC = VDD.2V) 4 tbl 7 71V1SA1 71V1SA 71V1SA1 71V1SA2 Symbol Parameter Com'l Only Com'l Ind Com'l Ind Com'l Ind Unit ICC Dynamic Operating Current VLC, Outputs Open, VDD = Max., f = fmax Max. 1 1 1 1 1 Typ. (4) () -- -- -- ma ISB Dynamic Standby Power Supply Current VHC, Outputs Open, VDD = Max., f = fmax 4 4 4 ma ISB1 Full Standby Power Supply Current (static) 1 1 1 1 1 1 1 ma VHC, Outputs Open, VDD = Max., f = 1. All values are maximum guaranteed values. 2. All inputs switch between.2v (Low) and VDD.2V (High).. fmax = 1/tRC (all address inputs are cycling at fmax); f = mea no address input lines are changing. 4. Typical values are based on characterization data for H step only measured at.v, 2 C and with equal read and write cycles..42 4 tbl
IDT71V1SA,.V CMOS Static RAM 1 Meg (4K x 1-Bit) Commercial and Industrial Temperature Ranges AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to.v 1. 1.V 1.V See Figure 1, 2 and 4 tbl 9 AC Test Loads.V I/O Z = Ω +1.V Ω pf DATA OUT pf* 2Ω Ω Figure 1. AC Test Load 4 drw *Including jig and scope capacitance. Figure 2. AC Test Load (for tclz, tolz, tchz, tohz, tow, and twhz) 4 drw 4 taa, ta (Typical, ) 7 4 2 1 2 4 1 14 1 1 2 CAPACITANCE (pf) 4 drw Figure. Output Capacitive Derating.42 4
IDT71V1SA,.V CMOS Static RAM 1 Meg (4K x 1-Bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) 71V1SA1 (2) 71V1SA 71V1SA1 71V1SA2 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE trc Read Cycle Time 1 1 2 taa Address Access Time 1 1 2 ta Chip Select Access Time 1 1 2 tclz (1) Chip Select Low to Output in Low-Z 4 4 tchz (1) Chip Select High to Output in High-Z toe Outp ut Enable Low to Output Valid 7 tolz (1) Output Enable Low to Output in Low-Z tohz (1) Output Enable High to Output in High-Z toh Output Hold from Address Change 4 4 4 4 tbe Byte Enable Low to Output Valid 7 tblz (1) Byte Enable Low to Output in Low-Z tbhz (1) Byte Enable High to Output in High-Z WRITE CYCLE twc Write Cycle Time 1 1 2 taw Address Valid to End of Write 7 1 tcw Chip Select Lo w to End of Write 7 1 tbw Byte Enable Low to End of Write 7 1 tas Address Set-up Time twr Address Hold from End of Write twp Write Pulse Width 7 1 tdw Data Valid to End of Write 7 9 tdh Data Hold Time tow (1) Write Enable High to Output in Low-Z twhz (1) Write Enable Low to Output in High-Z 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 2. C to +7 C temperature range only. 4 tbl 1 Timing Waveform of Read Cycle No. 1 (1,2,) trc toh DATAOUT PREVIOUS DATAOUT VALID 1. is HIGH for Read Cycle. 2. Device is continuously selected, is LOW.. OE, BHE, and BLE are LOW. taa DATAOUT VALID toh 4 drw.42
IDT71V1SA,.V CMOS Static RAM 1 Meg (4K x 1-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 2 (1) trc taa toh OE BHE, BLE DATAOUT (2) ta tclz (2) tbe tblz toe tolz DATA OUTVALID tohz tchz tbhz 1. is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of, BHE, or BLE traition LOW; otherwise taa is the limiting parameter.. Traition is measured ±2mV from steady state. 4 drw 7 Timing Waveform of Write Cycle No. 1 ( Controlled Timing) (1,2,4) twc taw (2) tcw tbw () tchz BHE, BLE twp twr () tbhz DATAOUT tas PREVIOUS DATA VALID () twhz () tow DATA VALID tdw tdh DATAIN DATAIN VALID 4 drw 1. A write occurs during the overlap of a LOW, LOW BHE or BLE, and a LOW. 2. OE is continuously HIGH. If during a controlled write cycle OE is LOW, twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during a controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified twp.. During this period, I/O pi are in the output state, and input signals must not be applied. 4. If the LOW or BHE and BLE LOW traition occurs simultaneously with or after the LOW traition, the outputs remain in a high-impedance state.. Traition is measured ±2mV from steady state..42
IDT71V1SA,.V CMOS Static RAM 1 Meg (4K x 1-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 2 ( Controlled Timing) (1,4) twc taw BHE, BLE tas (2) tcw tbw twp twr DATAOUT DATAIN tdw DATAIN VALID tdh 4 drw 9 Timing Waveform of Write Cycle No. (BHE, BLE Controlled Timing) (1,4) twc taw BHE, BLE tas (2) tcw tbw twp twr DATAOUT tdw tdh DATAIN DATAIN VALID 4 drw 1 1. A write occurs during the overlap of a LOW, LOW BHE or BLE, and a LOW. 2. OE is continuously HIGH. If during a controlled write cycle OE is LOW, twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during a controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified twp.. During this period, I/O pi are in the output state, and input signals must not be applied. 4. If the LOW or BHE and BLE LOW traition occurs simultaneously with or after the LOW traition, the outputs remain in a high-impedance state.. Traition is measured ±2mV from steady state..42 7
IDT71V1SA,.V CMOS Static RAM 1 Meg (4K x 1-Bit) Commercial and Industrial Temperature Ranges Ordering Information 71V1 Device Type H SA Power XX Speed XXX Package X X X Process/ Tape & Reel Temperature Range Blank I Commercial ( C to +7 C) Industrial (-4 C to + C) G Y PH BF Restricted hazardous substance device 4-mil SOJ (SO44-1) 4-mil TSOP Type II (SO44-2) 7. x 7. mm FBGA (BF4-1) 1** 1 2 Speed in nanoseconds Blank H First generation or current stepping Current generation die step optional ** Commercial temperature range only. 4 drw 11.42
IDT71V1SA,.V CMOS Static RAM 1 Meg (4K x 1-bit) Commercial and Industrial Temperature Ranges Datasheet Document History 1/7/ Updated to new format Pp. 1,,, Added Industrial Temperature range offerings Pg. 2 Numbered I/Os and address pi on FBGA Top View Pg. Revised footnotes on Write Cycle No. 1 diagram Pg. 7 Revised footnotes on Write Cycle No. 2 and No. diagrams Pg. 9 Added Datasheet Document History // Pg. Tighten ICC and ISB. Pg. Tighten tclz, tchz, tohz, tbhz and twhz /22/1 Pg. Removed footnote "available in 1 and 2 only" /2/2 Pg. Added tape and reel field to ordering information 1//4 Pg. Added "Restricted hazardous substance device" to ordering information. 9/27/ Pg. Corrected ordering information, changed position of I and G. 2/14/7 Pg. Added H step generation to data sheet ordering information. /2/7 Pg. Changed typical parameters for ICC, DC electrical characteristics table. 1/1/ Pg. Removed "IDT" from orderable part number CORPORATE HEADQUARTERS for SALES: for Tech Support: 24 Silver Creek Valley Road -4-71 or ipchelp@idt.com San Jose, CA 91 4-24-2-4-71 fax: 4-24-277 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 9