machne Artcle Modelng, Analy, and Realzaton of Permanent Magnet Synchronou Motor Current Vector Control by MATLAB/Smulnk and FPGA Chu-Keng La, Yao-Tng Tao and Cha-Che Ta Department of Electrcal Engneerng, Natonal Chn-Y Unverty of Technology, Tachung 41170, Tawan; kpop015@yahoo.com.tw (Y.-T.T.); four094@yahoo.com.tw (C.-C.T.) Correpondence: chukl@ ncut.edu.tw; Tel.: +886-4-39-4505 Receved: 13 September 017; Accepted: 8 October 017; Publhed: 8 October 017 Abtract: In th paper, we preent modelng, analy, and realzaton of current vector control for a permanent magnet ynchronou motor (PMSM) drve ung MATLAB/Smulnk and a feld programmable gate array (FPGA). In AC motor drve ytem, mot of current vector control are realzed by dgtal gnal proceor (DSP) becaue of r complete and compact hardware functon. However, performance of drve ytem realzed by low-cot DSP are lmted by hardware tructure and computaton capacty, whch may lead to dffculty of reachng a fat enough repone, above all, for thoe motor wth a mall electrcal tme contant. Therefore, we ue FPGA to peed up calculaton about current vector control to attan a fat repone. Smulaton and practcal expermental reult are ued to verfy correctne and performance of degned full hardware ytem. Keyword: vector control; DSP; FPGA; permanent magnet ynchronou motor; MATLAB 1. Introducton The rapd development of hgh-performance and low-cot dgtal gnal proceor (DSP) ha encouraged reearcher to degn motor drve wth DSP. The functonalty of a DSP dependent on demand for partcular requrement and proceng peed. Snce motor control ung DSP ha been wdely developed by reearcher and ndutry, IC manufacturer have, thu, degned and produced pecfc DSP for motor control, uch a TI TMS30F8 ere DSP, Mcrochp dpic, etc. Thoe motor control cheme wth DSP a controller have advantage, uch a mple crcutry, oftware control, and flexblty n adaptaton to varou motor control requrement and applcaton. However, t mportant to have an nner current control loop wth a hort tme contant n order to obtan a rapd dynamc repone on velocty or poton control. To th requrement tated above, calculaton tme to decde dered wtchng pattern wth pace vector pule wdth modulaton (SVPWM) trategy requeted a hort a poble. Under th conderaton, nherent properte of DSP wth equental proceng and oftware executon may make ytem hardly reach dered performance on current loop control wth hgh amplng frequency, e.g., 40 khz or above, epecally for a fxed-pont DSP, or developed algorthm wthout upport by buld-n hardware of DSP. Therefore, a DSP wth a floatng pont proceor and hgh frequency clock developed and ued; however, th carre a hgh prce. Current feedback can be accomplhed by Hall enor or retor, and ometme analog nuodal gnal proceed by a low pa flter to remove component, ncludng thoe from modulaton. However, phae lag and ampltude attenuaton of wndng current from Hall enor and low pa flter hould be taken nto conderaton when ytem operated at hgh amplng frequency, whch cloed to bandwdth of Hall current enor or low pa flter. Machne 017, 5, 6; do:10.3390/machne504006 www.mdp.com/journal/machne
Machne 017, 5, 6 of 14 MATLAB/Smulnk, produced by MathWork, Inc., often ued to analy and mulaton for control purpoe, and controller degn of modern power electronc and motor drve ytem by feld programmable gate array (FPGA) ha become more and more mportant. Thu, MATLAB/Smulnk ha been ued a an alternatve method to automatcally generate a readable and portable IEEE tandard complant hardware decrpton language (HDL) to realze dered ytem whch generally and formerly bult by DSP [1]. Sytem degn wth MATLAB/Smulnk make complcated degn eaer. The degner can ealy buld and mulate r hardware control ytem by olvng conventonal control problem wth MATLAB/Smulnk. Of coure, ome, or even many, modfcaton are needed to realze developed hardware ytem on a electve FPGA. However, for reearcher, hardware crcut degn tartng from MATLAB/Smulnk anor choce to horten developng tme. An FPGA fully cutomzable, allowng a completely flexble degn whch cutom-made for partcular type of control technology. Furrmore, an FPGA feld programmable, and furr functonalte can be added anytme and anywhere when y are neceary []. FPGA-baed dgtal controller have, thu, been mplemented uccefully n motor drve, uch a nducton motor (IM) [3], permanent magnet ynchronou motor (PMSM) [4 7], teppng motor [8], bruhle DC motor [9], and wtched reluctance motor []. Addtonally, FPGA are alo ued n mplementaton of controller, uch a PID controller [10], fuzzy controller [4,11], trackng controller [8], and for realzaton of SVPWM module [6]. In th tudy, procedure of degnng an FPGA-baed current vector control for a PMSM drve ytem demontrated. The requrement of degn nclude fat wndng current repone, realzable ntellectual property (IP) for vector control, and complete nterface and perpheral. At frt, ytem degned va MATLAB/Smulnk on ytem level, mulated by ModelSm, produced by Mentor Graphc Corporaton, to evaluate correctne, and converted nto Verlog HDL code a a vector control IP. Next, ome modfcaton are made for developed IP ytem n order to be realzable by pecfc elected FPGA. To fnh degn of hardware ytem, nterface for an analog to dgtal converter (ADC), dgtal to analog converter (DAC), eral/parallel converter, quadrature encoder pule (QEP) counter, SVPWM module, and dgtal flter for peed movng average and for encoder gnal are ncluded n degn. Fnally, degned overall hardware crcut are appled to PMSM drve ytem to practcally evaluate performance of FPGA-baed ytem by howng nuodal teady-tate repone. Th paper organzed a follow. In Secton, mamatcal decrpton regardng electrcal crcut of PMSM motor are gven. The mulated and expermental ytem degned and created by MATLAB/Smulnk are hown n Secton 3. In Secton 4, mulated reult baed on ytem created n Secton 3, and expermental reult baed on FPGA, power module, and PMSM motor are demontrated. Fnally, concluon are gven n Secton 5.. The Electrcal Model of Permanent Magnet Synchronou Motor The typcal mamatcal model of a PMSM decrbed n dq-ax ynchronou rotatng reference frame a follow [4]: d d dt = R L d + ω e q + 1 v d L d L d (1) d d q dt = R q ω e L d d + 1 v q ω e λ f () where v d and v q are d- and q-ax voltage; d and q are d- and q-ax current; R phae wndng retance; L d and are d- and q-ax nductance, and L d = = L ; ω e rotatng peed of magnet flux; and λ f permanent magnet flux lnkage.
Ld Lq L ; rotatng peed of magnet flux; and e f permanent magnet flux lnkage. Generally, current control of PMSM baed on vector control approach, and generated torque, T, can be repreented a: e Machne 017, 5, 6 3 of 14 3P Te f q Ktq (3) Generally, current control of PMSM baed 4 on vector control approach, and generated torque, T e, can be repreented a: 3P where P pole number, and Kt T e = 3P 4 λ f torque contant. (3) how that 4 f q = Kt q (3) generated torque proportonal to q-ax current under decouplng control. where P pole number, and K t = 3P 4 λ f torque contant. (3) how that generated torque 3. proportonal Analy and todegn q-ax for current PMSM under Drve decouplng Sytem Baed control. MATLAB/Smulnk 3.1. Analy The Block and Dagram Degn of for PMSM PMSM Drve Drve Sytem Sytem Baed on MATLAB/Smulnk 3.1. The A complete Block Dagram velocty of PMSM control Drve model Sytem created n MATLAB/Smulnk hown n Fgure 1, whch nclude three PI controller (block A for peed control, block B for d-ax current control, and A complete velocty control model created n MATLAB/Smulnk hown n Fgure 1, whch block C nclude for q-ax three current PI controller control), (block decouplng A for peed control control, (block block D), B for d-ax 3 / current coordnate control, and tranformaton block C for(block q-axe current and F), control), and PMSM decouplng model. In control tudy, (block we manly D), conder 3ϕ/ϕ coordnate current tranformaton loop controller degn, (block epecally E and F), and q-ax PMSM one. The model. tructure In of tudy, enhanced we manlycurrent conder control current loop loop controller degn, epecally q-ax one. The tructure of enhanced current control loop baed on a tandard feld-orented control, and two voltage, v baed on tandard feld-orented control, and two voltage, v d and v d and v q n q n Equaton (1) and Equaton (1) and (), for (), d- for and d- and q-ax q-ax crcut crcut are, are, repectvely, repectvely, determned determned from from two two PI controller PI controller (block (block B and B and C). Snce C). Snce decouplng decouplng control control aumed, aumed, parameter parameter of of current current loop loop PI PI controller are degned eparately. A C E D B F Fgure 1. The block dagram of mulated ytem for PMSM peed control. In th tudy, controller for current loop are excluvely realzed by FPGA. In order to reach goalof offat fat current repone, all all component delay delay of of current current loop loop are taken are taken nto nto conderaton. conderaton. The The man man delay delay are are from from 1-bt 1-bt ADC, ADC, quadrature encoder pule (QEP) counter, and SVPWM module, etc. The block dagram of vector control repreented by Verlog HDL hown n Fgure, where n/co look up table (LUT), two PI controller, four coordnate tranformaton module and and SVPWM SVPWM module module are are ncluded. ncluded. In Fgure In Fgure, nce, nce rotor rotor a permanent a permanent magnet, magnet, d-ax command d-ax command et to zero. et to Addtonally, zero. Addtonally, q-ax command q-ax command whch proportonal whch proportonal to dered to torque dered from torque PI from controller PI controller of veloctyof control. velocty The control. block The named block a encoder_cnt named a encoder_cnt QEP counter, QEP whch counter, provde whch provde nformaton nformaton of rotor poton of rotor for poton and for velocty feedback, a well a coordnate tranformaton. The nput gnal of QEP are named a Z, P_A, and CW, whch come from encoder on motor. In Fgure, blue block are operated at a 0 khz clock.
Machne 017, 5, 6 4 of 15 poton and velocty feedback, a well a coordnate tranformaton. The nput gnal of QEP are named a Z, P_A, and CW, whch come from encoder on motor. In Fgure, blue block are operated at a 0 khz clock. Machne 017, 5, 6 4 of 14 PI controller coordnate tranformaton SVPWM Sn/Co LUT 3.. The Degn of Hardware PI Controller Fgure. The block dagram of current vector control. The PI controller realzed by FPGA frt come from contnuou ytem: CC() ( ) = K p + K (4) (4) where K p and p and K are K are parameter parameter of PI of controller. PI controller. Equaton Equaton (4) dgtalzed (4) dgtalzed by backward by dfference method: backward dfference method: = 1 z 1 (5) T 1 1 z where T amplng tme. To ubttuteequaton (5) nto Equaton (4), reultng dgtal (5) PI T controller a follow: where T amplng tme. To ubttute Equaton (5) nto Equaton (4), reultng dgtal PI C(z) = K p + K T 1 z 1 (6) controller a follow: In Equaton (6), I-control wth teraton operaton, and one lmter added to accumulator output to prevent aturaton. Snce amplng KT frequency for current control loop C( z) K p 1 (6) normally n cale of 10 khz 0 khz, amplng 1tme z qute mall. Thu, to conder reoluton of parameter and avod truncated error, varable are repreented n 3-bt number. In Equaton (6), I-control wth teraton operaton, and one lmter added to The realzed hardware PI controller are hown n Fgure 3 where command (cmd) and ytem accumulator output to prevent aturaton. Snce amplng frequency for current control loop feedback (fb) are nput. The data bu programmed a 3 bt, n whch 15 bt for nteger normally n cale of 10 khz 0 khz, amplng tme qute mall. Thu, to conder part, 16 bt for fractonal part, and one bt for gn bt. Addtonally, n Fgure 3, proce reoluton of parameter and avod truncated error, varable are repreented n 3-bt of error gnal n parallel ( P and I acton) to enhance performance and reduce number. The realzed hardware PI controller are hown n Fgure 3 where command (cmd) and calculaton tme. ytem feedback (fb) are nput. The data bu programmed a 3 bt, n whch 15 bt for nteger part, 16 bt for fractonal part, and one bt for gn bt. Addtonally, n Fgure 3,
Machne 017, 5, 6 5 of 15 Machne 017, 5, 6 5 of 14 proce of error gnal n parallel ( P and I acton) to enhance performance and reduce calculaton tme. Fgure 3. The realzaton of hardware PI controller. 3.3. The Clarke, Park, Invere Park, and Invere Clarke Tranformaton To mplement functon of of Clarke, Park, Invere Park, and Invere Clarke tranformaton, n(θ) n( ) and and co(θ) co( table ) table are are created. created. Each Each of of element element of of table table repreented repreented a 3-bt a number, 3-bt number, wth three wth bt three forbt for nteger nteger part, 8part, bt for 8 bt fractonal for fractonal part, andpart, oneand bt for one bt gn for bt. The gn ndex bt. The θ ndex from encoder from counter encoder whch counter alo whch programmed alo programmed a a 3-bt number. a a 3-bt number. 3.4. The SVPWM Model The SVPWM module bult to obtan dered voltage by outputtng x gate drver gnal, A1, A, B1, B, B, C1, C1, and and C, C, a hown a hown n Fgure n Fgure, and, more and more detal detal are hown are hown n Fgure n Fgure 4. The perod 4. The of perod SVPWM of SVPWM et a 50 et µa wth 50 aμ ymmetrcal wth a ymmetrcal tructure, and tructure, dead-tme and dead-tme et a 1 µ. et In Fgure a 1 μ 4,. control voltage, V d and V q from PI controller, are ued to generate correpondng wtchng In Fgure 4, control voltage, V d and V q from PI controller, are ued to generate pattern [6], example are hown n Fgure 5, where Fgure 5a ndcate that dered vector voltage correpondng Sector 1, and wtchng can be ynzed pattern [6], example by vector are hown V 0, V 1, n V, Fgure and V 7 5,. The where turn-on Fgure equence 5a ndcate are hown that ndered Fgure 5b, vector where voltage actve n vector Sector 1, are and V 1 can andbe V, ynzed non-effectve by vector vector are V 0 V and 0, V 7, 1, and: V, and V 7. The turn-on equence are hown T = n TFgure 0 + T a 5b, + Twhere b actve vector are V 1 and V (7), where non-effectve T 0 vector duraton are for V 0and ytem V 7, nand: zero vector V 0 (000) and V 7 (111), T a for vector V 1 (100) and T b for vector V (110) n condton of Fgure 5b. The total actve tme (T a + T b ), and duty cycle for th condton defned a: T T 0 Ta Tb (7) where 0 T duraton for ytem n zero vector V (000) 0 and (111) 7 V (100) 1 and T b for vector (110) T Duty Cycle (%) = T a + T b 100% V, T a for vector (8) V T n condton of Fgure 5b. The total actve tme ( Machne 017, 5, 6 6 of 15 a T b ), and duty cycle for th condton defned a: Ta Tb Duty Cycle (%) = 100% T (8) Fgure 4. 4. The SVPWM module. The SVPWM ytem condered a havng larget hardware delay n block dagram The SVPWM ytem condered a havng larget hardware delay n block dagram of of Fgure, and value 50 μ (0 khz amplng frequency). Fgure, and value 50 µ (0 khz amplng frequency). β V (1,1,0) V ref
Fgure 4. The SVPWM module. The SVPWM ytem condered a havng larget hardware delay n block dagram of Fgure, and value 50 μ (0 khz amplng frequency). Machne 017, 5, 6 6 of 14 β V (1,1,0) V ref Vector T T a V 1 T T b V (a) Sector1 V 1 (1,0,0) α T 0 Ta Tb T 0 T 0 Tb Ta T 0 V 7 V V 1 V 0 T T Tme (b) Fgure 5. The The generaton of V ofref V re by f by SVPWM. (a) A (a) vector A vector voltage voltage n Sector n 1; Sector and (b) 1; and wtchng (b) wtchng pattern. pattern. We degned all all component eparately, and and added added D-F-F D-F-F for thoe for thoe block block marked marked by 1 µby for1 μ ake for of ynchronzaton. ake of ynchronzaton. They arethey hown are nhown Fguren 6. Fgure Addtonally, 6. Addtonally, ADC need ADC 4 µneed to convert 4 μ to convert analog current analog gnal current ntognal dgtalnto value. dgtal By value. Fgure 6, By Fgure total 6, computaton total computaton tme to determne tme to determne duty cycle (Equaton duty cycle (8)) (Equaton for SVPWM (8)) for module SVPWM are 8 module µ, whch are are 8 horter μ, whch thanare horter 50 µ ofthan SVPWM perod. Thu, total propagaton tme from ADC to entry of SVPWM block could be omtted,.e., run tme of 50 µ of SVPWM perod uffcent to accomplh all of calculaton. In tudy, object to obtan a cloed-loop current control ytem wth bandwdth hgher than 1 khz, whch equvalent to havng a cloed-loop pole greater than 680 rad/. To th requrement, electrcal tme contant of motor tator wndng, choce of current enor, proceng of current gnal, and executon perod of SVPWM to generate control voltage are epecally taken nto conderaton. Among m, SVPWM module greatet obtacle n control loop due to fact that t need longet tme to complete a cyclng operaton. The degn procedure are a follow.
than greatet 1 khz, obtacle whch n equvalent control loop to due havng to a cloed-loop fact that t pole need greater longet than 680 tme rad/. to complete To th a requrement, cyclng operaton. electrcal The degn tme procedure contant are of a follow. motor tator wndng, choce of current enor, proceng of current gnal, and executon perod of SVPWM to generate control voltage are epecally taken nto conderaton. Among m, SVPWM module Modelm (Verlog HDL code) MATLAB greatet obtacle n control v 1u (1+50)u loop q due to fact that t need longet tme to complete a Machne 017, 5, q 6 6 7 of 14 cyclng operaton. The degn PI procedure v e to are a follow. to 3 SVPWM Inverter d Modelm (Verlog HDL code) d q 0 PI PI q v q v d d q d to e e to to e 1u 1u 1u MATLAB (1+4)u A/D 3 to 6 to 3 SVPWM converter Inverter 1u 3 to n/co LUT (1+50)u QEP (1+4)u 3 A/D converter Fgure 6. The vector control ytem to how propagaton 3 delay. Aumng ytem under decouplng control, q-ax equvalent cloed-loop control can be mplfed a hown n Fgure 7. The tranfer functon of q-ax crcut mplfed a: Fgure 6. The vector control ytem to how propagaton delay. Fgure 6. The vector control ytem I to how propagaton delay. q Aumng ytem under decouplng H ) 1 1 ( control, equvalent cloed-loop control (9) can Aumng ytem under decouplng Vcontrol, q Lq Rq-ax be mplfed a hown n Fgure 7. The tranfer functon of q-ax crcut equvalent mplfed cloed-loop a: control can be mplfed a hown n Fgure 7. The tranfer functon of q-ax crcut mplfed a: and cloed-loop relaton of Fgure 7 could be H H ) 1 () = I repreented a: q 1 = (9) K1 ( V q + R p K (9) V K p K q Lq R and cloed-loop relatoni qof Fgure 7 could Lq be repreented a: L q K p and cloed-loop H relaton ( ) of Fgure 7 could be repreented a: (10) I ( ) q H () = I R K p +K K p K K p R K q + p K K K p K p p K I = L( ) Iq Lq K p H q + R + K = ( ) q L q L p + K q + R Lq L + K (10) p q L + K q where ( ) (10) where Iq I q q-ax current command. In (10), re are one zero at ( K q-ax current I command. q R In K(10), p re K are one K R p K Lq L zero at ( K /K / K p ) p) and two pole and two pole to be to be determned. q L q Lq L q Lq where d 0 I + PI Controller Q-ax Equvalent q q-ax current command. In (10), re are one zero at ( K / K p) - (4) Crcut (9) to be determned. q PI 1u n/co LUT v q QEP q PMSM PMSM and two pole q + - PI Controller (4) v q Q-ax Equvalent Crcut (9) Fgure 7. The equvalent block dagram of q-ax cloed-loop current control. Fgure 7. The equvalent block dagram of q-ax cloed-loop current control. Wth Wth conderaton conderaton to to get get a wde wde bandwdth bandwdth repone, repone, a a large large proportonal proportonal gan gan of of K p p choen, and rato made: choen, and rato made: K Fgure 7. The equvalent block dagram of = 0 K p q-ax cloed-loop current control. (11) In Equaton (11), parameter K Wth conderaton to get a wde p and K bandwdth of PI controller are alo programmed a 3-bt repone, a large proportonal gan of K p number. Wth ettng, we could ealy obtan dered reoluton for parameter of controller. choen, and Accordng rato to made: aumpton of Equaton (11), Equaton (10) can be mplfed a: q I q I q = K p ( ) + R + K (1) p + K Snce value of K p / greater than value of K /, Equaton (1) can be furr rewrtten a: I q I q = K p + ( R + K p ) = K p + ( R + K p ) (13)
Machne 017, 5, 6 8 of 14 Regardng Equaton (1) and (13), y how that parameter K p can manly be ued to determne bandwdth of q-ax crcut. Addtonally, control parameter of d-ax can be obtaned n ame manner. The charactertc of Equaton (1) a econd-order band-pa flter, whch ha lower 3 db frequency and upper 3 db frequency. However, nce lower 3 db frequency mall enough to be omtted, bandwdth of Equaton (1) very cloe to that of Equaton (13). Due to fact that electrcal crcut operated at a hgher frequency ( amplng frequency, f ), approxmaton of Equaton (13) vald. It noted that hardware control ytem for PMSM current vector control decrbed n paper may alo be ued for current vector control of nducton motor, except command of d-ax current, whch wll not be et to zero due to tructure of rotor. 4. Smulaton, Experment, and Dcuon Smulaton and experment are both done to how performance of degned hardware control ytem. The charactertc of PMSM motor are hown n Table 1. The number of pole 10; tator retance and nductance are, repectvely, 3.5 Ω and 13 mh [1]. The electrcal tme contant about 3.71 m. A cloed-loop control wth PI controller a kernel ued to compenate ytem, and expected cloed-loop bandwdth equal to, or greater than, 1 khz. To reach goal, K p of peed PI controller frt degned accordng to Equaton (13), and choen a K p = 100 for th ytem. The bandwdth of equvalent current loop ytem f 3dB = 500 Hz. The parameter of PI controller are K p = 100 and K = 0.00, amplng frequency et a f = 0 khz, whch eght tme dered ytem bandwdth, and th ft crteron of dgtal gnal proceng. Wth above-mentoned parameter, we have equvalent ytem: I q I q = 15385 + 15654 (14) Table 1. The parameter of PMSM motor (FRLS 400506A). Pole 10 R (Ω) 3.5 L (mh) 13 J m (kg m 10 4 ) 0.70 B m (Nm ec) 0 φ(wb) 0.0707 T c (Nm) 1.7 The correpondng frequency repone of Equaton (14) hown n Fgure 8 wth MATLAB, and bandwdth about.5 khz, whch greater than dered 1 khz. A tated n lat ecton, Equaton (1) a band-pa ytem, and frequency repone hown n Fgure 9. It noted that, n regon of low frequency, repone of Fgure 8 dfferent from one of Fgure 9. Neverle, ytem operated at f = 0 khz, whch far away from lower 3 db frequency, whch about 5 10 5 rad/, and repone for both ytem are very mlar.
and bandwdth about.5 khz, whch greater than dered 1 khz. A tated n lat ecton, Equaton (1) a band-pa ytem, and frequency repone hown n Fgure 9. It noted that, n regon of low frequency, repone of Fgure 8 dfferent from one of Fgure 9. Neverle, ytem operated at f 0 khz, whch far away from lower 3 Machne 017, 5, 6 9 of 14 5 db frequency, whch about 5 10 rad/, and repone for both ytem are very mlar. Fgure Fgure 8. 8. The The frequency frequency repone repone of of Equaton Equaton (14). (14). The waveform of command from a prevouly-bult dcrete-type nuodal gnal, The waveform of command from a prevouly-bult dcrete-type nuodal gnal, whch whch programmed and tored n memory of FPGA, and all data are 3-bt number. programmed and tored n memory of FPGA, and all data are 3-bt number. The FPGA The FPGA ued to mplement ytem made wth an Altera Corp. model Cyclone III ued to mplement ytem made wth an Altera Corp. model Cyclone III EP3C10E144C8. EP3C10E144C8. Snce man object are focued on nner current cloed-loop control to yeld Snce man object are focued on nner current cloed-loop control to yeld a fat repone a fat repone wth dedcated ytem by SVPWM, reult regardng current loop of wth dedcated ytem by SVPWM, reult regardng current loop of q-ax are man q-ax are man component to be hown. Machne component 017, 5, to6 be hown. 10 of 15 Fgure 9. The frequency repone of Equaton (1). Fgure 9. The frequency repone of Equaton (1). 4.1. The Smulaton Reult 4.1. The Smulaton Reult The mulaton frt performed on MATLAB/Smulnk platform. Fgure 10 and 11 are The mulaton frt performed on MATLAB/Smulnk platform. Fgure 10 and 11 are mulaton reult wth control block dagram a hown n Fgure 1. To prevent aturaton of mulaton reult wth control block dagram a hown n Fgure 1. To prevent aturaton of PI controller and PMSM drve, ampltude of current command et to A. In followng, PI controller and PMSM drve, ampltude of current command et to 1 A. In followng, reult for command at 100 Hz and khz nuodal nput are demontrated, repectvely. reult for command at 100 Hz and 1 khz nuodal nput are demontrated, repectvely. Fgure 10 how reult at 100 Hz, where q cmd and d cmd are, repectvely, 100 Hz nuodal command nput, and q fb and d fb are current feedback. The repone and command of two fgure are very cloe to each or. In Fgure 10a, re only a mall DC offet between two trace, and n Fgure 10b, d-ax current very mall, except for tranent duraton at tart. Furrmore, we et 1 khz nuodal command a nput, and
(a) The mulaton frt performed on MATLAB/Smulnk platform. Fgure 10 and 11 are mulaton reult wth control block dagram a hown n Fgure 1. To prevent aturaton of PI controller and PMSM drve, ampltude of current command et to 1 A. In followng, reult for command at 100 Hz and 1 khz nuodal nput are demontrated, repectvely. Fgure 10 how reult at 100 Hz, where Machne 017, 5, 6 q cmd and d cmd are, repectvely, 100 Hz 10 of 14 nuodal command nput, and q fb and d fb are current feedback. The repone and command Fgure 10 how of two reult fgure at 100 are Hz, very where cloe to each q cmd and or. In d cmd are, Fgure repectvely, 10a, re 100 only Hz a nuodal mall DC offet command between nput, and two trace, q f b and and n d f b are Fgure current 10b, feedback. d-ax current The repone very mall, and except command for of tranent two fgure duraton are at very tart. cloe Furrmore, to each or. we In et Fgure 1 khz 10a, nuodal re command only a mall a DC offet nput, between and current two ampltude trace, and n alo Fgure approxmately 10b, d-ax 1 current A. Fgure very 11 mall, mulated except for reult. tranent A duraton pont marked at tart. Furrmore, on Fgure 11a we of et 1 q-ax khz nuodal repone, command tme delay a 0.00115 nput, and 0.001108 current = 0.00004 ampltude ; t equvalent alo approxmately to a phae 1 A. lag Fgure 15.111. Addtonally, mulated reult. dfference A of pont ampltude marked onbetween Fgure 11a qof cmd q-ax repone, tme delay 0.00115 0.001108 = 0.00004 ; t equvalent to a phae lag 15.1. and Addtonally, q fb very mall. Snce phae delay le than 45, and nearly no ampltude drop off, dfference of ampltude between q cmd and q f b very mall. Snce phae delay q-ax le equvalent than 45, and crcut nearly under no ampltude feedback control, drop off, thu, q-ax ha a equvalent bandwdth crcut greater under than feedback 1 khz. Fgure control, 11b thu, how ha that a bandwdth d-ax greater current than tll 1 khz. mall, Fgure except 11b for how tranent that duraton d-ax current hown n tll reult mall, except of Fgure for 10b. tranent duraton hown n reult of Fgure 10b. Machne 017, 5, 6 11 of 15 (a) (b) Fgure Fgure 10. 10. The The mulated mulated reult reult wth wth 100 100 Hz Hz nuodal nuodal command. command. (a) (a) q-ax q-ax current current command command and and repone; repone; and and (b) (b) d-ax d-ax current current command command and and repone. repone.
(b) Fgure 10. The mulated reult wth 100 Hz nuodal command. (a) q-ax current command and Machne 017, 5, 6 11 of 14 repone; and (b) d-ax current command and repone. (a) (b) Fgure Fgure 11. 11. The The mulated mulated reult reult wth wth 1 khz khz nuodal nuodal command. command. (a) (a) q-ax q-ax current current command command and and feedback; feedback; and and (b) (b) d-ax d-ax current current command command and and feedback. feedback. 4.. The Expermental Setup and Reult The hardware etup for mplementaton of experment hown n Fgure 1. It nclude an Altera FPGA-baed control board, a 1-bt eral ADC and eral DAC board, power module board, brake, and PMSM. Analog current of phae A and B are ened by retor on power module board wthout flterng, and are converted nto dgtal value by eral ADC, AD7866, wth unpolar mult-channel voltage nput. The ADC are operated at a 50 khz amplng frequency, t feed back dgtal value of wndng current to controller n FPGA by way of eral to parallel nterface. Addtonally, DAC are ued to convert dcrete-type control varable (current of q and q ) nto analog waveform wth tranfer gan of 0.5 V/A, and hown on dgtal ocllocope. Fnally, we copy waveform on ocllocope and plot m n MATLAB. Furrmore, PMSM motor haft-connected to a brake, and rotor locked by brake when operatng wth hgh-frequency command nput. The current command ued n mulaton are alo ued for experment, and only reult of q-ax current are hown. Fgure 13 how reult wth an ampltude of 1 A and a frequency of 100 Hz. It how that degned repone nearly matche command wthout phae delay and ampltude attenuaton,.e., t ha good trackng when t operated at 100 Hz. It worth notcng that trgger tme of Fgure 13 et at center of creen due to fact that data n fgure from dgtal ocllocope. Fgure 14 reult wth command 1 khz. Two pont, ( 0.00005 0.004) and ( 0.0000 0.004), are choen to evaluate phae delay and correpondng
reult of q-ax current are hown. Fgure 13 how reult wth an ampltude of 1 A and a frequency of 100 Hz. It how that degned repone nearly matche command wthout phae delay and ampltude attenuaton,.e., t ha good trackng when t operated at 100 Hz. It worth notcng that trgger tme of Fgure 13 et at center of creen due to fact that data n fgure from dgtal ocllocope. Fgure 14 reult wth command 1 khz. Machne 017, 5, 6 1 of 14 Two pont, ( 0.00005 0.004) and ( 0.0000 0.004), are choen to evaluate phae delay and correpondng reult 10.8. Th how that repone ha only a lght drop-off n ampltude and reulta mall 10.8. Th phae how delay that compared repone to ha only command. a lght drop-off Upon comparng ampltude andmulated a mall phae and expermental delay compared reult, to command. t alo found Upon comparng that y are mulated qute mlar and expermental to each or. reult, Fnally, t alo expermental found that yreult are qute how mlar that to each hardware or. Fnally, ytem ha expermental attaned reult expected how performance that hardware wth a bandwdth ytem ha attaned greater than expected 1 khz. performance wth a bandwdth greater than 1 khz. Brake and load Power Module FPGA Board PMSM motor ADC and DAC Machne 017, 5, 6 Fgure Fgure 1. 1. The The etup etup of of expermental expermental ytem. ytem. 13 of 15 0.5A/Dv Fgure Fgure 13. 13. The The expermental expermental reult reult wth wth a 100 100 Hz Hz nuodal nuodal nput. nput. 0.5A/Dv
Reference Machne 017, 5, 6 13 of 14 Fgure 13. The expermental reult wth a 100 Hz nuodal nput. 0.5A/Dv 5. Concluon Fgure 14. The expermental reult wth a 1 khz nuodal nput. In th paper, we we have hown analy and and hardware hardware current current loop loop controller controller degn degn wth FPGA wth FPGA for a PMSM for a drver. PMSM The drver. degnthe conder degn conder executng andexecutng computaton and delay computaton of hardware delay ytem. of hardware The developng ytem. procedure The tart developng from ytem procedure degn wth tart MATLAB/Smulnk, from ytem and degn bult model wth MATLAB/Smulnk, verfed by Modelm. and Moreover, bult model reultng verfed Verlog by Modelm. HDL code Moreover, are modfed reultng to ft elected Verlog HDL FPGA. code Fnally, are modfed developed to ft ytem elected realzed FPGA. on an Fnally, Altera Cyclone developed III FPGA, ytem and evaluated realzed by on an Altera PMSM Cyclone drve ytem. III FPGA, The mulated and evaluated and practcal by expermental PMSM drve reult ytem. how The that mulated developed and practcal current expermental loop vector control reult ytem how wththat MATLAB/Smulnk developed ha current been uccefully loop vector realzed, control and ytem alo reveal wth MATLAB/Smulnk a hgh dynamc repone. ha been Theuccefully bandwdth realzed, greaterand thanalo 1 khz. reveal The a etup hgh ytem dynamc alo repone. uccefully The bandwdth operate current greater ytem than 1 reachng khz. The to etup khz ytem a hown alo n Fgure uccefully 15, where operate repone current ha aytem phae reachng delay approxmately to khz a hown 57.6. n Fgure 15, where repone ha a phae delay approxmately 57.6The. dgtal hardware crcut for controller degn are complcated when y are developed drectly The from dgtal hardware electronccrcut degnfor automaton controller (EDA) degn ytem. are On complcated orwhen hand, y whenare developed degn drectly tarted from platform electronc lke MATLAB/Smulnk, degn automaton (EDA) LabVIEW, ytem. or or On mlar or tool, hand, y when make degn degn Machne tarted eay. Of 017, from coure, 5, 6 platform t neceary lke MATLAB/Smulnk, to optmze created LabVIEW, hardware or crcut or mlar to maketool, t an uable y make IP. 14 of 15 degn eay. Of coure, t neceary to optmze created hardware crcut to make t an uable IP. 0.5A/Dv Fgure 15. The expermental reult wth a khz nuodal command. Author Contrbuton: Chu-Keng La and Yao-Tng Tao conceved and degned experment; Yao-Tng Tao and Cha-Che Ta performed experment; Chu-Keng La, Yao-Tng Tao, and Cha-Che Ta analyzed data; and Chu-Keng La and Yao-Tng Tao wrote paper. Conflct of Interet: The author declare no conflct of nteret.
Machne 017, 5, 6 14 of 14 Author Contrbuton: Chu-Keng La and Yao-Tng Tao conceved and degned experment; Yao-Tng Tao and Cha-Che Ta performed experment; Chu-Keng La, Yao-Tng Tao, and Cha-Che Ta analyzed data; and Chu-Keng La and Yao-Tng Tao wrote paper. Conflct of Interet: The author declare no conflct of nteret. Reference 1. Swakot, Y.P.; Town, G.E. Degn of FPGA-Controlled Power Electronc and Drve Ung MATLAB Smulnk. In Proceedng of IEEE/ECCE, Melbourne, VIC, Autrala, 3 6 June 013; pp. 571 577. [CroRef]. Stumpf, A.; Elton, D.; Devln, J.; Lovatt, H. Beneft of an FPGA baed SRM controller. In Proceedng of IEEE 9th Conference on Indutral Electronc and Applcaton (ICIEA), Hangzhou, Chna, 9 11 June 014; pp. 1 17. 3. Roht, B.C.; Patl, M.D.; Shah, D.; Kadam, A. FPGA Implementaton of SVPWM Control Technque for Three Phae Inducton Motor Drve Ung Fxed Pont Realzaton. In Proceedng of 014 Internatonal Conference on Crcut, Sytem, Communcaton and Informaton Technology Applcaton, Mumba, Maharahtra, Inda, 4 5 Aprl 014; pp. 93 98. 4. Kung, Y.-S.; Ta, M.-H. FPGA-Baed Speed Control IC for PMSM Drve wth Adaptve Fuzzy Control. IEEE Tran. Power Electron. 007,, 476 486. [CroRef] 5. Kung, Y.-S.; Huang, P.-G.; Chen, C.-W. Development of a SOPC for PMSM Drve. In Proceedng of 47th IEEE Internatonal Mdwet Sympoum on Crcut and Sytem, Hrohma, Japan, 5 8 July 004; pp. 39 33. 6. Quynh, N.V.; Kung, Y.-S. FPGA-Realzaton of Fuzzy Speed Controller for PMSM Drve wthout Poton Senor. In Proceedng of ICCAIS, Nha Trang, Vetnam, 5 8 November 013; pp. 78 8. [CroRef] 7. Zhang, G.Z.; Zhao, F.; Wang, Y.X.; Wen, X.H.; Cong, W. Analy and Optmzaton of Current Regulator Tme Delay n Permanent Magnet Synchronou Motor Drve Sytem. In Proceedng of 013 Internatonal Conference on Electrcal Machne and Sytem, Buan, Korea, 6 9 October 013; pp. 86 90. 8. Zhang, C.J.; Wu, X.J.; Zuo, X.Y. FPGA Soft-Core Baed Step Motor Drvng. In Proceedng of 010 Internatonal Conference on Electrcal and Control Engneerng, Wuhan, Chna, 5 7 June 010; pp. 1035 1038. 9. Horvat, R.; Jezernk, K.; Curkovc, M. An Event-Drven Approach to Current Control of a BLDC Motor Ung FPGA. IEEE Tran. Ind. Electron. 014, 61, 3719 376. [CroRef] 10. Kocur, M.; Kozak, S.; Dvorcak, B. Degn and Implementaton of FPGA-Dgtal Baed PID Controller. In Proceedng of 15th Internatonal Carpathan Control Conference, Velke Karlovce, Czech Republc, 8 30 May 014; pp. 33 36. 11. Quang, N.K.; Kung, Y.-S.; Ha, Q.P. FPGA-Baed Control Archtecture Integraton for Multple-Ax Trackng Moton Sytem. In Proceedng of IEEE/SICE, Kyoto, Japan, 0 December 011; pp. 591 596. [CroRef] 1. Data heet of FRLS400506A. Avalable onlne: http://www.hwn.de/en/produktfnder_detal_/ Motor_Drve_and_Acceore/Servo_motor/Wthout_motor_brakeand_fear_key/0373 (acceed on 3 October 017). 017 by author. Lcenee MDPI, Bael, Swtzerland. Th artcle an open acce artcle dtrbuted under term and condton of Creatve Common Attrbuton (CC BY) lcene (http://creatvecommon.org/lcene/by/4.0/).