Manufacturing Case Studies: Copy Exactly (CE!) and the two-year cycle at Intel Paolo A. Gargini Director Technology Strategy Intel Fellow 1
Agenda 2-year cycle Copy Exactly Conclusions 2
I see no reason to expect the rate of progress In the use of smaller dimensions in complex Circuits to decrease in the near future. With respect to the factor contributed by Device and Circuit Cleverness, however, the situation is different. We are approaching a limit that must slow the rate of progress The new slope might approximate a doubling Every two years. Gordon Moore, IEDM 1975 3
.but Cost of Equipment Continues to Raise (ISMT Exposure Tool Cost Survey Results) Source: ISMT EUV CoO Analysis Update, 1st International EUVL Symposium, October 15th 2002 4
Industry Challenge Introduction of new products into the market place requires very costly investments in research, development and manufacturing. How can an IC company optimize the above phases and obtain maximum return on investment in the shortest time? 5
Intel Semiconductor Roadmap 15nm Moore s Law is driving semiconductor technology ~ 30% reduction in transistor size with each new technology every e 2 years ~ 2X more chips per wafer with each new process technology ~ 2X improvement in the product price/performance ratio 6
Intel s Core Competencies Drive Processor Performance Silicon Process Transistors Technology 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ (Millions) Intel Brand Pentium Processor 60MHz Pentium II Processor Pentium III Processor 3.3 7.5 9.5-25 Pentium 4 Processor 2GHz+ Northwood 42 + Itanium Processor Madison Deerfield 40 + Process transitions enable: 2x die per wafer, ½ transistor cost, 2x microprocessor speed 7
Capital cost per unit wafer area Moderate Cost Increase from Generation to Generation and 300mm Rolls Cost Back 0.35µm 0.25µm 0.18µm 0.13µm 200mm 0.13µm 300mm 8
>60X Transistor Cost Drop from 350nm to 90nm Node (Source: Intel 03) 100.0 Normalized Cost/Transistor 10.0 1.0 Cost per Total Trans 25% Savings/Year 35% Savings/Year 40% Savings/Year 0.1 350nm 250nm 180nm 130nm 90nm 1995 1997 1999 Cost/Transistor Normalized to to 130nm Node 2001 Technology Node/Introduction Year 2003 9
Transistor Manufacturing Costs Falling (Source: Sematech 02) Historic -26 % CAGR Accelerated -32 % CAGR Strategic -26 % CAGR Wafer Size Blend 125/150mm 200mm Wafer Size Blend 200mm 300mm Source: Goodall,Randall, et.al., Long-Term Productivity Mechanisms of of the Semiconductor Industry, 9th International Symposium on on Semiconductor Silicon 2002, sponsored by by ECS, International Sematech 10
15 years of Is a technology transfer methodology pioneered by Intel The method ensures consistent yield and quality at any Intel factory making the same products The result is highly predictable output from our factories Whether this methodology is suitable for other companies or other industries depends on many factors 11
Intel Research, Development and Manufacturing Research Activities are de-centralized Multiple sites, consortia, universities, etc Central Technology Development groups Logic: Hillsboro, Oregon Memory: Santa Clara, California Packaging: Chandler, Arizona from Development into Manufacturing Fastest and Highest Volume Manufacturing Ramp 12
Intel s High Volume Manufacturing Sites Washington Systems Mfg. Oregon Dev D1C/D1D Fab 15/20 Board Mfg. California Dev D2 Sub-con Mfg. Arizona Fab12/22 A/T Dev New Mexico Fab 11/11X Colorado Fab 23 Mass. Fab 17 Costa Rica Ireland Fab 14/24 San Jose A/T Brazil Sub-con Mfg. Israel Fab 8/18 Thailand Sub-con Mfg. Malaysia China Pudong A/T Sub-con Mfg. Penang A/T Kulim A/T Kulim Board/Module Mfg. Sub-con Mfg. Taiwan Sub-con Mfg. Philippines Manila A/T Cavite A/T 13
Technology Focus: Logic Actual Forecast Process Name P858 Px60 P1262 P1264 P1266 P1268 P1270 1 st Production 1999 2001 2003 2005 2007 2009 2011 Lithography Node 180 130 90 65 45 32 22nm Gate Length 130 70 50 30 20 15 10nm Fab Development Research Copy Exactly! Pathfinding 14
Huge cumulative investments as volume manufacturing begins 1000x Wafers/Wk 100x Internal Budget 10x 1x External Budget Year 1 2 3 4 5 6 7 8 9 Research Development Manufacture Engineers Yield Enhancements 15
First Generation! Results Equivalent Yield Development CE! Fab 2nd Fab 3rd Fab Months 16