Aalborg Unverstet An mproved desgn of vrtual output mpedance loop for droop-controlled parallel three-phase Voltage Source Inverters Wang, Xongfe; Blaabjerg, Frede; Chen, Zhe Publshed n: Proceedngs of the IEEE Energy Converson Congress and Exposton 2012 DOI (lnk to publcaton from Publsher): 10.1109/ECCE.2012.6342404 Publcaton date: 2012 Document Verson Early verson, also known as pre-prnt Lnk to publcaton from Aalborg Unversty Ctaton for publshed verson (APA): Wang, X., Blaabjerg, F., & Chen, Z. (2012). An mproved desgn of vrtual output mpedance loop for droopcontrolled parallel three-phase Voltage Source Inverters. In Proceedngs of the IEEE Energy Converson Congress and Exposton 2012 (pp. 2466-2473). Ralegh, NC: IEEE Press. DOI: 10.1109/ECCE.2012.6342404 General rghts Copyrght and moral rghts for the publcatons made accessble n the publc portal are retaned by the authors and/or other copyrght owners and t s a condton of accessng publcatons that users recognse and abde by the legal requrements assocated wth these rghts.? Users may download and prnt one copy of any publcaton from the publc portal for the purpose of prvate study or research.? You may not further dstrbute the materal or use t for any proft-makng actvty or commercal gan? You may freely dstrbute the URL dentfyng the publcaton n the publc portal? Take down polcy If you beleve that ths document breaches copyrght please contact us at vbn@aub.aau.dk provdng detals, and we wll remove access to the work mmedately and nvestgate your clam. Downloaded from vbn.aau.dk on: marts 11, 2018
An Improved Desgn of Vrtual Output Impedance Loop for Droop-Controlled Parallel Three-Phase Voltage Source Inverters Xongfe Wang, Frede Blaabjerg, Zhe Chen Department of Energy Technology Aalborg Unversty, Aalborg, Denmark xwa@et.aau.dk, fbl@et.aau.dk, zch@et.aau.dk Abstract The vrtual output mpedance loop s known as an effectve way to enhance the load sharng stablty and qualty of droop-controlled parallel nverters. Ths paper proposes an mproved desgn of vrtual output mpedance loop for parallel three-phase voltage source nverters. In the approach, a vrtual output mpedance loop based on the decomposton of nverter output current s developed, where the postve- and negatvesequence vrtual mpedances are syntheszed separately. Thus, the negatve-sequence crculatng current among the parallel nverters can be mnmzed by usng a large negatve-sequence vrtual resstance even n the case of feedng a balanced threephase load. Furthermore, to adapt to the varety of unbalanced loads, a dynamcally-tuned negatve-sequence resstance loop s desgned, such that a good compromse between the qualty of nverter output voltage and the performance of load sharng can be obtaned. Fnally, laboratory test results of two parallel three-phase voltage source nverters are shown to confrm the valdty of the proposed method. I. INTRODUCTION The power electronc-based dstrbuted power generaton has undergone a rapd development n recent years. A wde spread use of voltage source nverters as grd nterfaces for dstrbuted energy resources (DER) can be envsoned n the near future [1]. To accommodate the ncreased penetraton of DER unts, the mcrogrd concept that can operate n grdconnected and slanded modes s emergng as an attractve way. The ntentonal and non-ntentonal slanded operatons of mcrogrds provde more relable electrcty servce durng abnormal dsturbances n the upstream grd [2]. To preserve the stablty and power qualty of a mcrogrd, partcularly n the dynamc slandng operatons, the cooperatve control of nverter-nterfaced DER unts plays an essental role. Hence, there s an ncreasng concern over the paralleled operaton of voltage source nverters, and n such systems, the dampng of crculatng current among nverters s mportant for the stablty and qualty of load sharng [3]. A number of control approaches have been developed to acheve a good load sharng among parallel nverters [4]. The droop control schemes, among other optons, have shown superor performances n terms of the relablty and costs, thanks to the absence of communcaton lnks [5]. However, due to the mpact of lne mpedance and load characterstcs, several lmtatons are mposed on drectly usng the actve power-frequency (P-ω) droop and the reactve power-voltage (Q-V) droop controllers. For example, the hgh R/X rato of dstrbuton feeders couples the control of actve power and reactve power flows, whle on the other hand the frequencyand voltage-dependent load characterstcs lmt to use the opposte droop relatonshps,.e. Q-ω and P-V droops [6]. To overcome such effects, the closed-loop output mpedance of the nverter s adjusted by, ether changng the bandwdth of the voltage control loop [7], or nsertng a vrtual mpedance loop [8]. Snce the njecton of noncharacterstc frequency sgnal s needed n [7], t requres advanced sgnal processng technques whch complcate the control system. In contrast, the vrtual mpedance loop s much easer to mplement and has become more popular. It s well known that the vrtual output mpedance loop s manly nductve to reshape the R/X rato of nterconnected mpedances among nverters. For a three-phase nverter, the vrtual nductance can be easly realzed usng the complex number calculaton n the statonary -frame, thus the tme dervatve of the output current can be avoded [9]. However, only the postve-sequence vrtual nductance s syntheszed n ths way. For parallel three-phase nverters wth separate DC-lnks, the crculatng current among them comprses the negatve-sequence crculatng current (NSCC) n addton to the postve-sequence crculatng current (PSCC) [10]. Thus, the conventonal nductve vrtual mpedance has lttle effect on the dampng of the NSCC, and the output currents of the parallel nverters become unbalanced even n the presence of balanced three-phase loads. To solve ths problem, nstead of syntheszng vrtual nductance, a vrtual resstance loop s appled wth a resonant voltage controller n [11]. Thus, the vrtual resstance takes the same effect on the postve- and negatve-sequence output currents. Nevertheless, ths method
s n capable of dampng the NSCC when feedng balanced or slghtly unbalanced three-phase loads, due to the couplng between the sharng of actve power and negatve-sequence load current. In [12], a negatve-sequence conductance loop based on the output voltage decomposton s reported, where a droop relatonshp between the negatve-sequence reactve power (Q ) and the negatve-sequence conductance (G) s bult. Thus, a better sharng of the unbalanced compensaton burdens can be obtaned n comparson to the fxed vrtual resstance scheme. However, the performance of the Q G droop method s stll restrcted on reducng the NSCC when feedng balanced three-phase loads, snce the NSCC n ths case s gradually reduced wth the decrease of G. In order to overcome the aforementoned drawbacks, an mproved desgn of vrtual output mpedance loop for threephase nverters s proposed n ths paper. In the approach, the nverter output current s decomposed nto the postve- and negatve-sequence components. A vrtual resstance loop for the negatve-sequence output current s developed, together wth the conventonal nductve vrtual mpedance loop for the postve-sequence output current. Thus, the NSCC among parallel nverters can be effectvely damped by adjustng the negatve-sequence vrtual resstance. Compared wth the PIbased NSCC control schemes n [10], the negatve-sequence vrtual resstance can be furnshed n each nverter wthout usng any addtonal nterconnecton crcut, whch s more sutable for scattered DER nverters. Furthermore, to adapt to the unbalanced load varaton, a dynamcally-tuned negatvesequence vrtual resstance loop s desgned, such that a good compromse between the performance of sharng negatvesequence currents and the nverter output voltage qualty can be obtaned. Fnally, laboratory tests on two parallel threephase voltage source nverters are performed to confrm the valdty of the proposed method. II. CIRCULATING CURRENT IN PARALLEL VOLTAGE- CONTROLLED DER INVERTERS Fg. 1 shows an example of an slanded three-phase lowvoltage mcrogrd, where n parallel DER unts are nterfaced wth three-phase voltage source nverters and connected to a common AC bus through dstrbuton feeders, respectvely. The DC-lnks of DER nverters are assumed to be controlled by the separate, solated energy sources and kept constant. A. Defnton of Crculatng Current The crculatng current of a three-phase nverter s termed as the dfference between the actual output current and the assgned load current, whch s gven by [13] n k a, b, c c h h, (1) m, 1,2,..., n k, m ok, ok, m m1 n m1 hm 1 (2) where c k, s the crculatng current of the -th DER nverter and k denotes the nverter phase. ok, and ok, m are the output currents of the -th and m-th nverters, respectvely. h m and h Energy source Energy source Energy source # DER 1 # DER 2 # DER n L a, 1 Z la, 1 L b, 1 L c, 1 C a, 1 C a, 2 Z La C b, 1 C c, 1 Z Lb Z Lc Z lb, 1 Z lc, 1 L a, 2 Z la, 2 L b, 2 L c, 2 L a, n L b, n L c, n C b, 2 C c, 2 C a, n C b, n C c, n Z lb, 2 Z lc, 2 Z la, n Z lb, n Z lc, n Fg. 1. An example of an slanded three-phase low-voltage mcrogrd. are the load current dstrbuton factors for the -th and m-th nverter, respectvely, and the sum of all dstrbuton factors equals to 1. Fg. 2 shows a path for the crculatng current between two parallel DER nverters. Snce the DC-lnks of nverters are solated, there s no zero-sequence crculatng current n the nverters. However, due to the component tolerance, and the parameters drfts of sensors, the asynchronous swtchng patterns of the nverters are nevtably generated [14]. As a consequence, the path for the non-zero-sequence crculatng current, whch s also termed as the cross current n [15], s formed whenever the nverters are n the dfferent swtchng state. Furthermore, t can be seen that the non-zero-sequence crculatng current flowng through one phase s dependent on the crculatng current n the other two phases. In such case, the parallel DER nverters can be further smplfed as a set of parallel-connected three-phase voltage sources [16]. B. Small-Sgnal Modelng of DER Inverter Wthn the slanded mcrogrd DER nverters are usually controlled as voltage sources. Notce that the nverter output mpedance has an mportant effect on the characterstc of crculatng current. Thus, the closed-loop dynamc behavor of nverter output voltage control loop has to be consdered n order to derve the crculatng current of a DER nverter. Fg. 3 llustrates the block dagram of the output voltage control scheme adopted for the -th DER nverter. It conssts of two loops, where an nner nductor current controller wth a proportonal term, K pc,, s used for over-current protecton
Fg. 2. A non-zero-sequence crculatng current path between two parallel DER nverters. Fg. 3. Block dagram of output voltage control scheme adopted by the -th DER nverter and flter resonance dampng, and an outer capactor voltage control loop usng the proportonal plus resonant controller, whch can be gven by K v, V, () pv, 2 2 s G s K Notce that the nverter wth a constant DC-lnk voltage s a lnear system [17]. The closed-loop dynamc behavor of DER nverter can be equvalent as a Thevenn equvalent crcut, whch are derved as follows G o, cl, () s Vo, o, cl, o, o, o, s (3) V ( s) G ( s) V ( s) Z ( s) ( s) (4) V () s () s o, ( s) 0 K G () s G () s L C s K G () s r C s K G () s G () s pc, d, V, 2 f, f, pc, d, f, f, pc, d, V, Vo, () s Zo, () s () s o, vo, ()0 s L sr K G () s L C s K G () s r C s K G () s G () s f, f, pc, d, 2 f, f, pc, d, f, f, pc, d, V, (5) (6) where V o (s) and V o, (s) are the actual and command nverter output voltages, repectvely. G cl, (s) denotes the closed-loop transfer functon of the voltage control loops, and Z o, (s) s the output mpedance. r f, s the parastc resstance of the flter nductance L f,. G d, (s) s the 1.5 samplng perod (T s ) delay ncludng the computatonal delay (T s ) and the PWM delay (0.5T s ). C. Analyss of Crculatng Current Fg. 4 llustrates the small-sgnal model of parallel threephase DER nverters n the statonary frame. Notce that any dfferences among the ampltudes of voltage sources may result n crculatng currents. Snce the output current of the -th nverter can be easly derved by o, G () s V () s V () s Z () s Z () s cl, o, pcc l, o, where V pcc s the voltage at the common AC bus and Z l, (s) s the lne mpedance. Under the crculatng current defnton n (1), the crculatng current of the -th DER nverter can be obtaned n (8), shown at the bottom of next page, where δ j s defned as (7) 1 j j 0, j (9)
G clα, 1 V oα, 1 G clβ, 1 V oβ, 1 G clα, 2 V oα, 2 G clβ, 2 V oβ, 2 # DER Inveter 1 Z oα, 1 Z lα, 1 Z oβ, 1 Z lβ, 1 Z oα, 2 Z lα, 2 Z oβ, 2 Z lβ, 2 controller, and 3) the ntermedate vrtual output mpedance loop. A. Lmts of Droop Control Consderng the frequency- and voltage-dependent loads effects [6], the standard actve power-frequency (P-ω) and the reactve power-voltage (Q-V) droop controllers are used, whch can be gven by mp (10) 0 G clα, n V oα, n # DER Inveter 2 Z oα, n Z Lα Z Lβ Z lα, n V V nq (11) 0 where ω 0 and V 0 are the nomnal frequency and magntude of the -th nverter output voltage at no load. m and n are the frequency and voltage droop coeffcents, respectvely, and the followng condtons are needed to determne the load dstrbuton factors of nverters. G clβ, n V oβ, n Z oβ, n Z lβ, n mpmp mp (12) 1 1 2 2 n n # DER Inveter n Fg. 4. The small-sgnal model of parallel three-phase DER nverters n the statonary frame. From (8), t s seen that the crculatng current s not only affected by the voltage dfferences of DER nverters, but also subjected to the load condton at the common AC bus. Also, the presence of any unbalanced parameters drfts wll cause unbalanced voltage dfferences among the nverters, and the unbalanced crculatng current loop are consequently formed. Hence, dfferent from the parallel sngle-phase nverters, the crculatng current n the three-phase nverters conssts of the PSCC and the NSCC. Under the certan voltage dfferences, the magntudes of crculatng currents are dependent on the lne mpedance and the nverter output mpedance. Thus, by actvely controllng the nverter output mpedance, the crculatng current can be damped effectvely. However, n the presence of dfferent electrcal constants, lke the dfferent lne mpedance and the unbalanced load, a good compromse between the qualty of the nverter output voltage and the suppresson level of the crculatng current s needed. III. PROPOSED CONTROL METHOD Fg. 5 llustrates the dagram of the droop-based power control scheme and the proposed vrtual mpedance loop for the -th DER nverter. The approach employs a mult-loop control scheme, whch ncludes 1) the nner voltage control loops, as shown n Fg. 3, 2) the outer droop-based power nq nq nq (13) 1 1 2 2 n n Snce there s an ntegral relatonshp between the power angle and the frequency, the zero steady-state error of actve power sharng can be acheved by usng the P-ω droop [18]. In contrast, the Q-V droop controller depends heavly on the characterstcs of power transfer mpedances among parallel nverters. The hgh R/X rato of the low-voltage dstrbuton lne mpedance degrades the performance of reactve power sharng. Furthermore, the droop controller only takes effect on the PSCC, whereas the NSCC stll reman n the output currents of nverters. B. Proposed Vrtual Output Impedance Loop The desgn of the vrtual output mpedance loop has two man purposes,.e. 1) to enhance the stablty and qualty of usng the P-ω and Q-V droop control, and 2) to suppress the NSCC n parallel nverters. To acheve these objectves, a vrtual output mpedance loop based on the decomposton of the output current s developed. Thus, both the postve- and negatve-sequence vrtual mpedances can be syntheszed, as shown n Fg. 5. Fg. 6 shows the dagrams of the nverter voltage and current sequence detector. The double synchronous reference frames are used to detect the postve- and negatve-sequence components. The frst-order low-pass flter wth 1 Hz cut-off frequency s adopted n each reference frame. It s worth to menton that the feedforward decouplng terms are less effectve n such case, snce the transent changes of the 1j h1 Zl,1 Zo,1 c n, Gcl,1 Vo,1 Gcl,2 Vo,2 Gcl, nvo, n 2j h2 Zl,2 Z,2 j h V o c, Gcl,1 Vo,1 Gcl,2 Vo,2 Gcl, nvo, n j1 Zl, j Zo, j V nj hn Zl, n Zo, n pcc pcc (8)
Energy source Z l, PCC Inner loop (Fg. 3) PWM Labc, L V o, L, DER nverter abc C V oabc, oabc, abc Postve-Sequence Vrtual Impedance abc V op, V on, V oβp RvP, ω LvP, oβp Negatve-Sequence Vrtual Resstance op, on, V o, V oαp ω LvP, RvP, oαp R vn, R vn0, R vnd, Dynamcally- Tuned (Fg. 7) Sequence Detector (Fg. 6) o, Proposed Vrtual Output Impedance Loop 1 0 1.2% 2% Unbalanced Factor (Eq. 14) V on, V op, ω t ω ω 0 P 0 Voltage reference generator V Droop controller V 0 V Q Q 0 Q P P P & Q calculator Fg. 5. Block dagram of the droop-based power control scheme and the proposed vrtual output mpedance loop output current can aggravate the nteractons between the dfferent sequence components. For the postve-sequence vrtual output mpedance loop, the nductve mpedance s desgned to mtgate the effect of hgh R/X rato of dstrbuton lnes and to reduce the error of sharng reactve power among the nverters [9]. On the other hand, for the negatve-sequence vrtual mpedance loop, an adaptve resstance s syntheszed to damp the NSCC. Notce that the negatve-sequence nductance can also be used here, but wth lower stablty margn due to the 90 degrees phase shft. Dependng on the presence of the unbalanced loads, the negatve-sequence resstance s adaptvely swtched between a statc large resstance and a dynamcally-tuned one. The NSCC tself s dynamcally reduced wth the ncrease of negatve-sequence vrtual resstance. Thus, lttle unbalanced voltage dstorton s caused at the output of the nverter. Hence, the voltage unbalanced factor can be used to detect the presence of unbalanced loads [19], whch s defned as U V V V V (14) 2 2 2 2 N, on, on, op, op, The negatve-sequence resstance s ntally fxed wth a large value at the start of the nverter. When the unbalanced loads are absent, the NSCC can be damped effectvely by the large negatve-sequence resstance. The voltage unbalanced factor s kept below a certan value 1.2%, whch s dependent on the parameters devatons of voltage sensors. Based on the hysteress control n Fg. 5, the negatve-sequence resstance s kept as R vn0. In the case that unbalanced loads are present, o, V o, ω t -ω t ω t -ω t 1Hz 1Hz 1Hz 1Hz ω t -ω t ω t -ω t Fg. 6. Block dagram of the adopted sequence detector. op, on, V op, V on, once the negatve-sequence load current causes the voltage unbalanced factor hgher than the lmt, 2%, the negatvesequence vrtual resstance are swtched from the fxed value to a dynamcally-tuned one. Fg. 7 shows the block dagram of the dynamcally-tuned negatve resstance loop. A proportonal relatonshp between the negatve-sequence reactve power Q N, [20] and the negatve-sequence vrtual resstance s ntroduced, so that the nverter wth hgher negatve-sequence reactve power can furnsh a hgher negatve-sequence resstance. The values of proportonal coeffcents for all nverters need to meet the followng condton kq kq kq (15) 1 N,1 2 N,2 n N, n
VP, X 0.2 Hz QN, RN RvNd, QN N, X 0.2 Hz VN, X 0.2 Hz KQ, 1/X Fg. 7. Block dagram of the dynamcally-tuned negatve-sequence vrtual resstance. where k s the coeffcent of the proportonal relatonshps n the -th nverter. Furthermore, wth the ncrease of the unbalanced loads, the negatve-sequence nverter output voltage wll nevtably ncrease. Thus, a smaller negatve-sequence vrtual resstance s generally needed to get a good load sharng. To adapt to the ncrease of unbalanced loads, the proportonal coeffcent s dynamcally reduced accordng to the negatve-sequence voltage at the output of nverter. IV. LABORATORY TEST RESULTS To evaluate the performance of the proposed approach, two 5.5 kw Danfoss frequency converters powered by two separate, solated DC sources are used as the DER nverters. Fg. 8 shows the schematc of the test system bult n the lab. Two nductances, L l, 1 and L l, 2, are used to represent the lne mpedances n the laboratory tests, respectvely. The control system for parallel nverters s mplemented n the DS1006 dspace system wth the 10 khz samplng frequency and a half-perod nterrupt shft. The man crcut constants and the control system parameters are summarzed n Table I and II, respectvely. To clearly see the adverse effect of the NSCC, a balanced three-phase parallel R-L load s tested at the frst step. Fg. 9 (a) shows the tested output current waveforms for the case of only usng the conventonal vrtual output mpedance loop. It s seen that the output current of the nverters are unbalanced even feedng balanced three-phase loads, whch valdates the presence of the NSCC between parallel nverters. Also, the crculatng current can be observed through the dfference n the phase-a output currents of two nverters. In contrast, the nverter output current waveforms wth the proposed vrtual output mpedance are shown n Fg. 9 (b). It s obvous that the NSCC s effectvely damped by the negatve-sequence vrtual resstance loop. Fg. 10 shows the steady-state waveforms n the presence of an unbalanced load. Fg. 10 (a) shows the output voltages and phase-a output currents of nverters when the negatvesequence vrtual resstances are kept as R vn0. It s clearly seen that the current dfferences are almost zero, whle the output voltages are obvously unbalanced. It ndcates that the fxed Fg. 8. Schematc of the laboratory test system. TABLE I. MAIN CIRCUIT CONSTANTS Crcut Constants Values L 1 = L 2 1.5 mh LC-flters of nverters C 1 = C 2 25 µf DC voltages of nverters V dc, 1 = V dc, 2 750 V Lne nductance L l, 1 = L l, 2 3 mh Parallel R-L load R L L L 40 Ω 160 mh Unbalanced load R U 80 Ω System voltage V 0 380 V System frequency ω 0 314 rad/s TABLE II. CONTROL SYSTEM PARAMETERS Controller Parameters Values Current controller K pc, 1 = K pc, 2 10 Voltage controller Droop controller Postve-sequence vrtual mpedance loop Negatve-sequence vrtual resstance loop K pv, 1 = K pv, 2 0.2 K v, 1 = K v, 2 50 m 1 = m 2 10-4 n 1 = n 2 10-3 R vp, 1 = R vp, 2 0 L vp, 1 = L vp, 2 R vn0, 1 = R vn0, 2 K Q, 1 = K Q, 2 30 6 mh 20 Ω negatve-sequence vrtual resstances tend to aggravate the unbalanced voltage dstortons when the unbalanced loads ncreases. Thus t s needed to adaptvely adjust the negatvesequence vrtual resstance. Fg 10 (b) shows the measured waveforms after actvatng the dynamcally-tuned negatvesequence resstance loop. Compared to Fg. 10 (a), the output voltages are clearly mproved, whereas the dfference of the phase-a output currents s slghtly ncreased. It mples that a
INV 2 [2 A/dv] [4 ms/dv] (a) INV 1 [5 A/dv] INV 2 [2 A/dv] INV 1 [2 A/dv] INV 2 [5 A/dv] [4 ms/dv] [4 ms/dv] Current dfference [2 A/dv] [4 ms/dv] (b) Fg. 9. Measured output current waveforms of the nverters feedng a balanced three-phase load. INV 1 [100 V/dv] INV 2 [100 V/dv] [4 ms/dv] [4 ms/dv] (a) (b) Fg. 10. Measured output voltage and current waveforms of the nverters n the presence of an unbalanced three-phase load. good trade-off between the performance of unbalanced load sharng and the unbalanced voltage dstorton s acheved. Fg. 11 shows the measured transent waveforms when the unbalanced load s swtched on and off. To confrm the performance of the negatve-sequence vrtual resstance loop, the changes of the voltage unbalanced factor, the negatvesequence reactve power, and the negatve-sequence vrtual resstance are evaluated. It s seen that before the unbalanced load s swtched on, the negatve-sequence reactve power s almost zero, the voltage unbalanced factor s lower than the threshold, 2 %, and the negatve-sequence vrtual resstance s kept as RvN0. Once the unbalanced load s swtched on, the voltage unbalanced factor ncreases to be hgher than 2 %, the negatve-sequence vrtual resstance s swtched from the RvN0 to be a dynamcally-tuned resstance, whch drops down rapdly, snce the negatve-sequence reactve power ncreases slowly. At the nstant of swtchng off the unbalanced load, the voltage unbalanced factor starts to reduce gradually to be INV 1 Current dfference [2 A/dv] Negatve-Sequence Vrtual Resstance [10 Ω /dv] Negatve-Sequence Recatve Power [500 Var /dv] (a) [2 s/dv]
(b) Fg. 11. Measured transent waveforms when the unbalanced load s swtched on and off. Fg. 12. Measured transent waveforms when the unbalanced load s swtched on and off. lower than the threshold, 1.2 %, and then negatve-sequence vrtual resstance s swtched back to R vn0. Fg. 12 compares the negatve-sequence reactve powers of two nverters when the dynamcally-tuned resstance loop s used. It ndcates that a good unbalanced load sharng durng the transents s acheved. V. CONCLUSIONS Ths paper has dscussed an mproved desgn method of the vrtual output mpedance loop for the droop-controlled parallel voltage source nverters. The crculatng current n the parallel nverters are frst modeled consderng the effect of the closed-loop output mpedances of nverters. Then, a vrtual mpedance loop for dampng the NSCC s proposed. In the approach, a vrtual mpedance loop that s based on the decomposton of the output current s developed, thus the postve- and negatve-sequence vrtual mpedance can be desgned separately. As a consequence, the NSCC can be effectvely damped usng the negatve-sequence resstance. Furthermore, n the case that unbalanced loads present, an adaptve negatve-sequence vrtual resstance s desgned, so that the negatve-sequence vrtual resstance can be changed automatcally accordng to the output voltage unbalanced factors. Fnally, laboratory test results have been shown to confrm the performance of the proposed control method. REFERENCES [1] F. Blaabjerg, Z. Chen, and S. B. Kjaer, Power electroncs as effcent nterface n dspersed power generaton systems, IEEE Trans. Power Electron. vol. 19, no. 5, pp. 1184-1194, Sept., 2004. [2] R. Lasseter, Smart dstrbuton: Coupled mcrogrds, IEEE Proc., vol. 99, no. 6, pp. 1074-1082, Jun. 2011. [3] J. Rocabert, A. Luna, F. Blaabjerg, and P. Rodrguez, Control of power converters n AC mcrogrds, IEEE Trans. Power Electron. vol. 27, no. 11, pp. 4734-4749, Nov., 2012. [4] X. Wang, J. M. Guerrero, F. Blaabjerg, and Z. Chen, A revew of power electroncs based mcrogrds, Journal of Power Electron., vol. 12, no. 1, pp. 181-192, Jan. 2012. [5] X. Wang, J. M. Guerrero, F. Blaabjerg, and Z. Chen, Dstrbuted energy resources n grd nteractve AC mcrogrds, n Proc. IEEE PEDG 2010, pp. 806-812. [6] H. Zeneldn and J. Krtley, Mcro-grd operaton of nverter based dstrbuted generaton wth voltage and frequency dependent loads, n Proc. IEEE PESGM, pp. 1-6, 2009. [7] A. Tuladhar, H. Jn, T. Unger, and K. Mauch, Control of parallel nverters n dstrbuted ac power systems wth consderaton of lne mpedance, IEEE Trans. Ind. Appl., vol. 36, no. 1, pp. 131-138, Jan./Feb. 2000. [8] S. J. Chang and J. M. Chang, Parallel control of the UPS nverters wth frequency-dependent droop scheme, n Proc. IEEE PESC 2001, pp. 957-961. [9] J. He and Y. L, Analyss, desgn and mplementaton of vrtual mpedance for power electroncs nterfaced dstrbuted generaton, IEEE Trans. Ind. Appl., vol. 47, no. 6, pp. 2525-2538, Nov./Dec., 2011. [10] C. T. Pan and Y. H. Lao, Modelng and coordnate control of crculatng currents n parallel three-phase boost rectfers, IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 825-838, Apr. 2007. [11] D. De and V. Ramanarayanan, Decentralzed parallel operaton of nverters sharng unbalanced and nonlnear loads, IEEE Trans. Power Electron. vol. 25, no. 12, pp. 3015-3025, Dec., 2010. [12] P. T. Cheng, C. A. Chen, T. L. Lee, and S. Y. Kuo, A cooperatve mbalance compensaton method for dstrbuted-generaton nterface converters, IEEE Trans. Ind. Appl., vol. 45, no. 2, pp. 805-815, Mar./Apr., 2009. [13] C. T. Pan and Y. H. Lao, Modelng and control of crculatng currents for parallel three-phase boost rectfers wth dfferent load sharng, IEEE Trans. Ind. Electron., vol. 55, no. 7, pp. 2776-2785, Jul. 2008. [14] T. Itkonen, J. Luukko, A. Sankala, T. Laakkonen, and R. Pollanen, Modelng and analyss of the dead-tme effects n parallel PWM two-level three-phase voltage-source nverters, IEEE Trans. Power Electron. vol. 24, no. 11, pp. 2446-2455, Nov., 2009. [15] Y. Komatsuzak, Cross current control for parallel operatng three pahse nverter, n Proc. IEEE PESC 1994, pp. 943-950. [16] T. Itkonen, J. Luukko, and R. Pollanen, Analyss of current characterstcs of parallel three-phase voltage source nverters, n Proc. EPE 2009, pp. 1-10. [17] S. Ht and D. Borojevc, Small-sgnal modelng and control of three-phase PWM converter, n Proc. IEEE IAS 1994, pp. 1143-1150. [18] X. Wang, J. M. Guerrero, and Z. Chen, Control of grd-nteractve AC mcrogrds, n Proc. IEEE ISIE 20010, pp. 2211-2216. [19] A. V. Jouanne and B. Banerjee, Assessment of voltage unbalance, IEEE Trans. Power Del. vol. 16, no. 4, pp. 782-790, Oct., 2001. [20] A. E. Emanuel, On the defnton of power factor and apparent power n unbalanced polyphase crcuts wth snusodal voltage and currents, IEEE Trans. Power Del. vol. 8, no. 3, pp. 841-852, Jul., 1993.