SEVEN-LEVEL THREE PHASE CASCADED H-BRIDGE INVERTER WITH A SINGLE DC SOURCE

SEVEN-LEVEL THREE PHASE CASCADED H-BRIDGE INVERTER WITH A SINGLE DC SOURCE T. Porselvi 1 ad Ragaath Muthu 1 Sri Sairam Egieerig College, Cheai, Idia SSN College of Egieerig, Cheai, Idia E-Mail: tporselvi@yahoo.com ABSTRACT Multi level iverters (MLIs) have bee attractive for high power applicatios. Amog the various MLIs, the Cascaded H-Bridge iverter is promisig for grid coected wid power ad photovoltaic applicatios. This paper compares three types of MLIs amely the Neutral Poit Clamped MLI, the Flyig Capacitor MLI, ad the Cascaded H- Bridge MLI. I additio, the Cascaded H-Bridge MLI with a sigle DC source is preseted. These MLIs are simulated i MATLAB usig multi-carrier sie pulse width modulatio (MCPWM) techique. Simulated output voltages ad currets for a RL load are show for the four cofiguratios ad compared based o the total harmoic distortio (THD). Results obtaied show the applicability of the Cascaded H-Bridge iverter with a sigle DC source for grid coected wid power applicatios. Keywords: cascaded H-bridge iverter (CHB), multi carrier pulse width modulatio (MCPWM), eutral poit clamped iverter (NPC), flyig capacitor iverter (FLC), total harmoic distortio (THD). 1. INTRODUCTION MLIs are becomig icreasigly popular for their high voltage operatig capability, high power capability ad reduced EMI effects. MLIs have three or more voltage levels; have lower total harmoic distortio (THD) ad less switchig losses compared to the classical iverters. There have bee various desigs for MLIs icludig the followig: Cascaded H-Bridge (CHB) Iverter Neutral Poit Clamped (NPC) Iverter Flyig-capacitor (FLC) Iverter Of the above, the Cascaded H- Bridge Iverter does ot require ay clamp diodes or capacitors. It achieves high voltage by cascadig multiple sigle-phase iverter modules ad requires the least umber of compoets [1]. I additio, it is flexible, robust ad easy to cotrol. However, the CHB iverter has the disadvatage of requirig idepedet DC sources.. NPC, FLC AND CONVENTIONAL CHB INVERTERS Figure-1 shows the sigle-phase seve-level NPC iverter, which uses a sigle DC source, 1 IGBT/ DIODE switches, 10 diodes ad 6 capacitors. Figure- shows the sigle-phase seve-level FLC iverter, which uses a sigle DC source, 1 IGBT/ DIODE switches ad 7 capacitors. Figure-. Seve-level FLC Figure-3 shows the covetioal sigle-phase seve-level CHB iverter that requires three separate DC sources ad 1 IGBT/ DIODE switches. Each DC source has a sigle phase H-bridge [-3]. Figure-1. Seve-level NPC Figure-3. Covetioal seve level CHB 1546

3. MULTI CARRIER PWM The most popular cotrol techique used i MLIs is the siusoidal or sub harmoic atural pulse width modulatio (PWM) method. Its popularity is due to its simplicity ad to the good results it guaratees at all operatig coditios, icludig over-modulatio, which allows the first harmoic. It ca be used for ay MLI ad ca be easily implemeted. For a m-level iverter, m-1 carrier (triagular) waves with same amplitude ad frequecy are required. The frequecy modulatio idex, which is the ratio of the carrier frequecy to the modulatig sigal frequecy, is expressed by equatio (1). f cr m f = (1) f m Where, f m is the frequecy of the modulatig sigal ad f cr is the frequecy of the carrier waves. The amplitude modulatio idex ma is defied by equatio (). vm ma = () v ( m 1) cr Figure-4. PD modulatio scheme for the seve-level MLIs are simulated for a star coected RL load of 50+j7.53 Ω/phase. Figures 5 ad 6 show the output voltage ad output curret waveforms of the three-phase seve-level NPC Figures 7 ad 8 show the output voltage ad output curret waveforms of the three-phase seve-level FLC Figures 9 ad 10 show the output voltage ad output curret waveforms of the three-phase seve-level CHB iverter with separate DC sources. Where, vm is the peak value of the modulatig wave ad v cr is the peak value of each carrier wave. Four carrier PWM strategies, available i literature, with differet phase relatios are [4-7]: a) Phase Dispositio (PD) b) Phase Oppositio Dispositio (POD) c) Alterate Phase Oppositio Dispositio (APOD) d) Phase Shift (PS). I this paper, PD modulatio scheme is used for pulse geeratio because it provides the lowest harmoic distortio for lie voltages [8]. Figure-5. Simulated output voltage of the NPC 4. SIMULATION USING MATLAB Seve-level three-phase NPC, FLC ad covetioal CHB MLIs are simulated with MATLAB for a RL load. I PD techique, for a m level iverter, m-1 carrier waves are used which are i phase with each other. These carrier waves are arraged to have vertical shifts. Hece, for a seve-level iverter six carrier waves are used to geerate the switchig pulses. These six carrier waves are compared with a referece to obtai the switchig pulses. The PD scheme is show i Figure-4. Figure-6. Simulated output curret of the NPC 1547

Figure-7. Simulated output voltage of the FLC Figure-10. Simulated output curret of the traditioal CHB 5. COMPARISON OF THE THDs The FFT aalysis obtaied by simulatig MLIs are show for the three cofiguratios. Figures 11 ad 1 respectively show the FFT aalysis for the phase a output voltage ad output curret for the NPC Figures 13 ad 14 respectively show the FFT aalysis of the phase a output voltage ad output curret for the FLC Figures 15 ad 16 respectively show the FFT aalysis of the phase a output voltage ad output curret for the covetioal CHB Figure-8. Simulated output curret of the FLC Figure-11. FFT aalysis of the output voltage of the NPC Figure-9. Simulated voltage of the traditioal CHB Figure-1. FFT aalysis of the output curret of the NPC 1548

respectively. The THD for four cycles of the output curret of NPC, FLC, ad traditioal CHB are %, 10.37%,.13%, respectively. Figure-17 shows the voltage ad curret THDs for all the three iverters. 30.00% 5.00% Figure-13. FFT aalysis of the output voltage of the NPC 0.00% 15.00% 10.00% 5.00% 0.00% Voltage THD Curret THD NPC iverter FLC Iverter Traditioal CHB Iverter Figure-14. FFT aalysis of the output curret of the FLC Figure-15. FFT aalysis of the output voltage of the covetioal CHB Figure-17. Voltage ad curret THDs for the NPC, FLC, ad CHB iverters. From the simulated waveforms, it is see that for high power applicatios, CHB iverter is better suited as its fudametal output voltages ad currets are high. I additio, the CHB iverter requires less umber of compoets compared to the NPC ad the FLC iverters. However, the CHB iverter has the disadvatage of requirig separate DC sources for each level, which icreases the cost of the This disadvatage is ot preset i the proposed CHB MLI as it uses oly a sigle DC source. The simulatio time, for four cycles of output, for the three MLI cofiguratios, vary betwee 1.5 s ad.5 s, ad is give i the Table-1. It ca be see that simulatio time for the CHB MLI of 1.75 s is comparable to the least simulatio time take by the FLC MLI, which is 1.5 s. Table-1. Simulatio time for four cycles of output for the three iverters. Type of iverter Simulatio time i secods (s) NPC MLI FLC MLI CHB MLI.5 1.5 1.75 Figure-16. FFT aalysis of the output curret of the traditioal CHB From Figures 11-16, it ca be see that the THD for four cycles of the output voltage for the NPC, FLC, ad traditioal CHB are 9.61%, 8.34%, ad 9.5%, 6. CHB MLI WITH A SINGLE DC SOURCE Figure-18 shows the proposed sigle-phase seve-level CHB MLI that uses a sigle DC source. The output of the iverter is coected through trasformers to the load. The iverter uses three trasformers per phase, the secodary of each trasformer beig coected i series. The load is coected across the series coected secodary of the trasformer [9-11]. 1549

Figure-1. FFT aalysis of the output voltage of the proposed CHB Figure-18. Seve-level CHB iverter with a sigle DC Source. The proposed seve-level three-phase CHB iverter is simulated i MATLAB. Output voltage ad curret waveforms are show i Figures 19 ad 0, respectively. Figure-. FFT aalysis of the output curret of the proposed CHB Figures 3-34 show the switch currets ad switch voltages for 1 switches of oe leg (phase) of the proposed CHB Figure-19. Simulated output voltages of the proposed CHB Figure-3. Switch curret ad voltage for S 1. Figure-0. Simulated output currets of the proposed CHB The FFT aalysis of the output voltage ad the output curret, obtaied by simulatio of the proposed CHB iverter, is show i Figures 1 ad, respectively. Figure-4. Switch curret ad voltage for S. 1550

Figure-5. Switch curret ad voltage for S 3. Figure-9. Switch curret ad voltage for S 3. Figure-6. Switch curret ad voltage for S 4. Figure-30. Switch curret ad voltage for S 4. Figure-7. Switch curret ad voltage for S 1. Figure-31. Switch curret ad voltage for S 1. Figure-8. Switch curret ad voltage for S. Figure-3. Switch curret ad voltage for S. 1551

Z is the per phase load impedace give by equatio (6) ad φ is the power factor agle give by equatio (7). Z = ( R + ( ωl) (6) Figure-33. Switch curret ad voltage for S 3. ωl φ ta 1 = ( ) (7) R The rms value of the phase curret I a is give by equatio (8). Figure-34. Switch curret ad voltage for S 4. Figure-1 shows that the THD of the output voltage of the proposed CHB iverter is 9.65% ad Figure- shows that the THD of the output curret of the proposed CHB iverter is.11%. The voltage THD of the proposed iverter is slightly higher tha that of the covetioal CHB iverter ad the curret THD of the proposed CHB iverter is slightly lower tha that of the covetioal CHB The proposed CHB may be cosidered better as it costs less due to the requiremet of oly oe DC source, with performace comparable to the covetioal CHB 7. OUTPUT POWER CALCULATION The Fourier series expasio of the phase voltage of the CHB iverter is give by equatio (3) [1]. v a 3 4V DC = [ cos( α j )]si( ωt) (3) π j= 1 Where α is the coductio agle ad = 1, 5, 7, etc. The Fourier series expasio of the phase curret, which is also the lie curret for the star coected load, is give by equatio (4). 4 3 VDC ia = [ cos( α j )]si( ωt φ ) (4) πz j= 1 The equatio (4) ca be rewritte as give by equatio (5). 3 ia = I [ cos( α j )]si( ωt φ ) (5) Where I j= 1 4V = πz DC = I 1 I = a (8) The output power is give by equatio (10) P out = 3I R (9) a For the covetioal CHB iverter, the rms value of the phase curret is 8.8 A. The output power is give by: P out = 3*8.8 = 1084 W *50 For the proposed CHB iverter, the rms value of the phase curret is foud to be 8.7 A. Hece, the output power is give by: P out = 3*8.7 = 1059 W *50 8. COMPARISON OF CHB MLI HAVING SEPARATE DC SOURCES WITH CHB MLI HAVING A SINGLE DC SOURCE The two CHB iverters are simulated i MATLAB with PD modulatio with a star coected RL load of 50+j7.53 Ω/phase. The output voltage, output curret ad FFT aalysis of voltage ad curret waveforms of the CHB iverter with separate DC sources were show i the Figures 9, 10, 15 ad 16 respectively. Figures 19-1 show the output voltage, output curret, ad FFT aalysis of voltage ad curret of CHB with a sigle DC source. Table- shows the compariso of the proposed CHB iverter with the covetioal MLI. From Table-, it ca be see that THD values ad power output of the CHB MLI are comparable with the covetioal oe. It requires oe DC source, which reduces the cost of the proposed CHB 155

9. PARAMETERS FOR PROPOSED CHB Iput DC Voltage VDC = 00 V Load Impedace/phase = 50+j7.53 Ω IGBT/Diode voltage/curret ratig = 400 V/15A Trasformer ratig = 00V/00V, 15A/15A Table-. Compariso of the covetioal ad the proposed CHBs. Parameters Covetioal CHB MLI Proposed CHB MLI No. of DC sources required Nie DC sources Oe DC source Number of IGBT/Diode pairs 36 36 Voltage THD 9.5 % 9.65 % Curret THD.13 %.11 % Output power 1084 W 1059 W Cost US $ 5,500 US $ 3,600 Voltage ratig of power switches 400 V 400 V Curret ratig of power switches 15 A 15 A 10. CONCLUSIONS The simulatio of three Multi-level Iverters (MLIs) amely the Neutral Poit Clamped (NPC), the Flyig Capacitor (FLC) ad the Cascaded H-Bridge (CHB) is preseted i this paper. These iverters are simulated i MATLAB usig multi-carrier sie pulse width modulatio (MCPWM) techique. The simulated output voltage ad curret waveforms for a RL load are show for the three cofiguratios ad the total harmoic distortio (THD) is compared. For high power applicatios, CHB iverter is better suited as its fudametal output voltages ad currets are high. I additio, the CHB iverter requires less umber of compoets compared to the NPC ad the FLC iverters. However, the CHB iverter has the disadvatage of requirig separate DC sources for each level, which icreases the cost of the The proposed Cascaded H-Bridge with a sigle DC source is simulated i MATLAB usig multi-carrier sie pulse width modulatio (MCPWM) techique. The simulated output voltage ad curret waveforms, FFT aalysis ad switchig voltages ad currets for a RL load are show for the proposed Cascaded H-Bridge with a sigle DC source. The total harmoic distortio (THD), output power ad the cost for the two CHB Iverter cofiguratios are compared. The proposed CHB iverter does ot require separate DC sources ad hece the cost of the system is lesser. I additio, this system elimiates the possibility of short circuit of the DC sources, which may occur i the covetioal CHB REFERENCES [1] Hog Zheg, Baohua Zhag ad Ligkui Che. 010. Carrier Overlappig-switchig Frequecy optioal PWM Method for Cascaded Multilevel Iverter. I: Iteratioal Coferece o Electrical ad Cotrol Egieerig. 5-7 Jue. pp. 3450-3453. [] Peg F. Z., Lai J., McKeever J. W. ad VaCoeverig J. 1996. A multilevel voltage-source iverter with separate DC sources for static var geeratio. I: IEEE Trasactios o Idustry Applicatios. 3(5): 1130-1138. [3] Majrekar M., Steimer P. K. ad Lipo T. 000. Hybrid multilevel power coversio system: A competitive solutio for high-power applicatios. I: IEEE Trasactios o Idustry Applicatios. 36(3): 834-84. [4] Urmila B ad Subbarayudu D. 010. Multi level Iverter: A Comparative Study of Pulse Width Modulatio Techiques. I: Iteratioal Joural of Scietific ad Egieerig research. 1(3): -5. [5] Ilhami Colak, Ersa Kabalci ad Ramaza Bayidir. 011. Review of multilevel voltage source iverter topologies ad cotrol schemes. I: Itera Joural o Eergy Coversio ad Maagemet. 5(): 1114-118. [6] Wajekeche T., V.Nicolae D. ad Jimoh A.A. 009. Realizatio of a Nie - Level Cascaded NPC/ H- 1553

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