Instituto Tecnológico y de Estudios Superiores de Occidente (), OBJECTIVES The general objective of this experiment is to contrast the practical behavior of a real differential pair with its theoretical version. Other more specific objectives are: a) to reinforce the notion of common-emitter half circuits in the process of design and analysis of a differential amplifier b) to verify the differential and common mode operation c) to design a current mirror and apply it to bias a differential pair. Join nodes C and D (which should have nearly the same voltage) and measure again the voltages on nodes A through F. Note that they are virtually the same as before. With nodes C and D joined, A unchanged and B connected via a 1MΩ resistor to the center of a 1KΩ potentiometer, Rp, connected between 15V and 10.7V, measure the voltage between nodes E and F, Adjust Rp until this is exactly zero. Measure the voltages at A through F and P (the center of Rp). You have in effect compensated for the total input offset including the voltage offset resulting from base-emitter mismatch, and the difference in bias-current flow (i.e., offset current) in the base resistors RB. What is the total input offset voltage and the average offset current? APPROACH Theoretical Procedure, Part A -----------------------------------------------------------------------------------------Calculate all the DC voltages and currents in the two differential half-circuits shown in Fig. 1 (refer to the appendix for the internal parameters of the transistors). Lab Procedure, Part A -----------------------------------------------------------------------------------------Assemble the circuit of Fig. 1 using resistors that are as wellmatched as you can make them (use your digital ohmmeter if necessary). Please note that in the 3046 array pin 13 must be connected to the most negative voltage supplied to any of the devices, since all the devices in this chip are fabricated on a common substrate. Create a table to display the voltages on nodes A through F before and after the compensation procedure. Label this table as Table II. Theoretical Procedure, Part B -----------------------------------------------------------------------------------------Calculate the voltage gain from A to E (ve/va) for the circuit shown in Fig. 2 (refer to the appendix for the internal parameters of the transistors). Calculate the input impedance at node A. Calculate the voltage gain from A to E (ve/va) when node B is not grounded and connected to node A (common-mode operation). Fig. 2: Simple differential amplifier. Lab Procedure, Part B -----------------------------------------------------------------------------------------Fig. 1: Two differential half-circuits. Measure the voltages at nodes A through F. From these measurements calculate the currents in all the branches as well as α1, α2, β1 and β2, as well as VBE1 and VBE2. Create a table to compare these results with your theoretical results previously calculated. Label this table as Table I. Assemble the circuit of Fig. 2. Connect a generator to provide a sine wave of 1Vpp at 1KHz at node G. Using a two-channel oscilloscope, measure the voltage gain from A to E (ve/va). Plot va, ve and vf as they appear in the oscilloscope. Why was the voltage divider of 10KΩ-100Ω added to the circuit? Measure the input impedance at node A (after the 100Ω resistor). Describe the method used to measure this impedance. Subject: Analog Electronic Circuits - Page 1 of 8
Instituto Tecnológico y de Estudios Superiores de Occidente (), Measure the voltage gain from A to E (ve/va) when node B is not grounded and connected to node A (common-mode operation). Plot va, ve and vf as they appear in the oscilloscope. Create a table to compare this results with your theoretical results previously calculated (voltage gains and input impedance). Label this table as Table III. Theoretical Procedure, Part C ------------------------------------------------------------------------------------------ COMPONENTS Circuit Simulation Software (SPICE). LM3046 (Fig. 3) x1 (BJT npn transistor array). Several resistors (1% tolerance if possible). 1kΩ Potentiometer x1. Two variable DC power supplies (0 to 20 V). Waveform generator. Digital multimeter. Two-channel oscilloscope with X10 probes. Design a differential amplifier biased with a current mirror (choose any configuration of current mirror) using the transistors available in a single chip 3046. Refer to the appendix for the internal parameters of the transistors. Your design must fulfill the following specifications: A) ICMR ±100mV B) Output Voltage Swing ±5V C) AVd > 40dB D) CMRR > 60dB Lab Procedure, Part C -----------------------------------------------------------------------------------------Implement your designed differential amplifier biased with a current mirror. Measure the DC voltages on all the nodes and calculate from them all currents in the circuit. Fig. 3: LM3046 - Top View What are the resulting AVd, CMRR, Slew Rate, Offset, and Power Consumption values? Plot the corresponding waveforms as seen in the oscilloscope and create a table to compare your theoretical predictions with your lab measurements. Label this table as Table IV. Subject: Analog Electronic Circuits - Page 2 of 8
Instituto Tecnológico y de Estudios Superiores de Occidente (), EXPLANATION Many electronic devices use differential amplifiers internally. Implementations consist of a differential input stage (Fig. 5) followed by single or multiple amplification stages. We can also clearly amplify the signal with this type of circuits, by mounting a small-signal on one input and measuring the outv C1 C2 we are are removing the common portion of put at the signal at the input while getting an amplified version of the small-signal. This mode is called differential (Fig. 4). Differential amplifiers are widely used because of their high tolerance to noise. Fig. 4: Comparative in modes. Fig. 5: Differential amplifier in common mode. Having an input in the circuit ( V B1 and V B2 ) and the out- put at V C1 C2 we can clearly see how the common component gets removed at the output as the transistors match in physical characteristics. This operation mode is called common (Fig. 4). It can be seen clearly as a big advantage as coupled signal noise is common at the input. The relationship between the gain of the common and differential modes is called the Common Mode Rejection Ratio (CMRR) and is defined as: CMRR= AVD ACM As we have already seen in multi-stage amplifiers, the concept is to take the best features of the different topologies of amplifiers for specific applications. The higher the CMRR the higher tolerance our amplifier has to noise. That is clearly a something to take onto consideration in medical instrumentation or places with high electromagnetic emissions for example. Fig. 6: MOS (left) and BJT (right) differential amplifiers. Implementing this type of circuit is as easy as putting together two common-emitter (BJT) or two common-drain (MOS) amplifiers facing against each other (Fig. 6). Subject: Analog Electronic Circuits - Page 3 of 8
Instituto Tecnológico y de Estudios Superiores de Occidente (), PROCEDURE First are going to start by measuring some internal transistor parameters needed for our calculations by assembling the circuit and measuring the currents and voltages. Lab Procedure, Part A -----------------------------------------------------------------------------------------According to the next differential amplifier circuit (Fig. 7) The most important and influential parameters would be =1046.80 and V BE =0.728[V ], for easier calculation we will be using a normalized value of beta after seeing the measurements under this section (Lab Procedure, Part A). ####################### PSPICE Model for the LM3046 ###################### ##########################################################################.model LM3046 NPN IS=10e-15 BF=1046.80 XTI=3E00 VAR=1.00E2 IKF=46.7E-03 EG=1.110E00 VAF=1.00e02 ISE=114.286E-15 NE=1.48E00 XTB=0 BR=0.1 ISC=10.005e-15 NC=2 IKR=10e-3 RC=10 MJC=.333 VJC=.75 FC=5.00e-01 CJE=1.02e-12 MJE=.336 VJE=.728 TR=10e-9 TF=277.01e-12 ITF=1.75 XTF=309.38 VTF=16.37) Fig. 7: DC Parameters. ########################################################################## The measured parameters in DC (Fig. 7) are: Theoretical Procedure, Part A -----------------------------------------------------------------------------------------DC currents analysis relationship using the normalized beta gives us: = =0.9990456 1 10.7 0.728 ie = =1.0124[mA ] 9.85x10 3 i c = i e =1.0114[mA ] and V E = 0.728[V ] Currents: E i c =0.995[mA ] A i b=9.300[ua] C i e =0.994 [ma] and as F i c=0.993[ma] B i b=9.700 [ua] D i e =0.992[mA ] Voltages: then V AE = 4.81[V ] V AC = 0.72 [V ] V EC = 6.10 [V ] i b 1[uA] The voltages in the nodes are the result of the resistors and end up as: V B=10 [mv ] Table I V C =5.0375[V ] V FB= 5.19[V ] V BD = 0.72[V ] V FD = 6.07 [V ] Thus obtaining the betas for each transistor: 1=1069.89 and 2=1023.71 After joining nodes C and D we proceed to measure again. Meaning that the voltages in the nodes according to our diagram (Fig. 7) Table II V AE = 5.0275[V ] V AC = 0.680 [V ] V EC = 6.08[V ] V FB = 5.0275 [V ] V BD = 0.718[V ] V FD= 6.391[V ] Voltages: V AE = 5.360[V ] V AC = 0.680 [V ] V EC = 6.08[V ] V FB= 5.600[V ] V BD = 0.710[V ] V FD= 6.09[ V ] Subject: Analog Electronic Circuits - Page 4 of 8
Instituto Tecnológico y de Estudios Superiores de Occidente (), Comparing Table I vs. Table II we can clearly notice the difference is minimal but having the nodes joined gives us even less of a difference between the differential halves. After implementing the voltage divider with the potentiometer we obtain the offset needed to get both transistors working ideally for common-mode: V offset =394 [mv ] ma Joining nodes C and D. therefore i c =1.9925[mA ] and meaning the transconductance is i b=1.9052 [ua] g m= ic =39.85[mA/V ] 2VT i offset =0.5[uA] Summarizing the values measured on a Table III for easier comparative. Regular (two half diff. Circuits). with the transconductance defined we are able to calculate the common mode gain and differential gain. Diff. Gain AVD = g m RC = 398.5[V /V ] Comm. Gain ACM = V 3 RC 10x = =1[V /V ] 2R EE 2 5x103 (E) ic 0.995 AE 4.81 (A) ib 9.300 AC -0.72 (C) ie 0.994 FC -6.10 (F) ic 0.993 FB 5.19 (B) ib 9.700 BD 0.72 (D) IC 0.992 FD -6.07 (E) ic 0.995 AE 5.36 (A) ib 9.300 AC -0.68 Voltages in the nodes according to Fig. 2: (C) ie 0.994 FC -6.08 Differential Mode (Small-Signal) - (F) ic 0.993 FB 5.60 (B) ib 9.700 BD -0.71 (D) IC 0.992 FD -6.09 Lab Procedure, Part B -----------------------------------------------------------------------------------------In the differential amplifier implementation of the circuit we proceed to measure the calculations done earlier. V E =172 mv V A=16.8 mv Gain: V A=200 mv AVD =10.23[V /V ] Table III Measurements. Common Mode (DC) Theoretical Procedure, Part B -----------------------------------------------------------------------------------------As we implement the (Fig. 8) with the voltage divider. V A=3.2 mv V E =6.00 mv Gain: V A=6.00 mv ACM =1.875[V / V ] Comparative of the calculations and the measurements below (Table IV). Common Mode Differential Mode Calculations 2 10.23 Measurements 1 398.5 Table IV Overview in the results of part B. Fig. 8: Differential amplifier. We can clearly see that ie = 10.7 0.728 =1.9944[mA ] 5x10 3 Subject: Analog Electronic Circuits - Page 5 of 8
Instituto Tecnológico y de Estudios Superiores de Occidente (), Theoretical Procedure, Part C -----------------------------------------------------------------------------------------As we know the specifications of our design are the following: A) ICMR ±100mV B) Output Voltage Swing ±5V C) AVd > 40dB D) CMRR > 60dB So before even defining the topology to work with, we already need a minimum common-mode gain of: ACM 10 2 1 =10 =0.1 3 10 Then we define the current of polarization in the circuit as 1 ma meaning the transconductance is: g m= ic =20 [ma/v ] 2VT And if we want a differential gain of at least 100 [V/V] so if we define RC =10[ K ] then AVD =200[V /V ] The design implemented is the circuit in the schematic in Fig. 10. The next graph (Fig. 9) shows the gain curve. 200 Fig. 10: Amplifier Design (Part C) 150 100 50 1.0Hz 100Hz V(Q9:c)/V(Q14:b) 10KHz 1.0MHz 100MHz Frequency Fig. 9: Differential mode gain simulation with SPICE Subject: Analog Electronic Circuits - Page 6 of 8
Instituto Tecnológico y de Estudios Superiores de Occidente (), Lab Procedure, Part C -----------------------------------------------------------------------------------------After implementing the circuit with two LM3046 ICs, we take the oscilloscope and measure the parameters of our required specifications. With those two values we can easily calculate the CMRR and get: CMRR=110/414X10 6=265700[V /V ]=108 db. Note: Ch1: Output // Ch2: Input Fig. 13: Voltage swing. Fig. 11: Differential mode. Figure 11 shows the results of the differential gain having a value of A VD =110[V /V ]=40dB. Fig. 14: Distortion. Fig. 14 shows how as the input goes above 100mV the signal distorts giving valid proof of the following equation: ICMR=4V T = 100mV Fig. 12: Common mode. Fig. 12 gives us ACM =414x10 6 [V /V ]= 67.65 db. After looking at the photographs and calculations we can clearly validate how our design was successful in every specification. Subject: Analog Electronic Circuits - Page 7 of 8
Instituto Tecnológico y de Estudios Superiores de Occidente (), CONCLUSIONS We practiced BJT analysis concepts to calculate the DC operating values, small signal variations and gain. Using those same concepts from the Analog Electronic Devices course we were able to get the internal parameters of our transistors. After having done the calculations to get an idea of how the circuit was going to behave and by using SPICE for simulation after defining our own model of the transistors to approach real life results we were quite close to the results and the design was even easier. One thing that drew our attention was the small variation needed to destabilize and unbalance the currents. This small variation was enough for the common-mode to stop working ideally. BIBLIOGRAPHY A.R. Hambley, Electronics: A Top-Down Approach to ComputerAided Circuit Design, Englewood Cliffs, NJ : Prentice Hall, 2000. R.C. Jager, Microelectronic Circuit Design, New York, NY: McGraw Hill, 1997. Malvino, Albert, Electronic Principles, 6th Edition, McGraw Hill, 1999. A. S. Sedra and K. C Smith, Microelectronic Circuits. New York, NY: Oxford University Press, 2003. Subject: Analog Electronic Circuits - Page 8 of 8