INA6 INA6 INA6 Ultra Low Input Bias Current INSTRUMENTATION AMPLIFIER FEATURES LOW INPUT BIAS CURRENT: fa typ BUFFERED GUARD DRIVE PINS LOW OFFSET VOLTAGE: mv max HIGH COMMON-MODE REJECTION: db () LOW QUIESCENT CURRENT: ma INPUT OVER-VOLTAGE PROTECTION: ±V APPLICATIONS LABORATORY INSTRUMENTATION ph MEASUREMENT IONSPECIFIC PROBES LEAKAGE CURRENT MEASUREMENT DESCRIPTION The INA6 is a complete monolithic FET-input instrumentation amplifier with extremely low input bias current. Difet inputs and special guarding techniques yield input bias currents of fa at C, and only fa at C. Its -op amp topology allows gains to be set from to by connecting a single external resistor. pins adjacent to both input connections can be used to drive circuit board and input cable guards to maintain extremely low input bias current. The INA6 is available in 6-pin plastic DIP and SOL-6 surface-mount packages, specified for the C to C temperature range. V Over-Voltage Protection A kω 6kΩ 6kΩ INA6 kω 6 6 7 Over-Voltage Protection A kω 6kΩ A 6kΩ Difet ; Burr-Brown Corporation V International Airport Industrial Park Mailing Address: PO Box, Tucson, AZ 7 Street Address: 67 S. Tucson Blvd., Tucson, AZ 76 Tel: () 76- Twx: -- Internet: http://www.burr-brown.com/ FAXLine: () -6 (US/Canada Only) Cable: BBRCORP Telex: 66-6 FAX: () - Immediate Product Info: () -6 Burr-Brown Corporation PDS-B Printed in U.S.A. May,
SPECIFICATIONS AT T A = C, V S = ±V, R L = kω, unless otherwise noted. INA6P, U INA6PA, UA PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS INPUT Offset Voltage, RTI Initial T A = C ±. ±./G ± ±/G ± ±/G mv vs Temperature T A = T MIN to T MAX See Typical Curve vs Power Supply V S = ±.V to ±V ± ±/G ± ±/G ± ±/G µv/v Long-Term Stability ± ±/G µv/mo Bias Current ± ± ± fa vs Temperature See Typical Curve Offset Current ± ± ± fa vs Temperature See Typical Curve Impedance, Differential > /. Ω/pF Common-Mode > /7 Ω/pF Common-Mode Voltage Range (V) (V) V (V) (V). V Safe Input Voltage ± V Common-Mode Rejection V CM = ±V, R S = kω 7 db 7 db 6 db V CM = ±V, 6 db NOISE Voltage Noise, RTI, R S = Ω f = khz nv/ Hz f B =.Hz to Hz µvp-p Current Noise f = khz. fa/ Hz GAIN Gain Equation (kω/ ) V/V Range of Gain V/V Gain Error ±. ±.. % ±. ±. ±. % ±. ±. ±.7 % ±. % Gain vs Temperature () ± ± ± ppm/ C kω Resistance ()() ± ± ± ppm/ C Nonlinearity ±. ±. ±. % of FSR ±. ±. ±. % of FSR ±. ±. ±. % of FSR ±. % of FSR GUARD OUTPUTS Offset Voltage ± ± mv Output Impedance 6 Ω Current Drive /. ma OUTPUT Voltage Positive R L = kω (V) (V).7 V Negative R L = kω (V). (V). V Load Capacitance Stability pf Short-Circuit Current / ma FREQUEY RESPONSE Bandwidth, db khz khz 7 khz 7 khz Slew Rate to. V/µs Settling Time,.% V Step, µs µs µs µs Output Overload Recovery % Overdrive µs POWER SUPPLY Voltage Range ±. ± ± V Current = V ± ±. ma TEMPERATURE RANGE Specification C Operating C θ JA C/W Specification same as INA6P NOTE: () Guaranteed by wafer test. () Temperature coefficient of the kω term in the gain equation. INA6
PIN CONFIGURATION Top View V : No Internal Connection. ABSOLUTE MAXIMUM RATINGS 6 7 DIP SOL-6 Supply Voltage... ±V Input Voltage Range... ±V Output Short-Circuit (to ground)... Continuous Operating Temperature... C to C Storage Temperature... C to C Junction Temperature... C Lead Temperature (soldering, s)... C 6 V ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE INFORMATION PACKAGE DRAWING PRODUCT PACKAGE NUMBER () INA6PA 6-Pin Plastic DIP INA6P 6-Pin Plastic DIP INA6UA SOL-6 Surface-Mount INA6U SOL-6 Surface-Mount NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. INA6
TYPICAL PERFORMAE CURVES At T A = C, V S = ±V, R L = kω, unless otherwise noted. Gain (db) GAIN vs FREQUEY 6 k k k M M Common-Mode Rejection (db) COMMON-MODE REJECTION vs FREQUEY V/V V/V 7 6 V/V V/V k k k POSITIVE POWER SUPPLY REJECTION vs FREQUEY NEGATIVE POWER SUPPLY REJECTION vs FREQUEY Power Supply Rejection (db) 6 V/V V/V V/V V/V Power Supply Rejection (db) 6 < k k k k k k k INPUT BIAS CURRENT vs INPUT VOLTAGE INPUT BIAS CURRENT vs TEMPERATURE Input Bias Current (fa) Input Bias Current (fa) I B I OS Input Voltage (V) Measurement Limit 7 7 INA6
TYPICAL PERFORMAE CURVES (CONT) At T A = C, V S = ±V, R L = kω, unless otherwise noted. Common-Mode Voltage (V) INPUT COMMON-MODE RANGE vs OUTPUT VOLTAGE G G V V D/ V O INA6 V D/ V CM V Output Voltage (V) Voltage Noise Density (nv/ Hz) k k INPUT REFERRED NOISE vs FREQUEY V/V V/V V/V k Bandwidth Limit k Input Current (ma) INPUT OVER-VOLTAGE V/I CHARACTERISTICS V/V V/V V/V V/V Input Voltage (V) Offset Voltage Change (µv) OFFSET VOLTAGE WARM-UP G G Time After Power Supply Turn-On (s) Production Distribution (%) INPUT OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION.. 7 6 6 6 Offset Voltage Drift (µv/ C) 6 7.. Quiescent Current (µa).6.....6. 7 QUIESCENT CURRENT AND SLEW RATE vs TEMPERATURE I Q SR Temperature ( C).....6. 7 Slew Rate (V/µs) INA6
TYPICAL PERFORMAE CURVES (CONT) At T A = C, V S = ±V, R L = kω, unless otherwise noted. MAXIMUM OUTPUT VOLTAGE vs FREQUEY, VOLTAGE NOISE,. TO Hz INPUT-REFERRED, G Peak-to-Peak Output Voltage (V) 6 nv/div k k k M s/div SMALL SIGNAL RESPONSE SMALL SIGNAL RESPONSE G= G= mv/div mv/div G= G= µs/div µs/div LARGE SIGNAL RESPONSE LARGE SIGNAL RESPONSE G= G= V/div V/div G= G= µs/div µs/div INA6 6
APPLICATIONS INFORMATION Figure shows the connections required for basic operation of the INA6. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the supply pins as shown. The output is referred to the output reference () terminal which is normally grounded. This must be a low impedance connection to assure good common-mode rejection. A resistance of Ω in series with this connection will cause a typical device to degrade to approximately 7dB CMR at. SETTING THE GAIN Gain of the INA6 is set by connecting a single external resistor,, as shown. The gain is kω () Commonly used gains and resistor values are shown in Figure. The kω term in equation is the sum of the two feedback resistors of A and A. These on-chip metal film resistors are laser trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the INA6. The stability and temperature drift of also affect gain. s contribution to gain accuracy and drift can be directly inferred from the gain equation (). Low resistor values required for high gain make wiring resistance important. Sockets add to the wiring resistance that will contribute additional gain error in gains of approximately or greater. OFFSET TRIMMING The INA6 is laser trimmed for low offset voltage and offset voltage drift; most applications require no external offset adjustment. Figure shows an optional circuit for trimming the output offset voltage. A voltage applied to the terminal is summed at the output. Op amp A provides a low source impedance for the terminal, assuring good common-mode rejection. V.µF Over-Voltage Protection A R FB kω R 6kΩ R 6kΩ INA6 kω Input s See Text. 6 6 7 Over-Voltage Protection A R FB kω R 6kΩ A R 6kΩ.µF DESIRED GAIN (Ω).k.k.6k.6k.k....... : No Connection. NEAREST % (Ω).k.k.6k.6k.k... V Also drawn in simplified form: INA6 FIGURE. Basic Connections. 7 INA6
INA6 OPA ±mv Adjustment Range NOTE: () For wider trim range required in high gains, scale resistor values larger V kω () V µa / REF Ω () Ω () µa / REF CIRCUIT BOARD LAYOUT AND ASSEMBLY Careful circuit board layout and assembly techniques are required to achieve the exceptionally low input bias current performance of the INA6. terminals adjacent to both inputs make it easy to properly guard the critical input terminal layout. Since traces are not required to run between device pins, this layout is easily accomplished, even with the surface mount package. The guards should completely encircle their respective input connections see Figure. Both sides of the circuit board should be guarded, even if only one side has an input terminal conductor. Route any timevarying signals away from the input terminals. Solder mask should not cover the input and guard traces since this can increase leakage. FIGURE. Optional Trimming of Output Offset Voltage. INPUT BIAS CURRENT RETURN PATH Input circuitry must provide an input bias current path for proper operation. Figure shows resistors R and R to provide an input current path. Without these resistors, the inputs would eventually float to a potential that exceeds the common-mode range of the INA6 and the input amplifiers would saturate. Because of its exceedingly low input bias current, improperly biased inputs may operate normally for a period of time after power is first applied, or operate intermittently. Crystal or Ceramic Transducer Capacitive Sensor MΩ Polarizing Voltage MΩ R MΩ MΩ R MΩ R MΩ R INA6 INA6 Top and Bottom of Circuit Board. FIGURE. Circuit Board Layout. After assembly, the circuit board should be cleaned. Commercial solvents should be chosen according to the soldering method and flux used. Solvents should be cleaned and replaced often. Solvent cleaning should be followed by a deionized water rinse and C bake out. Sockets can be used, but select and evaluate them carefully for best results. Use caution when installing the INA6 in a socket. Careless handling can contaminate the plastic near the input pins, dramatically increasing leakage current. A proven low leakage current assembly method is to bend the input pins outward so they do not contact the circuit board. Input connections are made in air and soldered directly to the input pin. This technique is often not practical or production-worthy. It is, however, a useful technique for evaluation and testing and provides a benchmark with which to compare other wiring techniques. The circuit board guarding techniques discussed normally reduce leakage to acceptable levels. A solid mechanical assembly is required for good results. Nearby plastic parts can be especially troublesome since a static charge can develop and the slightest motion or vibration will couple charge to the inputs. Place a Faraday shield around the whole amplifier and input connection assembly to eliminate stray fields. FIGURE. Providing An Input Bias Current Path. INA6
INPUT CONNECTIONS Some applications must make high impedance input connections to external sensors or input connectors. To assure low leakage, the input should be guarded all the way to the signal source see Figure. Coaxial cable can be used with the shield driven by the guard. A separate connection is required to provide a ground reference at the signal source. Triaxial cable may reduce noise pickup and provides the ground reference at the source. Drive the inner shield at guard potential and ground the outer shield. Two separate guarded lines are required if both the inverting and non-inverting inputs are brought to the source. The guard drive output current is limited to approximately ma/µa. For slow input signals the internal guard output can directly drive a cable shield. With fast input signals, however, the guard may not provide sufficient output current to rapidly charge the cable capacitance. An op amp buffer may be required as shown in Figure 6. High-Z Source V Two coaxial cables and ground MΩ High-Z Source V Two triaxial cables MΩ FIGURE. Input Cable ing Circuits. Circuit Board Op amp buffer helps guard cables with fast input signals see text. Cable Ω OPA.6kΩ 6 6 INA6 FIGURE 6. Buffered Drive. Solution Ground Sample Electrode erence Electrode FIGURE 7. ph or Ion Measurement System. INA6