Applications l High frequency DC-DC converters SMPS MOSFET PD - 94392 IRFR24N5D IRFU24N5D HEXFET Power MOSFET V DSS R DS(on) max I D 50V 95mΩ 24A Benefits Low Gate-to-Drain Charge to Reduce Switching Losses Fully Characterized Capacitance Including Effective C OSS to Simplify Design, (See App. Note AN0) Fully Characterized Avalanche Voltage and Current l l l D-Pak IRFR24N5D I-Pak IRFU24N5D Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 24 I D @ T C = 0 C Continuous Drain Current, V GS @ V 7 A I DM Pulsed Drain Current 96 P D @T C = 25 C Power Dissipation 40 W Linear Derating Factor 0.92 W/ C V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 4.9 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range Soldering Temperature, for seconds 300 (.6mm from case ) C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case. R θja Junction-to-Ambient (PCB mount)* 50 C/W R θja Junction-to-Ambient Notes through are on page www.irf.com 03/4/02
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 50 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.8 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 82 95 mω V GS = V, I D = 4A V GS(th) Gate Threshold Voltage 3.0 5.0 V V DS = V GS, I D = 250µA 25 V µa DS = 50V, V GS = 0V I DSS Drain-to-Source Leakage Current 250 V DS = 20V, V GS = 0V, T J = 50 C Gate-to-Source Forward Leakage 0 V GS = 30V I GSS na Gate-to-Source Reverse Leakage -0 V GS = -30V Dynamic @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 8.2 S V DS = 25V, I D = 4A Q g Total Gate Charge 30 45 I D = 4A Q gs Gate-to-Source Charge 7.4 nc V DS = 20V Q gd Gate-to-Drain ("Miller") Charge 7 26 V GS = V, t d(on) Turn-On Delay Time V DD = 75V t r Rise Time 53 ns I D = 4A t d(off) Turn-Off Delay Time 9 R G = 6.8Ω t f Fall Time 5 V GS = V C iss Input Capacitance 890 V GS = 0V C oss Output Capacitance 220 V DS = 25V C rss Reverse Transfer Capacitance 46 pf ƒ =.0MHz C oss Output Capacitance 460 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 95 V GS = 0V, V DS = 20V, ƒ =.0MHz C oss eff. Effective Output Capacitance 200 V GS = 0V, V DS = 0V to 20V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 70 mj I AR Avalanche Current 4 A E AR Repetitive Avalanche Energy 4 mj Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 24 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 96 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.5 V T J = 25 C, I S = 4A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 4A Q rr Reverse RecoveryCharge 450 nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2 www.irf.com
I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRFR24N5D/IRFU24N5D 00 0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0V 0. 5.0V 0.0 0.00 20µs PULSE WIDTH Tj = 25 C 0. 0 V DS, Drain-to-Source Voltage (V) 0. 20µs PULSE WIDTH Tj = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 0 3.0 I D = 24A T J = 75 C 2.5 I D, Drain-to-Source Current (A) T = 25 J C V DS= 50V 20µs PULSE WIDTH 0. 4 6 8 2 4 6 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.0.5.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 0 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
I D, Drain-to-Source Current (A) C, Capacitance(pF) IRFR24N5D/IRFU24N5D 000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds C rss = C gd C oss = C ds C gd SHORTED 2 I = D 4A V DS V DS V DS = 20V = 75V = 30V 00 0 Ciss Coss Crss V GS, Gate-to-Source Voltage (V) 8 6 4 2 0 00 V DS, Drain-to-Source Voltage (V) 0 0 5 5 20 25 30 35 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 0 00 OPERATION IN THIS AREA LIMITED BY R DS (on) I SD, Reverse Drain Current (A) T J = 75 C T = 25 J C V GS = 0 V 0. 0.0 0.5.0.5 2.0 2.5 V SD,Source-to-Drain Voltage (V) 0 0. Tc = 25 C Tj = 75 C Single Pulse 0µsec msec msec 0 00 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
25 V DS R D 20 R G V GS D.U.T. - V DD I D, Drain Current (A) 5 V GS Pulse Width µs Duty Factor 0. % Fig a. Switching Time Test Circuit 5 V DS 90% 0 25 50 75 0 25 50 75 T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) P DM t t 2 Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc T C 0.0 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
5V 320 I D V DS L DRIVER 240 TOP BOTTOM 5.9A A 4A R G 20V tp Fig 2a. Unclamped Inductive Test Circuit tp D.U.T I AS 0.0Ω V (BR)DSS - V DD A E AS, Single Pulse Avalanche Energy (mj) 60 80 0 25 50 75 0 25 50 75 Starting Tj, Junction Temperature ( C) I AS Fig 2b. Unclamped Inductive Waveforms Fig 2c. Maximum Avalanche Energy Vs. Drain Current Current Regulator Same Type as D.U.T. Q G 50KΩ Q GS Q GD 2V.2µF.3µF D.U.T. V - DS V G V GS 3mA Charge I G I D Current Sampling Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFET Power MOSFETs www.irf.com 7
D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.25) 5.2 (.205) 6.73 (.265) 6.35 (.250) - A -.27 (.050) 0.88 (.035) 2.38 (.094) 2.9 (.086).4 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.08) 4.02 (.040).64 (.025).52 (.060).5 (.045) 2X.4 (.045) 0.76 (.030) 2 3 3X 6.22 (.245) 5.97 (.235) - B - 0.89 (.035) 0.64 (.025) 0.25 (.0) M A M B.42 (.4) 9.40 (.370) 6.45 (.245) 5.68 (.224) 0.5 (.020) M IN. 0.58 (.023) 0.46 (.08) LEAD ASSIGNMENTS - G A TE 2 - D R A IN 3 - S O U R CE 4 - D R A IN 2.28 (.090) 4.57 (.80) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 2 CONTROLLING DIMENSION : INCH. 3 C O N FO R M S TO JE D E C O U TLIN E TO -252 AA. 4 DIMENSIONS SHOW N ARE BEFORE SOLDER DIP, SOLDER DIP MAX. 0.6 (.006). D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR20 WITH ASSEMBLY LOT CODE 234 ASSEMBLED ON WW 6, 999 IN THE ASSEMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 96A 2 34 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 6 LINE A 8 www.irf.com
I-Pak (TO-25AA) Package Outline Dimensions are shown in millimeters (inches) 5.46 (.25) 5.2 (.205).52 (.060).5 (.045) 6.73 (.265) 6.35 (.250) - A - 4 6.22 (.245) 5.97 (.235).27 (.050) 0.88 (.035) 2.38 (.094) 2.9 (.086) 0.58 (.023) 0.46 (.08) 6.45 (.245) 5.68 (.224) LEAD ASSIGNMENTS - G ATE 2 - D RA IN 3 - SOURCE 4 - D RA IN 2 3 - B - 2.28 (.090).9 (.075) 9.65 (.380) 8.89 (.350) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 2 CONTROLLING DIMENSION : INCH. 3 C O NF O R MS TO JEDE C O UTLINE TO -25 2AA. 4 D IM EN SIO N S S HO W N A R E BE FO RE SO L DE R D IP, SOLDER DIP MAX. 0.6 (.006). 3X.4 (.045) 0.76 (.030) 2.28 (.090) 2X 3X 0.89 (.035) 0.64 (.025) 0.25 (.0 ) M A M B.4 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.08) I-Pak (TO-25AA) Part Marking Information EXAMPLE: THIS IS AN IRFR20 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 9, 999 IN THE ASSEMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 99A 56 78 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 9 LINE A www.irf.com 9
D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOW N IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA-54. 3 INCH NOTES :. OUTLINE CONFORMS TO EIA-48. 6 mm Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L =.7mH R G = 25Ω, I AS = 4A. ƒ I SD 4A, di/dt 380A/µs, V DD V (BR)DSS, T J 75 C. Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. * When mounted on " square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q] market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information.03/02 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/