95GHz Receiver with Fundamental Frequency VCO and Static Frequency Divider in 65nm Digital CMOS Ekaterina Laskin, Mehdi Khanpour, Ricardo Aroca, Keith W. Tang, Patrice Garcia 1, Sorin P. Voinigescu University of Toronto, (1) STMicroelectronics Paper 9.1 1
Outline Motivation Circuit schematics Fabrication technology and passives Test setup Measurement results Conclusion Paper 9.1 2
Motivation / Applications DSB imaging / remote sensing receiver Receiver for 10+Gb/s data-rate communication Explore the capabilities of 65-nm CMOS W-band operation Technology scaling System integration Higher frequency better range resolution Paper 9.1 3
Receiver Block Diagram Fundamental-frequency VCO at 90GHz Fewer spurs on die Transformer-based signal distribution Low-loss, no DC power, small size Single-ended to differential conversion Bias & supply plane isolation Paper 9.1 4
Transformer-Feedback LNA [K.W. Tang, CICC 07] Transistor biased at J SOPT, sized to match R SOPT Transformer chosen to match Z IN Smaller devices for 50Ω match ( Z ) Re = Paper 9.1 5 IN g m k L P L S
Transformer-Feedback LNA 0.5pF 1.5V 1.5V 1.5V to mixer RF port [K.W. Tang, CICC 07] 0.5pF 20 24 40 RF in 20 24 40 1µm L P L S V B 2:1 0.5pF decoupling at every bias node in layout Provides a low-l short-circuit at these nodes Paper 9.1 6
Mixer and IF Buffer L G =60nm [D. Alldred, CSICS 06 K.W. Tang, CICC 07] broadband IF buffer 76-95GHz Gilbert cell mixer 120pH inductors NF & 2 nd harmonic LO reject Biasing through transformer center tap Paper 9.1 7
VCO Topology Need: VCO at 90 GHz fundamental Low phase noise High output power Distribute signal to mixer and divider From [K.W. Tang, CSICS 06]: 77 GHz Cross-coupled 137.5 Colpitts VCO 168.5 Choose: Quadrature Colpitts VCO at 90 GHz Buffers to equalize tank loading Paper 9.1 8
VCO Schematic 92pH 60fF 41pH P 58pH Control Control+ Q RDIFF 450pH 250fF R DIFF R QUAD 4 symmetrically coupled Colpitts VCOs VCO core: 0.2mA/μm, buffers: 0.3mA/μm Paper 9.1 9
VCO Analysis T-line T-line T-line T-line Z Z Z Z 11 12 13 12 Z Z Z Z 12 11 12 13 Z Z Z Z 13 12 11 12 Z Z Z Z 12 13 12 11 I I I I 1 2 3 4 = V V V V 1 2 3 4 Solution for quadrature oscillation mode: C 1 C VAR Z D Q 0 R S 2R QUAD 4R QUAD +2R DIFF Quad Odd Even Z T 0 2R 4R R T jx T R L P I I I I 1 2 3 4 = 1 j e e j e π 2 jπ 3π 2 I I I I 1 2 3 4 = 1 - j e e e π 2 - jπ 3π - j 2 Paper 9.1 10
Colpitts VCO Frequency C 1 =60fF, L=32pH NFET: 72 0.8μm 60nm C GS =0.75fF/μm C GD =0.4fF/μm C SB =0.65fF/μm Varactor: 34 0.8μm 60nm C VAR =24fF 41fF C B =0.7fF/μm C L =3fF Paper 9.1 11
Colpitts VCO Frequency f OSC Hand analysis Simulated (no extraction) Simulated (with extraction) Measured Upper limit 101 GHz 107.2 GHz 91.5 GHz 91.2 GHz Lower limit 96.7 GHz 100.2 GHz 88.4 GHz 88.2 GHz Accurate prediction by hand analysis Agreement between simulated & measured f OSC Paper 9.1 12
VCO and Buffers 150μm buffers buffers tank P 75μm 75μm 170μm Symmetry is maintained throughout VCO Paper 9.1 13
22μm Frequency Divider from VCO 100μm 200μm out Layout designed to minimize critical path delay Paper 9.1 14
Technology 65nm GP CMOS 300 300 ft, fmax (GHz) 250 200 150 100 50 0.02 f MAX f T V DS =1V 0.1 1 J DS (ma/μm) 250 200 150 100 f MAX =280GHz, f T =195GHz Device: 80 60nm 1μm, one side gate contact 7 metal backend, Metal-Over-Metal capacitors 2 ft, fmax (GHz) 50 0 f MAX 0 0.2 0.4 0.6 0.8 1 1.2 V DS (V) Paper 9.1 15 f T V GS =0.65V
Measured varactor at 94 GHz 9 45 50 fingers 8 40 Q 7 6 Q C VAR 35 30 CVAR (ff) 5 25 4 20-0.6-0.3 0 0.3 0.6 0.9 1.2 V GS (V) L G =60nm, W total =27.5μm, C VAR =1.53fF/μm 2 C variation: 25fF 42fF, Q: 6 8 at 94 GHz G SD Paper 9.1 16
Measured 24-µm 1:1 transformer S11, S22, S21 (db) s w + port 2 d port 1 center tap + d=24μm w=2μm s=1μm Transformer: VCO & Div VCO & Mixer LNA & Mixer MAG < -1.5dB Paper 9.1 17
Receiver Die Photo 600μm 1095μm Paper 9.1 18
Bias Distribution Metal mesh distributes ground, V DD, bias to all cells Substrate contacts, distributed decoupling, low R, L Meets all density rules Paper 9.1 19
Measurement Setup SSB gain Linearity Phase noise Tuning range Divider DSB NF DSB gain Paper 9.1 20
DC Power Consumption Block Current (ma) Supply (V) Power (mw) LNA 24 36 Mixer 9 1.5 13.5 50-Ω IF amplifier 19 28.5 Quadrature VCO 48 57.6 4 VCO buffers Divider 24 18.6 1.2 28.8 22.4 Divider 50-Ω driver 16.3 19.6 Total: 206.4 (158) Paper 9.1 21
VCO Tuning & Output Power VCO Frequency (GHz) VCO Output Power (dbm) 88.2 91.2GHz tuning range for all temperatures +3dBm to -4dBm total VCO output power Paper 9.1 22
Measured VCO Phase Noise -95dBc/Hz at 1MHz offset Measured at 90.3GHz 100 averages Paper 9.1 23
SSB Receiver Conversion Gain Differential Gain (db) 15 10 5 0-5 Gain S 11-10 -15-20 -25-30 S11 (db) 1.2V 1.5V 1.8V S 11 VCO = 89GHz -10-35 75 80 85 90 95 100 105 RF (GHz) 12 db differential gain with nominal bias S 11 better than -15 db over the BW Paper 9.1 24
Measured Receiver DSB NF Differential Gain (db) 18 16 14 12 10 8 6 4 2 0 Gain NF 0 3 6 9 12 15 18 IF (GHz) 6 9.5 db DSB NF Gain confirmed by NF measurement 22 20 18 16 14 12 10 8 6 4 DSB NF (db) VCO = 89GHz Paper 9.1 25
Measured Rx Optimal Bias 15 13 11 9 7 5 3 15 13 11 9 7 5 3 25 C 50 C 75 C LO=89GHz IF = 6 GHz 1 0 0.1 0.2 0.3 0.4 0.5 Current Density (ma/μm) 1 0 0.1 0.2 0.3 0.4 0.5 Current Density (ma/μm) Current swept in the 1 st LNA stage J GAIN, OPT > J NFMIN, OPT, insensitive to V T, I bias variation Paper 9.1 26
Measured Receiver Linearity Differential Gain (db) Output Power (dbm) RF = 85 GHz, LO = 89 GHz Input P 1-dB = -18 dbm Paper 9.1 27
Measured Static Divider Operation 45.6 45.4 45.2 45 44.8 44.6 44.4 44.2 25 C 50 C 44 88 88.5 89 89.5 90 90.5 91 VCO Frequency (GHz) Measured by observing the VCO and divider signals simultaneously Paper 9.1 28
Comparison to Previous Work: 60G Spec. Integration level 3-dB BW Power Gain VCO Freq. VCO PN @ 1MHz off. DC Power Supply Die Area Technology This Work fundamental VCO, LNA, mixer, 50-Ω IF amp, static divider 76 95 GHz 12.5 db NF 7 db 5-6.7 db 10.4 Input P 1-dB -18 dbm -36 dbm -15.8 dbm 88.3-91.3GHz -95 dbc/hz (at 90.3GHz) 206.4 mw 1.2 V / 1.5 V 0.66 mm 2 65-nm GP CMOS B. Floyd, ISSCC06 LNA, superheterodyne receiver, PLL, BB amp. 59 64 GHz 38-40 db 16.8-18.3GHz -90dBc/Hz 527 mw 2.7 V 5.78 mm 2 0.13µm SiGe BiCMOS S. Emami, ISSCC07 VCO, doubler, LNA, mixer, IF amplifier 57 63 GHz 11.8 db 28.4-29.4GHz -93dBc/Hz (at 29GHz) 76.8 mw 1.2V 3.8 mm 2 0.13μm CMOS Paper 9.1 29
Comparison to Previous Work: 77G Spec. Integration level 3-dB BW Power Gain NF Input P 1-dB VCO Freq. VCO PN @ 1MHz off. DC Power Supply Die Area This Work fundamental VCO, LNA, mixer, 50-Ω IF amp, static 2 76 95 GHz 12.5 db 7 db -18 dbm 88.3-91.3GHz -95 dbc/hz (at 90.3GHz) 206.4 mw 1.2 V / 1.5 V 0.66 mm 2 Babakhani, ISSCC 06 VCO, LNA, mixer, injection locked divider 76 80 GHz 35 db 8-10 db -27.5 dbm 52 GHz -95 dbc/hz (at 54GHz) 186 mw 3.3 / 5 V 6.46 mm 2 Nicolson, MTT 08 VCO, mixer, LNA, 50-Ω IF amplifier, static 64 85 96 GHz 31 db 5.2 db -30 dbm 76 GHz -99 dbc/hz 700 mw 1.8 / 2.5 / 3.3 V 1.02 mm 2 Technology 65-nm GP CMOS 250 f MAX SiGe HBT 230/300GHz f T /f MAX 0.13µm SiGe HBT Paper 9.1 30
Conclusion 76-95GHz receiver with 90-GHz VCO and divider Clock distribution using transformers Unique bias distribution & isolation scheme Operation verified up to 100 C Highest-frequency CMOS receiver (for now) W-band receiver integration demonstrated Paper 9.1 31
Acknowledgements Alexander Tomkins for varactor measurements Kenneth Yau for transistor measurements STMicroelectronics for fabrication Christophe Garnier and Bernard Sautreuil for technology access NSERC for funding Paper 9.1 32